1#[doc = "Reader of register C4"]
2pub type R = crate::R<u8, super::C4>;
3#[doc = "Writer for register C4"]
4pub type W = crate::W<u8, super::C4>;
5#[doc = "Register C4 `reset()`'s with value 0"]
6impl crate::ResetValue for super::C4 {
7 type Type = u8;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `BRFA`"]
14pub type BRFA_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `BRFA`"]
16pub struct BRFA_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> BRFA_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u8) -> &'a mut W {
23 self.w.bits = (self.w.bits & !0x1f) | ((value as u8) & 0x1f);
24 self.w
25 }
26}
27#[doc = "10-bit Mode select\n\nValue on reset: 0"]
28#[derive(Clone, Copy, Debug, PartialEq)]
29pub enum M10_A {
30 #[doc = "0: The parity bit is the ninth bit in the serial transmission."]
31 _0 = 0,
32 #[doc = "1: The parity bit is the tenth bit in the serial transmission."]
33 _1 = 1,
34}
35impl From<M10_A> for bool {
36 #[inline(always)]
37 fn from(variant: M10_A) -> Self {
38 variant as u8 != 0
39 }
40}
41#[doc = "Reader of field `M10`"]
42pub type M10_R = crate::R<bool, M10_A>;
43impl M10_R {
44 #[doc = r"Get enumerated values variant"]
45 #[inline(always)]
46 pub fn variant(&self) -> M10_A {
47 match self.bits {
48 false => M10_A::_0,
49 true => M10_A::_1,
50 }
51 }
52 #[doc = "Checks if the value of the field is `_0`"]
53 #[inline(always)]
54 pub fn is_0(&self) -> bool {
55 *self == M10_A::_0
56 }
57 #[doc = "Checks if the value of the field is `_1`"]
58 #[inline(always)]
59 pub fn is_1(&self) -> bool {
60 *self == M10_A::_1
61 }
62}
63#[doc = "Write proxy for field `M10`"]
64pub struct M10_W<'a> {
65 w: &'a mut W,
66}
67impl<'a> M10_W<'a> {
68 #[doc = r"Writes `variant` to the field"]
69 #[inline(always)]
70 pub fn variant(self, variant: M10_A) -> &'a mut W {
71 {
72 self.bit(variant.into())
73 }
74 }
75 #[doc = "The parity bit is the ninth bit in the serial transmission."]
76 #[inline(always)]
77 pub fn _0(self) -> &'a mut W {
78 self.variant(M10_A::_0)
79 }
80 #[doc = "The parity bit is the tenth bit in the serial transmission."]
81 #[inline(always)]
82 pub fn _1(self) -> &'a mut W {
83 self.variant(M10_A::_1)
84 }
85 #[doc = r"Sets the field bit"]
86 #[inline(always)]
87 pub fn set_bit(self) -> &'a mut W {
88 self.bit(true)
89 }
90 #[doc = r"Clears the field bit"]
91 #[inline(always)]
92 pub fn clear_bit(self) -> &'a mut W {
93 self.bit(false)
94 }
95 #[doc = r"Writes raw bits to the field"]
96 #[inline(always)]
97 pub fn bit(self, value: bool) -> &'a mut W {
98 self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u8) & 0x01) << 5);
99 self.w
100 }
101}
102#[doc = "Match Address Mode Enable 2\n\nValue on reset: 0"]
103#[derive(Clone, Copy, Debug, PartialEq)]
104pub enum MAEN2_A {
105 #[doc = "0: All data received is transferred to the data buffer if MAEN1 is cleared."]
106 _0 = 0,
107 #[doc = "1: All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816\\[ISO7816E\\]
108is set/enabled."]
109 _1 = 1,
110}
111impl From<MAEN2_A> for bool {
112 #[inline(always)]
113 fn from(variant: MAEN2_A) -> Self {
114 variant as u8 != 0
115 }
116}
117#[doc = "Reader of field `MAEN2`"]
118pub type MAEN2_R = crate::R<bool, MAEN2_A>;
119impl MAEN2_R {
120 #[doc = r"Get enumerated values variant"]
121 #[inline(always)]
122 pub fn variant(&self) -> MAEN2_A {
123 match self.bits {
124 false => MAEN2_A::_0,
125 true => MAEN2_A::_1,
126 }
127 }
128 #[doc = "Checks if the value of the field is `_0`"]
129 #[inline(always)]
130 pub fn is_0(&self) -> bool {
131 *self == MAEN2_A::_0
132 }
133 #[doc = "Checks if the value of the field is `_1`"]
134 #[inline(always)]
135 pub fn is_1(&self) -> bool {
136 *self == MAEN2_A::_1
137 }
138}
139#[doc = "Write proxy for field `MAEN2`"]
140pub struct MAEN2_W<'a> {
141 w: &'a mut W,
142}
143impl<'a> MAEN2_W<'a> {
144 #[doc = r"Writes `variant` to the field"]
145 #[inline(always)]
146 pub fn variant(self, variant: MAEN2_A) -> &'a mut W {
147 {
148 self.bit(variant.into())
149 }
150 }
151 #[doc = "All data received is transferred to the data buffer if MAEN1 is cleared."]
152 #[inline(always)]
153 pub fn _0(self) -> &'a mut W {
154 self.variant(MAEN2_A::_0)
155 }
156 #[doc = "All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816\\[ISO7816E\\]
157is set/enabled."]
158 #[inline(always)]
159 pub fn _1(self) -> &'a mut W {
160 self.variant(MAEN2_A::_1)
161 }
162 #[doc = r"Sets the field bit"]
163 #[inline(always)]
164 pub fn set_bit(self) -> &'a mut W {
165 self.bit(true)
166 }
167 #[doc = r"Clears the field bit"]
168 #[inline(always)]
169 pub fn clear_bit(self) -> &'a mut W {
170 self.bit(false)
171 }
172 #[doc = r"Writes raw bits to the field"]
173 #[inline(always)]
174 pub fn bit(self, value: bool) -> &'a mut W {
175 self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u8) & 0x01) << 6);
176 self.w
177 }
178}
179#[doc = "Match Address Mode Enable 1\n\nValue on reset: 0"]
180#[derive(Clone, Copy, Debug, PartialEq)]
181pub enum MAEN1_A {
182 #[doc = "0: All data received is transferred to the data buffer if MAEN2 is cleared."]
183 _0 = 0,
184 #[doc = "1: All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816\\[ISO7816E\\]
185is set/enabled."]
186 _1 = 1,
187}
188impl From<MAEN1_A> for bool {
189 #[inline(always)]
190 fn from(variant: MAEN1_A) -> Self {
191 variant as u8 != 0
192 }
193}
194#[doc = "Reader of field `MAEN1`"]
195pub type MAEN1_R = crate::R<bool, MAEN1_A>;
196impl MAEN1_R {
197 #[doc = r"Get enumerated values variant"]
198 #[inline(always)]
199 pub fn variant(&self) -> MAEN1_A {
200 match self.bits {
201 false => MAEN1_A::_0,
202 true => MAEN1_A::_1,
203 }
204 }
205 #[doc = "Checks if the value of the field is `_0`"]
206 #[inline(always)]
207 pub fn is_0(&self) -> bool {
208 *self == MAEN1_A::_0
209 }
210 #[doc = "Checks if the value of the field is `_1`"]
211 #[inline(always)]
212 pub fn is_1(&self) -> bool {
213 *self == MAEN1_A::_1
214 }
215}
216#[doc = "Write proxy for field `MAEN1`"]
217pub struct MAEN1_W<'a> {
218 w: &'a mut W,
219}
220impl<'a> MAEN1_W<'a> {
221 #[doc = r"Writes `variant` to the field"]
222 #[inline(always)]
223 pub fn variant(self, variant: MAEN1_A) -> &'a mut W {
224 {
225 self.bit(variant.into())
226 }
227 }
228 #[doc = "All data received is transferred to the data buffer if MAEN2 is cleared."]
229 #[inline(always)]
230 pub fn _0(self) -> &'a mut W {
231 self.variant(MAEN1_A::_0)
232 }
233 #[doc = "All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816\\[ISO7816E\\]
234is set/enabled."]
235 #[inline(always)]
236 pub fn _1(self) -> &'a mut W {
237 self.variant(MAEN1_A::_1)
238 }
239 #[doc = r"Sets the field bit"]
240 #[inline(always)]
241 pub fn set_bit(self) -> &'a mut W {
242 self.bit(true)
243 }
244 #[doc = r"Clears the field bit"]
245 #[inline(always)]
246 pub fn clear_bit(self) -> &'a mut W {
247 self.bit(false)
248 }
249 #[doc = r"Writes raw bits to the field"]
250 #[inline(always)]
251 pub fn bit(self, value: bool) -> &'a mut W {
252 self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u8) & 0x01) << 7);
253 self.w
254 }
255}
256impl R {
257 #[doc = "Bits 0:4 - Baud Rate Fine Adjust"]
258 #[inline(always)]
259 pub fn brfa(&self) -> BRFA_R {
260 BRFA_R::new((self.bits & 0x1f) as u8)
261 }
262 #[doc = "Bit 5 - 10-bit Mode select"]
263 #[inline(always)]
264 pub fn m10(&self) -> M10_R {
265 M10_R::new(((self.bits >> 5) & 0x01) != 0)
266 }
267 #[doc = "Bit 6 - Match Address Mode Enable 2"]
268 #[inline(always)]
269 pub fn maen2(&self) -> MAEN2_R {
270 MAEN2_R::new(((self.bits >> 6) & 0x01) != 0)
271 }
272 #[doc = "Bit 7 - Match Address Mode Enable 1"]
273 #[inline(always)]
274 pub fn maen1(&self) -> MAEN1_R {
275 MAEN1_R::new(((self.bits >> 7) & 0x01) != 0)
276 }
277}
278impl W {
279 #[doc = "Bits 0:4 - Baud Rate Fine Adjust"]
280 #[inline(always)]
281 pub fn brfa(&mut self) -> BRFA_W {
282 BRFA_W { w: self }
283 }
284 #[doc = "Bit 5 - 10-bit Mode select"]
285 #[inline(always)]
286 pub fn m10(&mut self) -> M10_W {
287 M10_W { w: self }
288 }
289 #[doc = "Bit 6 - Match Address Mode Enable 2"]
290 #[inline(always)]
291 pub fn maen2(&mut self) -> MAEN2_W {
292 MAEN2_W { w: self }
293 }
294 #[doc = "Bit 7 - Match Address Mode Enable 1"]
295 #[inline(always)]
296 pub fn maen1(&mut self) -> MAEN1_W {
297 MAEN1_W { w: self }
298 }
299}