jh71xx-pac 0.11.1

Peripheral access crate for the JH71xx SoCs
Documentation 
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#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
    _reserved0: [u8; 0x04],
    priority: [Priority; 136],
    _reserved1: [u8; 0x0ddc],
    pending: [Pending; 5],
    _reserved2: [u8; 0x0fec],
    enable: [Enable; 5],
    _reserved3: [u8; 0x001f_dd80],
    threshold_claim: [ThresholdClaim; 5],
}
impl RegisterBlock {
    #[doc = "0x04..0x224 - RISC-V PLIC Interrupt Source Priority."]
    #[inline(always)]
    pub const fn priority(&self, n: usize) -> &Priority {
        &self.priority[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x04..0x224 - RISC-V PLIC Interrupt Source Priority."]
    #[inline(always)]
    pub fn priority_iter(&self) -> impl Iterator<Item = &Priority> {
        self.priority.iter()
    }
    #[doc = "0x1000..0x1014 - RISC-V PLIC Pending: 32-bit register indicating if there is a pending interrupt, e.g. pending\\[0\\]\\[0\\]
is interrupt 0, pending\\[0\\]\\[31\\]
is interrupt 31, pending\\[1\\]\\[0\\]
is interrupt 32."]
    #[inline(always)]
    pub const fn pending(&self, n: usize) -> &Pending {
        &self.pending[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x1000..0x1014 - RISC-V PLIC Pending: 32-bit register indicating if there is a pending interrupt, e.g. pending\\[0\\]\\[0\\]
is interrupt 0, pending\\[0\\]\\[31\\]
is interrupt 31, pending\\[1\\]\\[0\\]
is interrupt 32."]
    #[inline(always)]
    pub fn pending_iter(&self) -> impl Iterator<Item = &Pending> {
        self.pending.iter()
    }
    #[doc = "0x2000..0x2280 - PLIC interrupt enable registers (per-HART)"]
    #[inline(always)]
    pub const fn enable(&self, n: usize) -> &Enable {
        &self.enable[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x2000..0x2280 - PLIC interrupt enable registers (per-HART)"]
    #[inline(always)]
    pub fn enable_iter(&self) -> impl Iterator<Item = &Enable> {
        self.enable.iter()
    }
    #[doc = "0x200000..0x205000 - PLIC threshold and claim_complete registers"]
    #[inline(always)]
    pub const fn threshold_claim(&self, n: usize) -> &ThresholdClaim {
        &self.threshold_claim[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x200000..0x205000 - PLIC threshold and claim_complete registers"]
    #[inline(always)]
    pub fn threshold_claim_iter(&self) -> impl Iterator<Item = &ThresholdClaim> {
        self.threshold_claim.iter()
    }
}
#[doc = "priority (rw) register accessor: RISC-V PLIC Interrupt Source Priority.\n\nYou can [`read`](crate::Reg::read) this register and get [`priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority`]
module"]
#[doc(alias = "priority")]
pub type Priority = crate::Reg<priority::PrioritySpec>;
#[doc = "RISC-V PLIC Interrupt Source Priority."]
pub mod priority;
#[doc = "pending (rw) register accessor: RISC-V PLIC Pending: 32-bit register indicating if there is a pending interrupt, e.g. pending\\[0\\]\\[0\\]
is interrupt 0, pending\\[0\\]\\[31\\]
is interrupt 31, pending\\[1\\]\\[0\\]
is interrupt 32.\n\nYou can [`read`](crate::Reg::read) this register and get [`pending::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pending::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending`]
module"]
#[doc(alias = "pending")]
pub type Pending = crate::Reg<pending::PendingSpec>;
#[doc = "RISC-V PLIC Pending: 32-bit register indicating if there is a pending interrupt, e.g. pending\\[0\\]\\[0\\]
is interrupt 0, pending\\[0\\]\\[31\\]
is interrupt 31, pending\\[1\\]\\[0\\]
is interrupt 32."]
pub mod pending;
#[doc = "PLIC interrupt enable registers (per-HART)"]
pub use self::enable::Enable;
#[doc = r"Cluster"]
#[doc = "PLIC interrupt enable registers (per-HART)"]
pub mod enable;
#[doc = "PLIC threshold and claim_complete registers"]
pub use self::threshold_claim::ThresholdClaim;
#[doc = r"Cluster"]
#[doc = "PLIC threshold and claim_complete registers"]
pub mod threshold_claim;