jh7110_vf2_13b_pac/syscrg/
clk_u1_i2stx_4ch1_bclk_mst.rs

1#[doc = "Register `clk_u1_i2stx_4ch1_bclk_mst` reader"]
2pub type R = crate::R<CLK_U1_I2STX_4CH1_BCLK_MST_SPEC>;
3#[doc = "Register `clk_u1_i2stx_4ch1_bclk_mst` writer"]
4pub type W = crate::W<CLK_U1_I2STX_4CH1_BCLK_MST_SPEC>;
5#[doc = "Field `clk_divcfg` reader - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"]
6pub type CLK_DIVCFG_R = crate::FieldReader<u32>;
7#[doc = "Field `clk_divcfg` writer - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"]
8pub type CLK_DIVCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
9#[doc = "Field `clk_icg` reader - 1: Clock enable, 0: Clock disable"]
10pub type CLK_ICG_R = crate::BitReader;
11#[doc = "Field `clk_icg` writer - 1: Clock enable, 0: Clock disable"]
12pub type CLK_ICG_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bits 0:23 - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"]
15    #[inline(always)]
16    pub fn clk_divcfg(&self) -> CLK_DIVCFG_R {
17        CLK_DIVCFG_R::new(self.bits & 0x00ff_ffff)
18    }
19    #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"]
20    #[inline(always)]
21    pub fn clk_icg(&self) -> CLK_ICG_R {
22        CLK_ICG_R::new(((self.bits >> 31) & 1) != 0)
23    }
24}
25impl W {
26    #[doc = "Bits 0:23 - Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4"]
27    #[inline(always)]
28    #[must_use]
29    pub fn clk_divcfg(&mut self) -> CLK_DIVCFG_W<CLK_U1_I2STX_4CH1_BCLK_MST_SPEC> {
30        CLK_DIVCFG_W::new(self, 0)
31    }
32    #[doc = "Bit 31 - 1: Clock enable, 0: Clock disable"]
33    #[inline(always)]
34    #[must_use]
35    pub fn clk_icg(&mut self) -> CLK_ICG_W<CLK_U1_I2STX_4CH1_BCLK_MST_SPEC> {
36        CLK_ICG_W::new(self, 31)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "U1 Clock I2S TX 1 BCLK MST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_u1_i2stx_4ch1_bclk_mst::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_u1_i2stx_4ch1_bclk_mst::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
50pub struct CLK_U1_I2STX_4CH1_BCLK_MST_SPEC;
51impl crate::RegisterSpec for CLK_U1_I2STX_4CH1_BCLK_MST_SPEC {
52    type Ux = u32;
53}
54#[doc = "`read()` method returns [`clk_u1_i2stx_4ch1_bclk_mst::R`](R) reader structure"]
55impl crate::Readable for CLK_U1_I2STX_4CH1_BCLK_MST_SPEC {}
56#[doc = "`write(|w| ..)` method takes [`clk_u1_i2stx_4ch1_bclk_mst::W`](W) writer structure"]
57impl crate::Writable for CLK_U1_I2STX_4CH1_BCLK_MST_SPEC {
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
60}
61#[doc = "`reset()` method sets clk_u1_i2stx_4ch1_bclk_mst to value 0"]
62impl crate::Resettable for CLK_U1_I2STX_4CH1_BCLK_MST_SPEC {
63    const RESET_VALUE: Self::Ux = 0;
64}
jh7110_vf2_13b_pac/syscrg/clk_u1_i2stx_4ch1_bclk_mst.rs

jh7110_vf2_13b_pac/syscrg/
clk_u1_i2stx_4ch1_bclk_mst.rs
