1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
use super::opcode::Opcode;
use super::environment::Environment;
use super::registers::{Flag, Reg8};
#[derive(Copy, Clone)]
pub enum ShiftMode {
Arithmetic,
Logical,
Rotate,
RotateCarry
}
#[derive(Copy, Clone)]
pub enum ShiftDir {
Left,
Right
}
pub fn build_rot_r(r: Reg8, (dir, mode, name): (ShiftDir, ShiftMode, &str), fast: bool, indexed: bool) -> Opcode {
let full_name = if indexed {
format!("LD {r}, {name} {}", Reg8::_HL)
} else {
let separator = if fast {""} else {" "};
format!("{name}{separator}{r}")
};
Opcode::new(
full_name,
move |env: &mut Environment| {
let mut v = if indexed {
env.reg8_ext(Reg8::_HL)
} else {
env.reg8_ext(r)
};
let carry = match dir {
ShiftDir::Left => {
let upper_bit = v >= 0x80;
v <<= 1;
let set_lower_bit = match mode {
ShiftMode::Arithmetic => false, // always 0 in bit 0
ShiftMode::Logical => true, // always 1 in bit 0
ShiftMode::Rotate => env.state.reg.get_flag(Flag::C), // carry in bit 0
ShiftMode::RotateCarry => upper_bit, // bit 7 moves to bit 0
};
if set_lower_bit { // bit 0 is 0 already
v |= 1;
}
upper_bit
},
ShiftDir::Right => {
let upper_bit = v >= 0x80;
let lower_bit = (v & 1) == 1;
v >>= 1;
let set_upper_bit = match mode {
ShiftMode::Arithmetic => upper_bit, // extend bit 7
ShiftMode::Logical => false, // always 0 in bit 7
ShiftMode::Rotate => env.state.reg.get_flag(Flag::C), // carry in bit 0
ShiftMode::RotateCarry => lower_bit, // bit 0 goes to bit 7
};
if set_upper_bit { // bit 7 is 0 already
v |= 0x80;
}
lower_bit
}
};
if indexed && r != Reg8::_HL {
env.set_reg(Reg8::_HL, v);
}
env.set_reg(r, v);
env.state.reg.put_flag(Flag::C, carry);
env.state.reg.update_hn_flags(false, false);
if fast {
env.state.reg.update_undocumented_flags(v);
} else {
env.state.reg.update_bits_in_flags(v);
}
}
)
}
pub fn build_bit_r(n: u8, r: Reg8) -> Opcode {
Opcode::new(
format!("BIT {n}, {r}"),
move |env: &mut Environment| {
let v = env.reg8_ext(r);
let z = v & (1<<n);
env.state.reg.put_flag(Flag::S, (z & 0x80) != 0);
env.state.reg.put_flag(Flag::Z, z == 0);
env.state.reg.put_flag(Flag::P, z == 0);
env.state.reg.set_flag(Flag::H);
env.state.reg.clear_flag(Flag::N); // BIT is Z80 only
if r == Reg8::_HL {
// Exceptions for (IX+d) TUZD-4-1
/* With the BIT n,(IX+d) instructions, the flags behave just
like the BIT n,r instruction, except for YF and XF. These are
not copied from the result but from something completely
different, namely bit 5 and 3 of the high byte of IX+d (so IX
plus the displacement).
*/
let address = env.index_address();
env.state.reg.update_undocumented_flags((address >> 8) as u8);
// Exceptions for (HL) TUZD-4-1
/* Things get more bizarre with the BIT n,(HL)
instruction. Again, except for YF and XF the flags
are the same. YF and XF are copied from some sort
of internal register */
// Not implemented. Just done the same than for (IX+d)
} else {
env.state.reg.update_undocumented_flags(v); // TUZD-4.1, copy bits from reg
}
}
)
}
pub fn build_set_res_r(bit: u8, r: Reg8, value: bool) -> Opcode {
let name = if value {"SET"} else {"RES"};
Opcode::new(
format!("{name} {bit}, {r}"),
move |env: &mut Environment| {
let mut v = env.reg8_ext(r);
if value {
v |= 1<<bit;
} else {
v &= !(1<<bit);
}
env.set_reg(r, v);
}
)
}
pub fn build_indexed_set_res_r(bit: u8, r: Reg8, value: bool) -> Opcode {
let name = if value {"SET"} else {"RES"};
Opcode::new(
format!("LD {}, {} {}, {}", r, name, bit, Reg8::_HL),
move |env: &mut Environment| {
/*
An instruction such as LD r, RES b, (IX+d) should be interpreted as
"attempt to reset bit b of the byte at (IX+d), and copy the result
to register r, even the new byte cannot be written at the said
address (e.g. when it points to a ROM location).
*/
let mut v = env.reg8_ext(Reg8::_HL);
if value {
v |= 1<<bit;
} else {
v &= !(1<<bit);
}
env.set_reg(Reg8::_HL, v);
if r != Reg8::_HL {
env.set_reg(r, v);
}
}
)
}
pub fn build_cpl() -> Opcode {
Opcode::new(
"CPL".to_string(),
|env: &mut Environment| {
let mut v = env.state.reg.a();
v = !v;
env.state.reg.set_a(v);
env.state.reg.update_hn_flags(true, true);
env.state.reg.update_undocumented_flags(v);
}
)
}
pub fn build_scf() -> Opcode {
Opcode::new(
"SCF".to_string(),
|env: &mut Environment| {
let a = env.state.reg.a();
env.state.reg.set_flag(Flag::C);
env.state.reg.update_hn_flags(false, false);
env.state.reg.update_undocumented_flags(a);
}
)
}
pub fn build_ccf() -> Opcode {
Opcode::new(
"CCF".to_string(),
|env: &mut Environment| {
let a = env.state.reg.a();
let c = env.state.reg.get_flag(Flag::C);
env.state.reg.put_flag(Flag::C, !c);
env.state.reg.update_hn_flags(c, false);
env.state.reg.update_undocumented_flags(a);
}
)
}
pub fn build_rxd(dir: ShiftDir, name: &str) -> Opcode {
Opcode::new(
name.to_string(),
move |env: &mut Environment| {
let mut a = env.state.reg.a();
let mut phl = env.reg8_ext(Reg8::_HL);
// a = 0xWX, phl = 0xYZ
match dir {
ShiftDir::Left => {
// a= 0xWY, phl = 0xZX
let temp = (a & 0xf0) | (phl >> 4);
phl = (phl << 4) | (a & 0x0f);
a = temp;
},
ShiftDir::Right => {
// a= 0xWZ, phl = 0xXY
let temp = (a & 0xf0) | (phl & 0x0f);
phl = (a << 4) | (phl >> 4);
a = temp;
}
}
env.state.reg.set_a(a);
env.set_reg(Reg8::_HL, phl);
env.state.reg.update_bits_in_flags(a);
}
)
}