iridia-dxbc 0.3.0

Translate Direct3D Shader Model 4 and 5 bytecode (DXBC, fxc output) to naga modules, for WGSL or SPIR-V output
Documentation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
//! Reading and writing DXBC operands: registers as four raw lanes, source swizzles and modifiers, write masks.

use iridia::build::{Kind, Val, Width};
use naga::{Expression as E, MathFunction as Mf, UnaryOperator as Uo};

use super::Lift;
use super::resources::lanes_of;
use crate::Result;
use dxbc_reader::decode::{Index, Operand, Register, Selection};

/// A lane number as a `u8`: a lane is one of at most four.
pub(super) fn lane_u8(n: usize) -> u8 {
    u8::try_from(n).unwrap_or(u8::MAX)
}

/// Component `lane` of four, where a swizzle's lane selectors are two bits wide.
pub(super) fn of_four<T: Copy + Default>(four: [T; 4], lane: u8) -> T {
    four.get(usize::from(lane)).copied().unwrap_or_default()
}

/// An instruction's operand by position. `Lift::instruction` checks the operand count against the opcode's (`arity`) before
/// any is read, so the error is the guard of a lookup that cannot miss, not a case of the input.
pub(super) trait OperandAt {
    fn operand(&self, n: usize) -> Result<&Operand>;
}
impl OperandAt for dxbc_reader::decode::Instruction {
    fn operand(&self, n: usize) -> Result<&Operand> {
        self.operands.get(n).ok_or_else(|| {
            crate::error(
                self.word,
                format!(
                    "{}: operand {n}, where the instruction has {}",
                    self.name(),
                    self.operands.len()
                ),
            )
        })
    }
}

impl Lift<'_> {
    /// Index `n` of an operand, which the decoder checked the register has the dimensions for.
    pub(super) fn index_of<'o>(&self, op: &'o Operand, n: usize) -> Result<&'o Index> {
        op.indices.get(n).ok_or_else(|| {
            crate::error(
                self.word,
                format!(
                    "{:?} has {} indices, where it is read at index {n}",
                    op.register,
                    op.indices.len()
                ),
            )
        })
    }

    /// The index of a register operand: its base plus the relative register, if any.
    pub(super) fn index_expr(&mut self, ix: &Index) -> Result<Val> {
        let base = self.b.lit_u(ix.base);
        match &ix.relative {
            None => Ok(base),
            Some(r) => {
                let relative = self.read(r, 1, Kind::U)?;
                Ok(self.b.binary(naga::BinaryOperator::Add, base, relative))
            }
        }
    }

    /// The `dcl_index_range` of input or output registers that holds register `base`: its first register and count.
    fn index_range(&self, output: bool, base: u32) -> Option<(u32, u32)> {
        self.setup
            .index_ranges
            .iter()
            .find(|(o, first, count)| *o == output && (*first..first.saturating_add(*count)).contains(&base))
            .map(|(_, first, count)| (*first, *count))
    }

    /// A register addressed by a computed index: the registers of its `dcl_index_range` as one array, indexed from the
    /// range's first; zero outside the range, as D3D reads past a declared one.
    fn relative_register(&mut self, op: &Operand, output: bool) -> Result<Val> {
        let Some((first, count)) = self.index_range(output, self.index_of(op, 0)?.base) else {
            return self.refuse("a register addressed by a computed index outside any dcl_index_range");
        };
        let index = self.index_expr(&self.index_of(op, 0)?.clone())?;
        let u4 = self.u4();
        let len = std::num::NonZeroU32::new(count).expect("a range holds registers");
        let ty = self.b.ty(naga::TypeInner::Array {
            base: u4,
            size: naga::ArraySize::Constant(len),
            stride: 16,
        });
        // the range's registers as a local array the index can address
        let array = self.b.local("range", ty);
        for (k, r) in (0u32..).zip(first..first.saturating_add(count)) {
            let value = match (if output {
                self.outputs.get(&r)
            } else {
                self.inputs.get(&r)
            })
            .copied()
            {
                Some(l) => {
                    let p = self.b.local_ptr(l);
                    self.b.load(p, Kind::U, Width::Four)
                }
                None => {
                    let z = self.b.lit_u(0);
                    self.b.splat(z, Width::Four)
                }
            };
            let pointer = self.b.local_ptr(array);
            let target = self.b.app(E::AccessIndex {
                base: pointer,
                index: k,
            });
            self.b.store(target, value);
        }
        let start = self.b.lit_u(first);
        let offset = self.b.binary(naga::BinaryOperator::Subtract, index, start);
        let length = self.b.lit_u(count);
        let inside = self.b.binary(naga::BinaryOperator::Less, offset, length);
        let zero = self.b.lit_u(0);
        let safe = self.b.select(inside, offset, zero);
        let pointer = self.b.local_ptr(array);
        let slot = self.b.app(E::Access {
            base: pointer,
            index: safe.expr,
        });
        let element = self.b.load(slot, Kind::U, Width::Four);
        let none = self.b.splat(zero, Width::Four);
        Ok(self.b.select(inside, element, none))
    }

    /// The register's four raw lanes as a `vec4<u32>`.
    fn reg_value(&mut self, op: &Operand) -> Result<Val> {
        match op.register {
            Register::Temp => {
                let Some(&local) = self.temps.get(self.index_of(op, 0)?.base as usize) else {
                    return self.refuse("a temporary beyond dcl_temps");
                };
                let p = self.b.local_ptr(local);
                Ok(self.b.load(p, Kind::U, Width::Four))
            }
            // a hull, domain or geometry program's inputs are indexed by control point (or vertex) first
            Register::Input | Register::InputControlPoint
                if op.indices.len() == 2
                    && matches!(
                        self.stage,
                        iridia::Stage::Hull | iridia::Stage::Domain | iridia::Stage::Geometry
                    ) =>
            {
                self.control_point_register(op, false)
            }
            Register::OutputControlPoint => self.control_point_register(op, true),
            Register::InputPatchConstant => self.patch_constant_register(op),
            Register::InputDomainPoint
            | Register::OutputControlPointId
            | Register::GsInstanceId
            | Register::ForkInstanceId
            | Register::JoinInstanceId => self.id_register(op.register),
            Register::Input => {
                if self.index_of(op, 0)?.relative.is_some() {
                    return self.relative_register(op, false);
                }
                let register = self.index_of(op, 0)?.base;
                let Some(&local) = self.inputs.get(&register) else {
                    return self.refuse(format!("input register v{register} is not in the signature"));
                };
                let p = self.b.local_ptr(local);
                Ok(self.b.load(p, Kind::U, Width::Four))
            }
            Register::Output => {
                if self.index_of(op, 0)?.relative.is_some() {
                    return self.relative_register(op, true);
                }
                let register = self.index_of(op, 0)?.base;
                let Some(&local) = self.outputs.get(&register) else {
                    return self.refuse(format!("output register o{register} is read but not declared"));
                };
                let p = self.b.local_ptr(local);
                Ok(self.b.load(p, Kind::U, Width::Four))
            }
            Register::IndexableTemp => {
                let Some(&(local, _)) = self.indexable.get(&self.index_of(op, 0)?.base) else {
                    return self.refuse("an undeclared indexable temporary");
                };
                let index = self.index_expr(&self.index_of(op, 1)?.clone())?;
                let p = self.b.local_ptr(local);
                let element = self.b.app(E::Access {
                    base: p,
                    index: index.expr,
                });
                Ok(self.b.load(element, Kind::U, Width::Four))
            }
            Register::Constant => {
                let slot = self.index_of(op, 0)?.base;
                let Some(&(g, rows)) = self.resources.constant_buffers.get(&slot) else {
                    return self.refuse(format!("cb{slot} is used but not declared"));
                };
                let index = self.index_expr(&self.index_of(op, 1)?.clone())?;
                if self.index_of(op, 1)?.relative.is_some() {
                    return Ok(self.guarded_load(g, index, Some(rows), Kind::U, Width::Four));
                }
                let p = self.b.global_ptr(g);
                let element = self.b.app(E::Access {
                    base: p,
                    index: index.expr,
                });
                Ok(self.b.load(element, Kind::U, Width::Four))
            }
            Register::ImmediateBuffer => {
                let Some((g, rows)) = self.resources.immediate else {
                    return self.refuse("the immediate constant buffer is used but not declared");
                };
                let index = self.index_expr(&self.index_of(op, 0)?.clone())?;
                if self.index_of(op, 0)?.relative.is_some() {
                    return Ok(self.guarded_load(g, index, Some(rows), Kind::U, Width::Four));
                }
                let p = self.b.global_ptr(g);
                let element = self.b.app(E::Access {
                    base: p,
                    index: index.expr,
                });
                Ok(self.b.load(element, Kind::U, Width::Four))
            }
            Register::PrimitiveId | Register::InputCoverage => {
                let local = if op.register == Register::PrimitiveId {
                    self.primitive_id
                } else {
                    self.input_coverage
                };
                let Some(local) = local else {
                    return self.refuse(format!("{:?} is used but not declared", op.register));
                };
                let p = self.b.local_ptr(local);
                Ok(self.b.load(p, Kind::U, Width::Four))
            }
            Register::ThreadId
            | Register::ThreadGroupId
            | Register::ThreadIdInGroup
            | Register::ThreadIdInGroupFlattened => {
                let system = match op.register {
                    Register::ThreadId => iridia::SystemValue::DispatchThreadId,
                    Register::ThreadGroupId => iridia::SystemValue::GroupId,
                    Register::ThreadIdInGroup => iridia::SystemValue::GroupThreadId,
                    _ => iridia::SystemValue::GroupIndex,
                };
                let Some(&local) = self.ids.get(&system) else {
                    return self.refuse(format!("{:?} is used but not declared", op.register));
                };
                let p = self.b.local_ptr(local);
                Ok(self.b.load(p, Kind::U, Width::Four))
            }
            other => self.refuse(format!("a source operand of register type {other:?}")),
        }
    }

    pub(super) fn dest_mask(&self, op: &Operand) -> u8 {
        match op.selection {
            Selection::Mask(m) => m,
            _ => 1,
        }
    }

    pub(super) fn read(&mut self, op: &Operand, mask: u8, kind: Kind) -> Result<Val> {
        self.read_lanes(op, &lanes_of(mask), kind)
    }

    /// The source for the destination lanes `lanes` (the swizzle is indexed by destination lane), as `kind`.
    pub(super) fn read_lanes(&mut self, op: &Operand, lanes: &[u8], kind: Kind) -> Result<Val> {
        if lanes.is_empty() {
            return self.refuse("a read of no lanes: the destination's write mask is empty");
        }
        let components: Vec<u8> = lanes
            .iter()
            .map(|&l| match op.selection {
                Selection::Swizzle(s) => Ok(of_four(s, l)),
                Selection::Scalar(c) => Ok(c),
                Selection::Mask(_) if op.register == Register::Immediate => Ok(l),
                _ => Err(()),
            })
            .collect::<std::result::Result<_, _>>()
            .or_else(|()| self.refuse("a numeric source without a swizzle"))?;
        if op.precision != 0 {
            self.notes
                .insert("min-precision operands are computed at 32 bits".into());
        }
        let mut value = if op.register == Register::Immediate {
            let parts: Vec<Val> = components
                .iter()
                .map(|&c| self.b.lit_bits(kind, of_four(op.immediate, c)))
                .collect();
            self.b.compose(&parts)
        } else {
            let base = self.reg_value(op)?;
            let picked = self.b.swizzle(base, &components);
            self.b.bitcast(picked, kind)
        };
        value = match (op.modifier, kind) {
            (0, _) => value,
            (1, Kind::F | Kind::I) => self.b.unary(Uo::Negate, value),
            (1, Kind::U) => {
                let signed = self.b.bitcast(value, Kind::I);
                let negated = self.b.unary(Uo::Negate, signed);
                self.b.bitcast(negated, Kind::U)
            }
            (2, Kind::F | Kind::I) => self.b.math(Mf::Abs, &[value]),
            (3, Kind::F) => {
                let magnitude = self.b.math(Mf::Abs, &[value]);
                self.b.unary(Uo::Negate, magnitude)
            }
            (m, k) => return self.refuse(format!("source modifier {m} on a {k:?} operand")),
        };
        Ok(value)
    }

    /// Write `v` to the destination operand's masked lanes; `saturate` clamps a float result first.
    pub(super) fn write(&mut self, op: &Operand, v: Val, saturate: bool) -> Result<()> {
        if op.register == Register::Null {
            return Ok(());
        }
        let mask = self.dest_mask(op);
        let lanes = lanes_of(mask);
        if lanes.is_empty() {
            return self.refuse("a destination whose write mask is empty");
        }
        let mut v = v;
        if v.width == Width::One
            && let Some(width) = Width::of_count(lanes.len()).filter(|&w| w > Width::One)
        {
            v = self.b.splat(v, width);
        }
        assert_eq!(
            usize::from(v.width),
            lanes.len(),
            "a result as wide as its destination mask (a lifter bug)"
        );
        if saturate {
            if v.kind != Kind::F {
                return self.refuse("saturation of a result that is not a float");
            }
            v = self.b.d3d_saturate(v);
        }
        let v = self.b.bitcast(v, Kind::U);
        let pointer = match op.register {
            Register::Temp => {
                let Some(&local) = self.temps.get(self.index_of(op, 0)?.base as usize) else {
                    return self.refuse("a temporary beyond dcl_temps");
                };
                self.b.local_ptr(local)
            }
            Register::Output => {
                if self.index_of(op, 0)?.relative.is_some() {
                    // a register of the range the index names: each is written where the index is its number
                    let Some((first, count)) = self.index_range(true, self.index_of(op, 0)?.base) else {
                        return self
                            .refuse("an output addressed by a computed index outside any dcl_index_range");
                    };
                    let index = self.index_expr(&self.index_of(op, 0)?.clone())?;
                    for r in first..first.saturating_add(count) {
                        let Some(&local) = self.outputs.get(&r) else {
                            continue;
                        };
                        let number = self.b.lit_u(r);
                        let here = self.b.binary(naga::BinaryOperator::Equal, index, number);
                        let lanes = lanes.clone();
                        self.b.when(here, |b| {
                            let pointer = b.local_ptr(local);
                            for (j, lane) in lanes.iter().enumerate() {
                                let component = b.lane(v, lane_u8(j));
                                let target = b.app(E::AccessIndex {
                                    base: pointer,
                                    index: u32::from(*lane),
                                });
                                b.store(target, component);
                            }
                        });
                    }
                    return Ok(());
                }
                let register = self.index_of(op, 0)?.base;
                let Some(&local) = self.outputs.get(&register) else {
                    return self.refuse(format!("a write to o{register}, which is not declared"));
                };
                self.b.local_ptr(local)
            }
            Register::IndexableTemp => {
                let Some(&(local, _)) = self.indexable.get(&self.index_of(op, 0)?.base) else {
                    return self.refuse("an undeclared indexable temporary");
                };
                let index = self.index_expr(&self.index_of(op, 1)?.clone())?;
                let p = self.b.local_ptr(local);
                self.b.app(E::Access {
                    base: p,
                    index: index.expr,
                })
            }
            Register::OutputDepth | Register::OutputDepthGreaterEqual | Register::OutputDepthLessEqual => {
                let Some(local) = self.depth else {
                    return self.refuse("the depth output is written but not declared");
                };
                self.b.local_ptr(local)
            }
            Register::OutputCoverage => {
                let Some(local) = self.coverage else {
                    return self.refuse("the coverage output is written but not declared");
                };
                self.b.local_ptr(local)
            }
            other => return self.refuse(format!("a destination operand of register type {other:?}")),
        };
        if mask == 15 {
            self.b.store(pointer, v);
        } else {
            for (j, lane) in lanes.iter().enumerate() {
                let component = self.b.lane(v, lane_u8(j));
                let target = self.b.app(E::AccessIndex {
                    base: pointer,
                    index: u32::from(*lane),
                });
                self.b.store(target, component);
            }
        }
        Ok(())
    }
}