infmachine 0.1.1

//! This module provides interface for internal processor state `proc_int_data`.
//!
//! This module provides structure that describes internal state of processor of machine
//! and reader of that internal states. The internal processor's state is called `proc_int_data`
//! and contains following fields:
//! * memory address,
//! * temporary buffer (`temp_buffer`),
//! * current position in memory address,
//! * current position in temporary buffer,
//! * current position in processor id,
//! * read main memory cell value (after read cycle stage),
//! * main memory cell value to write to this cell,
//! * main memory access
//! * read data part value (from some internal data like temp_buffer),
//! * data part access (access to internal data like temp_buffer or memory address),
//! * direction to move (change position) in internal data,
//! * indicator whether movement is dome,
//! * internal data kind (memory address, temp_buffer, proc_id),
//! * stop machine (STOP_MACHINE) indicator.
//!
//! The internal processor state stored in 32-bit words. The library allow to execute
//! machines with multiple million processors if machine configuration and
//! environment configuration will be optimized. Preferred configuration for massive
//! machines are:
//! * use small internal state,
//! * use 32-bit main memory addressing if possible,
//! * use small memory cells (not greater than 32-bit, preferred 16-bit or less),
//! * small temp buffer.
//!
//! Main memory address and temporary buffer are aligned to 32-bit words.
//! If main memory cell is 16-bit or less then it possible to save 1 32-bit word.
//! If data part has less than 22 bits in last 32-bit word, then it possible to save next
//! 32-bit word.

use crate::*;
use std::ops::Index;

/// Structure that describes internal processor state (proc_int_data).
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct ProcIntDataConfig {
    config: InfParMachineConfig,
    temp_buffer_len_in_bits: usize,
    entry_len: usize,       // in dwords
    mem_address_len: usize, // in dwords
    temp_buffer_len: usize, // in dwords
    temp_buffer_last_mask: u32,
    mem_address_pos_pos: usize,
    mem_cell_pos: usize,
    data_part_pos: usize,
    rest_pos: usize,
}

impl ProcIntDataConfig {
    /// Creates new proc_int_data configuration. It gets from machine configuration and
    /// environment configuration.
    pub fn new(config: InfParMachineConfig, env_config: InfParEnvConfig) -> Self {
        let cell_len = 1usize << config.cell_len_bits;
        let mem_address_len = if let Some(max_mem_size) = env_config.max_mem_size {
            if (max_mem_size as u128) > ((((cell_len as u128) << 32) + 7) >> 3) {
                2
            } else {
                1
            }
        } else {
            2
        };
        let temp_buffer_len = ((env_config.max_temp_buffer_len as usize) + 31) >> 5;
        let mem_address_pos_pos = mem_address_len + temp_buffer_len;
        let mem_cell_pos = mem_address_pos_pos + 1;
        let data_part_pos = mem_cell_pos + (((cell_len << 1) + 31) >> 5);
        let rest_pos = data_part_pos + ((config.data_part_len as usize + 31) >> 5);
        let rest_pos = if (config.data_part_len & 31) != 0 && (config.data_part_len & 31) <= 22 {
            rest_pos - 1
        } else {
            rest_pos
        };
        let entry_len = rest_pos + 1;
        Self {
            config,
            temp_buffer_len_in_bits: env_config.max_temp_buffer_len as usize,
            entry_len,
            mem_address_len,
            temp_buffer_len,
            temp_buffer_last_mask: if (env_config.max_temp_buffer_len & 31) != 0 {
                (1u32 << (env_config.max_temp_buffer_len & 31)) - 1u32
            } else {
                u32::MAX
            },
            mem_address_pos_pos,
            mem_cell_pos,
            data_part_pos,
            rest_pos,
        }
    }

    /// Returns length in 32-bit words.
    #[inline]
    pub fn len(&self) -> usize {
        self.entry_len
    }
    /// Returns main memory address length in bits.
    #[inline]
    pub fn mem_address_len(&self) -> usize {
        self.mem_address_len << 5
    }
    /// Returns machine configuration.
    #[inline]
    pub fn config(&self) -> &InfParMachineConfig {
        &self.config
    }
    /// Returns temp buffer length in bits.
    #[inline]
    pub fn temp_buffer_len_in_bits(&self) -> usize {
        self.temp_buffer_len_in_bits
    }
    /// Returns position of rest data in 32-bit words in entry.
    #[inline]
    pub fn rest_pos(&self) -> usize {
        self.rest_pos
    }
    /// Returns position of read main memory cell in 32-bit words in entry.
    #[inline]
    pub fn mem_cell_pos(&self) -> usize {
        self.mem_cell_pos
    }
    /// Returns position of write main memory cell in 32-bit words in entry.
    #[inline]
    pub fn write_mem_cell_pos(&self) -> usize {
        let cell_len = 1 << self.config.cell_len_bits;
        self.mem_cell_pos + (cell_len >> 5)
    }
    /// Returns position of internal data positions in 32-bit words in entry.
    #[inline]
    pub fn data_part_pos_pos(&self) -> usize {
        self.mem_address_pos_pos
    }
    /// Returns position of internal data in 32-bit words in entry.
    #[inline]
    pub fn data_part_pos(&self) -> usize {
        self.data_part_pos
    }

    // about methods: Methods with suffix '_all' returns vector of 32-bit words.
    // Methods with suffix '_slice' returns number of 32-bit words copied into out slice.

    /// Returns lower 64 bits of main memory address.
    pub fn mem_address(&self, entry: &[u32]) -> u64 {
        if self.mem_address_len >= 2 {
            (entry[0] as u64) | ((entry[1] as u64) << 32)
        } else {
            entry[0] as u64
        }
    }
    /// Returns whole main memory address as vector of 32-bit words.
    pub fn mem_address_all(&self, entry: &[u32]) -> Vec<u32> {
        Vec::from(&entry[0..self.mem_address_len])
    }
    /// Stores whole main memory address as slice of 32-bit words.
    /// Returns memory address length in 32-bit words.
    pub fn mem_address_slice(&self, entry: &[u32], out: &mut [u32]) -> usize {
        out[0..self.mem_address_len].copy_from_slice(&entry[0..self.mem_address_len]);
        self.mem_address_len
    }
    /// Returns temp buffer.
    pub fn temp_buffer(&self, entry: &[u32]) -> Vec<u32> {
        let mut wds =
            Vec::from(&entry[self.mem_address_len..self.mem_address_len + self.temp_buffer_len]);
        *wds.last_mut().unwrap() &= self.temp_buffer_last_mask;
        wds
    }
    /// Stores whole temp buffer to slice of 32-bit words.
    /// Returns temp buffer length in 32-bit words.
    pub fn temp_buffer_slice(&self, entry: &[u32], out: &mut [u32]) -> usize {
        out[0..self.temp_buffer_len].copy_from_slice(
            &entry[self.mem_address_len..self.mem_address_len + self.temp_buffer_len],
        );
        out[self.temp_buffer_len - 1] &= self.temp_buffer_last_mask;
        self.temp_buffer_len
    }
    /// Returns current main memory address position.
    pub fn mem_address_pos(&self, entry: &[u32]) -> u32 {
        entry[self.mem_address_pos_pos] & 0xff
    }
    /// Returns current temp buffer position.
    pub fn temp_buffer_pos(&self, entry: &[u32]) -> u32 {
        (entry[self.mem_address_pos_pos] >> 8) & 0xffff
    }
    /// Returns current processor id position.
    pub fn proc_id_pos(&self, entry: &[u32]) -> u32 {
        entry[self.mem_address_pos_pos] >> 24
    }
    /// Returns lower 64 bits of read main memory cell.
    pub fn read_mem_cell(&self, entry: &[u32]) -> u64 {
        let cell_len = 1 << self.config.cell_len_bits;
        if cell_len <= 32 {
            (entry[self.mem_cell_pos] as u64) & ((1u64 << cell_len) - 1u64)
        } else {
            (entry[self.mem_cell_pos] as u64) | ((entry[self.mem_cell_pos + 1] as u64) << 32)
        }
    }
    /// Returns whole read main memory cell.
    pub fn read_mem_cell_all(&self, entry: &[u32]) -> Vec<u32> {
        let cell_len = 1 << self.config.cell_len_bits;
        if cell_len <= 32 {
            vec![entry[self.mem_cell_pos] & u32::try_from((1u64 << cell_len) - 1u64).unwrap()]
        } else {
            Vec::from(&entry[self.mem_cell_pos..self.mem_cell_pos + (cell_len >> 5)])
        }
    }
    /// Stores whole read main memory cell to slice of 32-bit words.
    /// Returns main memory cell length in 32-bit words.
    pub fn read_mem_cell_slice(&self, entry: &[u32], out: &mut [u32]) -> usize {
        let cell_len = 1 << self.config.cell_len_bits;
        if cell_len <= 32 {
            out[0] = entry[self.mem_cell_pos] & u32::try_from((1u64 << cell_len) - 1u64).unwrap();
            1
        } else {
            let cell_len_in_dwords = (cell_len >> 5) as usize;
            out[0..cell_len_in_dwords]
                .copy_from_slice(&entry[self.mem_cell_pos..self.mem_cell_pos + cell_len_in_dwords]);
            cell_len_in_dwords
        }
    }
    /// Sets read main memory cell. `mem_cell` is new value of memory cell to read.
    pub fn set_read_mem_cell_all(&self, entry: &mut [u32], mem_cell: &[u32]) {
        let cell_len = 1 << self.config.cell_len_bits;
        if cell_len <= 16 {
            entry[self.mem_cell_pos] = (entry[self.mem_cell_pos] & 0xffff0000)
                | (mem_cell[0] & ((1u32 << cell_len) - 1u32));
        } else if cell_len <= 32 {
            entry[self.mem_cell_pos] = mem_cell[0];
        } else {
            entry[self.mem_cell_pos..self.mem_cell_pos + (cell_len >> 5)].copy_from_slice(mem_cell);
        }
    }
    /// Returns lower 64 bits of main memory cell to write.
    pub fn write_mem_cell(&self, entry: &[u32]) -> u64 {
        let cell_len = 1 << self.config.cell_len_bits;
        let mem_cell_pos_2 = self.mem_cell_pos + (cell_len >> 5);
        if cell_len <= 16 {
            ((entry[self.mem_cell_pos] as u64) >> 16) & ((1u64 << cell_len) - 1u64)
        } else if cell_len <= 32 {
            (entry[mem_cell_pos_2] as u64) & ((1u64 << cell_len) - 1u64)
        } else {
            (entry[mem_cell_pos_2] as u64) | ((entry[mem_cell_pos_2 + 1] as u64) << 32)
        }
    }
    /// Returns whole main memory cell to write.
    pub fn write_mem_cell_all(&self, entry: &[u32]) -> Vec<u32> {
        let cell_len = 1 << self.config.cell_len_bits;
        let mem_cell_pos_2 = self.mem_cell_pos + (cell_len >> 5);
        if cell_len <= 16 {
            vec![(entry[self.mem_cell_pos] >> 16) & ((1u32 << cell_len) - 1u32)]
        } else if cell_len <= 32 {
            vec![entry[mem_cell_pos_2] & u32::try_from((1u64 << cell_len) - 1u64).unwrap()]
        } else {
            Vec::from(&entry[mem_cell_pos_2..mem_cell_pos_2 + (cell_len >> 5)])
        }
    }
    /// Stores whole write main memory cell to slice of 32-bit words.
    /// Returns main memory cell length in 32-bit words.
    pub fn write_mem_cell_slice(&self, entry: &[u32], out: &mut [u32]) -> usize {
        let cell_len = 1 << self.config.cell_len_bits;
        let mem_cell_pos_2 = self.mem_cell_pos + (cell_len >> 5);
        if cell_len <= 16 {
            out[0] = (entry[self.mem_cell_pos] >> 16)
                & u32::try_from((1u64 << cell_len) - 1u64).unwrap();
            1
        } else if cell_len <= 32 {
            out[0] = entry[mem_cell_pos_2] & u32::try_from((1u64 << cell_len) - 1u64).unwrap();
            1
        } else {
            let cell_len_in_dwords = (cell_len >> 5) as usize;
            out[0..cell_len_in_dwords]
                .copy_from_slice(&entry[mem_cell_pos_2..mem_cell_pos_2 + cell_len_in_dwords]);
            cell_len_in_dwords
        }
    }
    /// Returns main memory access.
    pub fn mem_access(&self, entry: &[u32]) -> DataAccess {
        match (entry[self.rest_pos] >> 22) & 3 {
            0 => DataAccess::Nothing,
            1 => DataAccess::ReadOnly,
            2 => DataAccess::WriteOnly,
            3 => DataAccess::ReadWrite,
            _ => {
                panic!("Unexpected!")
            }
        }
    }
    /// Returns main memory access in raw form.
    pub fn mem_access_raw(&self, entry: &[u32]) -> u32 {
        (entry[self.rest_pos] >> 22) & 3
    }
    /// Returns true if main memory will be read.
    pub fn mem_read(&self, entry: &[u32]) -> bool {
        ((entry[self.rest_pos] >> 22) & 1) != 0
    }
    /// Returns true if main memory will be written.
    pub fn mem_write(&self, entry: &[u32]) -> bool {
        ((entry[self.rest_pos] >> 22) & 2) != 0
    }
    /// Returns lower 64 bits of read data part.
    pub fn read_data_part(&self, entry: &[u32]) -> u64 {
        let dp_len = self.config.data_part_len as usize;
        if dp_len <= 32 {
            (entry[self.data_part_pos] as u64) & ((1u64 << dp_len) - 1u64)
        } else {
            let wd =
                (entry[self.data_part_pos] as u64) | ((entry[self.data_part_pos + 1] as u64) << 32);
            if dp_len < 64 {
                wd & ((1u64 << dp_len) - 1u64)
            } else {
                wd
            }
        }
    }
    /// Returns whole data part.
    pub fn read_data_part_all(&self, entry: &[u32]) -> Vec<u32> {
        let dp_len = self.config.data_part_len as usize;
        if dp_len <= 32 {
            vec![entry[self.data_part_pos] & u32::try_from((1u64 << dp_len) - 1u64).unwrap()]
        } else {
            let mut wds =
                Vec::from(&entry[self.data_part_pos..self.data_part_pos + ((dp_len + 31) >> 5)]);
            if (dp_len & 31) != 0 {
                *wds.last_mut().unwrap() &= (1u32 << (dp_len & 31)) - 1;
            }
            wds
        }
    }
    /// Stores whole read internal data part to slice of 32-bit words.
    /// Returns internal data part length in 32-bit words.
    pub fn read_data_part_slice(&self, entry: &[u32], out: &mut [u32]) -> usize {
        let dp_len = self.config.data_part_len as usize;
        if dp_len <= 32 {
            out[0] = entry[self.data_part_pos] & u32::try_from((1u64 << dp_len) - 1u64).unwrap();
            1
        } else {
            let dp_len_in_dwords = ((dp_len + 31) >> 5) as usize;
            out[0..dp_len_in_dwords]
                .copy_from_slice(&entry[self.data_part_pos..self.data_part_pos + dp_len_in_dwords]);
            if (dp_len & 31) != 0 {
                out[dp_len_in_dwords - 1] &= (1u32 << (dp_len & 31)) - 1;
            }
            dp_len_in_dwords
        }
    }
    /// Returns data (internal data) access.
    pub fn data_part_access(&self, entry: &[u32]) -> DataAccess {
        match (entry[self.rest_pos] >> (22 + 2)) & 3 {
            0 => DataAccess::Nothing,
            1 => DataAccess::ReadOnly,
            2 => DataAccess::WriteOnly,
            3 => DataAccess::ReadWrite,
            _ => {
                panic!("Unexpected!")
            }
        }
    }
    /// Returns data (internal data) access in raw form.
    pub fn data_part_access_raw(&self, entry: &[u32]) -> u32 {
        (entry[self.rest_pos] >> (22 + 2)) & 3
    }
    /// Returns true if internal data will be read.
    pub fn data_part_read(&self, entry: &[u32]) -> bool {
        ((entry[self.rest_pos] >> 22) & 4) != 0
    }
    /// Returns true if internal data will be written.
    pub fn data_part_write(&self, entry: &[u32]) -> bool {
        ((entry[self.rest_pos] >> 22) & 8) != 0
    }
    /// Returns data movement direction.
    pub fn data_move_dir(&self, entry: &[u32]) -> DataPartMove {
        match (entry[self.rest_pos] >> (22 + 4)) & 3 {
            0 => DataPartMove::Nothing,
            1 => DataPartMove::Forward,
            2 => DataPartMove::Backward,
            3 => DataPartMove::Backward,
            _ => {
                panic!("Unexpected!")
            }
        }
    }
    /// Returns data movement direction in raw form.
    pub fn data_move_dir_raw(&self, entry: &[u32]) -> u32 {
        (entry[self.rest_pos] >> (22 + 4)) & 3
    }
    /// Returns data kind.
    pub fn data_kind(&self, entry: &[u32]) -> DataKind {
        match (entry[self.rest_pos] >> (22 + 6)) & 3 {
            0 => DataKind::MemAddress,
            1 => DataKind::TempBuffer,
            2 => DataKind::ProcId,
            3 => DataKind::ProcId,
            _ => {
                panic!("Unexpected!")
            }
        }
    }
    /// Returns data kind in raw form.
    pub fn data_kind_raw(&self, entry: &[u32]) -> u32 {
        (entry[self.rest_pos] >> (22 + 6)) & 3
    }
    /// Returns true if STOP_MACHINE is set.
    pub fn stop_machine(&self, entry: &[u32]) -> bool {
        ((entry[self.rest_pos] >> (22 + 8)) & 1) != 0
    }
    /// Returns whether movement of internal data position is done.
    pub fn data_part_move_done(&self, entry: &[u32]) -> bool {
        ((entry[self.rest_pos] >> (22 + 9)) & 1) != 0
    }
}

/// Object that can read proc_int_data from vector of 32-bit words.
pub struct ProcIntDataReader {
    data: Vec<u32>,
    data_config: ProcIntDataConfig,
}

impl ProcIntDataReader {
    /// Creates new proc_int_data reader.
    pub fn new(config: InfParMachineConfig, env_config: InfParEnvConfig, data: Vec<u32>) -> Self {
        let data_config = ProcIntDataConfig::new(config, env_config);
        assert_eq!(data.len() % data_config.entry_len, 0);
        Self { data, data_config }
    }
    /// Creates new proc_int_data reader from configuration.
    pub fn new_from_config(data_config: ProcIntDataConfig, data: Vec<u32>) -> Self {
        assert_eq!(data.len() % data_config.entry_len, 0);
        Self { data, data_config }
    }

    /// Returns proc_int_data configuration.
    #[inline]
    pub fn data_config(&self) -> &ProcIntDataConfig {
        &self.data_config
    }
}

impl Index<u64> for ProcIntDataReader {
    type Output = [u32];
    #[inline]
    fn index(&self, index: u64) -> &Self::Output {
        let offset = usize::try_from(index)
            .unwrap()
            .checked_mul(self.data_config.entry_len)
            .unwrap();
        &self.data[offset..offset + self.data_config.entry_len]
    }
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_proc_int_data_reader() {
        let mut temps = [0, 0, 0, 0, 0, 0, 0, 0, 0];
        let config = InfParMachineConfig {
            state_len: 40,
            data_part_len: 7,
            cell_len_bits: 3,
        };
        let env_config = InfParEnvConfig {
            proc_num: 1 << 8,
            flat_memory: true,
            max_temp_buffer_len: 24,
            max_mem_size: Some(20 * (1 << 20)),
        };
        let dh = vec![
            // entry 0 - values to read - can be nonsense
            24412,                         // mem_address
            0xabcdef11,                    // temp buffer
            0x1a2b3c4d,                    // mem_address_pos, temp_buffer_pos, proc_id_pos
            0x1ba3 | (0xcd1 << 16),        // read_mem_cell, write_mem_cell
            0x7ce3 | (0b1001101001 << 22), // read_data_part, write_data_part, rest
            // entry 1 - values to read - can be nonsense
            5960215,                       // mem_address
            0xc0a09d51,                    // temp buffer
            0x3046da1c,                    // mem_address_pos, temp_buffer_pos, proc_id_pos
            0x2a16 | (0x5a1 << 16),        // read_mem_cell, write_mem_cell
            0x6671 | (0b0110000110 << 22), // read_data_part, write_data_part, rest
        ];
        let pidr = ProcIntDataReader::new(config, env_config, dh);
        let dc = pidr.data_config();
        // first entry
        assert_eq!(24412, dc.mem_address(&pidr[0]));
        assert_eq!(vec![24412], dc.mem_address_all(&pidr[0]));
        assert_eq!(1, dc.mem_address_slice(&pidr[0], &mut temps));
        assert_eq!(24412, temps[0]);
        assert_eq!(vec![0xcdef11], dc.temp_buffer(&pidr[0]));
        assert_eq!(1, dc.temp_buffer_slice(&pidr[0], &mut temps));
        assert_eq!(0xcdef11, temps[0]);
        assert_eq!(0x4d, dc.mem_address_pos(&pidr[0]));
        assert_eq!(0x2b3c, dc.temp_buffer_pos(&pidr[0]));
        assert_eq!(0x1a, dc.proc_id_pos(&pidr[0]));
        assert_eq!(0xa3, dc.read_mem_cell(&pidr[0]));
        assert_eq!(vec![0xa3], dc.read_mem_cell_all(&pidr[0]));
        assert_eq!(1, dc.read_mem_cell_slice(&pidr[0], &mut temps));
        assert_eq!(0xa3, temps[0]);
        assert_eq!(0xd1, dc.write_mem_cell(&pidr[0]));
        assert_eq!(vec![0xd1], dc.write_mem_cell_all(&pidr[0]));
        assert_eq!(1, dc.write_mem_cell_slice(&pidr[0], &mut temps));
        assert_eq!(0xd1, temps[0]);
        assert_eq!(0x63, dc.read_data_part(&pidr[0]));
        assert_eq!(vec![0x63], dc.read_data_part_all(&pidr[0]));
        assert_eq!(1, dc.read_data_part_slice(&pidr[0], &mut temps));
        assert_eq!(0x63, temps[0]);
        assert_eq!(DataAccess::ReadOnly, dc.mem_access(&pidr[0]));
        assert_eq!(DataAccess::WriteOnly, dc.data_part_access(&pidr[0]));
        assert_eq!(true, dc.mem_read(&pidr[0]));
        assert_eq!(false, dc.mem_write(&pidr[0]));
        assert_eq!(false, dc.data_part_read(&pidr[0]));
        assert_eq!(true, dc.data_part_write(&pidr[0]));
        assert_eq!(DataPartMove::Backward, dc.data_move_dir(&pidr[0]));
        assert_eq!(DataKind::TempBuffer, dc.data_kind(&pidr[0]));
        assert_eq!(true, dc.data_part_move_done(&pidr[0]));
        assert_eq!(false, dc.stop_machine(&pidr[0]));
        // second entry
        assert_eq!(5960215, dc.mem_address(&pidr[1]));
        assert_eq!(vec![5960215], dc.mem_address_all(&pidr[1]));
        assert_eq!(1, dc.mem_address_slice(&pidr[1], &mut temps));
        assert_eq!(5960215, temps[0]);
        assert_eq!(vec![0xa09d51], dc.temp_buffer(&pidr[1]));
        assert_eq!(1, dc.temp_buffer_slice(&pidr[1], &mut temps));
        assert_eq!(0xa09d51, temps[0]);
        assert_eq!(0x1c, dc.mem_address_pos(&pidr[1]));
        assert_eq!(0x46da, dc.temp_buffer_pos(&pidr[1]));
        assert_eq!(0x30, dc.proc_id_pos(&pidr[1]));
        assert_eq!(0x16, dc.read_mem_cell(&pidr[1]));
        assert_eq!(vec![0x16], dc.read_mem_cell_all(&pidr[1]));
        assert_eq!(1, dc.read_mem_cell_slice(&pidr[1], &mut temps));
        assert_eq!(0x16, temps[0]);
        assert_eq!(0xa1, dc.write_mem_cell(&pidr[1]));
        assert_eq!(vec![0xa1], dc.write_mem_cell_all(&pidr[1]));
        assert_eq!(1, dc.write_mem_cell_slice(&pidr[1], &mut temps));
        assert_eq!(0xa1, temps[0]);
        assert_eq!(0x71, dc.read_data_part(&pidr[1]));
        assert_eq!(vec![0x71], dc.read_data_part_all(&pidr[1]));
        assert_eq!(1, dc.read_data_part_slice(&pidr[1], &mut temps));
        assert_eq!(0x71, temps[0]);
        assert_eq!(DataAccess::WriteOnly, dc.mem_access(&pidr[1]));
        assert_eq!(DataAccess::ReadOnly, dc.data_part_access(&pidr[1]));
        assert_eq!(false, dc.mem_read(&pidr[1]));
        assert_eq!(true, dc.mem_write(&pidr[1]));
        assert_eq!(true, dc.data_part_read(&pidr[1]));
        assert_eq!(false, dc.data_part_write(&pidr[1]));
        assert_eq!(DataPartMove::Nothing, dc.data_move_dir(&pidr[1]));
        assert_eq!(DataKind::ProcId, dc.data_kind(&pidr[1]));
        assert_eq!(false, dc.data_part_move_done(&pidr[1]));
        assert_eq!(true, dc.stop_machine(&pidr[1]));
        // check set_read_mem_cell_all
        let mut entry = pidr[0].to_vec();
        dc.set_read_mem_cell_all(&mut entry, &[0xda45]);
        assert_eq!(0x45, dc.read_mem_cell(&entry));
        assert_eq!(0xd1, dc.write_mem_cell(&entry));
        // next config
        let config = InfParMachineConfig {
            state_len: 40,
            data_part_len: 7,
            cell_len_bits: 3,
        };
        let env_config = InfParEnvConfig {
            proc_num: 1 << 8,
            flat_memory: true,
            max_temp_buffer_len: 64,
            max_mem_size: Some(20 * (1 << 20)),
        };
        let dh = vec![
            // entry 0 - values to read - can be nonsense
            24412,                         // mem_address
            0xabcdef11,                    // temp buffer 0
            0xca03916e,                    // temp buffer 1
            0x1a2b3c4d,                    // mem_address_pos, temp_buffer_pos, proc_id_pos
            0x1ba3 | (0xcd1 << 16),        // read_mem_cell, write_mem_cell
            0x7ce3 | (0b1011111001 << 22), // read_data_part, write_data_part, rest
        ];
        let pidr = ProcIntDataReader::new(config, env_config, dh);
        let dc = pidr.data_config();
        // first entry
        assert_eq!(24412, dc.mem_address(&pidr[0]));
        assert_eq!(vec![24412], dc.mem_address_all(&pidr[0]));
        assert_eq!(1, dc.mem_address_slice(&pidr[0], &mut temps));
        assert_eq!(24412, temps[0]);
        assert_eq!(vec![0xabcdef11, 0xca03916e], dc.temp_buffer(&pidr[0]));
        assert_eq!(2, dc.temp_buffer_slice(&pidr[0], &mut temps));
        assert_eq!([0xabcdef11, 0xca03916e], temps[0..2]);
        assert_eq!(0x4d, dc.mem_address_pos(&pidr[0]));
        assert_eq!(0x2b3c, dc.temp_buffer_pos(&pidr[0]));
        assert_eq!(0x1a, dc.proc_id_pos(&pidr[0]));
        assert_eq!(0xa3, dc.read_mem_cell(&pidr[0]));
        assert_eq!(vec![0xa3], dc.read_mem_cell_all(&pidr[0]));
        assert_eq!(1, dc.read_mem_cell_slice(&pidr[0], &mut temps));
        assert_eq!(0xa3, temps[0]);
        assert_eq!(0xd1, dc.write_mem_cell(&pidr[0]));
        assert_eq!(vec![0xd1], dc.write_mem_cell_all(&pidr[0]));
        assert_eq!(1, dc.write_mem_cell_slice(&pidr[0], &mut temps));
        assert_eq!(0xd1, temps[0]);
        assert_eq!(0x63, dc.read_data_part(&pidr[0]));
        assert_eq!(vec![0x63], dc.read_data_part_all(&pidr[0]));
        assert_eq!(1, dc.read_data_part_slice(&pidr[0], &mut temps));
        assert_eq!(0x63, temps[0]);
        assert_eq!(DataAccess::ReadOnly, dc.mem_access(&pidr[0]));
        assert_eq!(DataAccess::WriteOnly, dc.data_part_access(&pidr[0]));
        assert_eq!(DataPartMove::Backward, dc.data_move_dir(&pidr[0]));
        assert_eq!(DataKind::ProcId, dc.data_kind(&pidr[0]));
        assert_eq!(true, dc.data_part_move_done(&pidr[0]));
        assert_eq!(false, dc.stop_machine(&pidr[0]));
        // check set_read_mem_cell_all
        let mut entry = pidr[0].to_vec();
        dc.set_read_mem_cell_all(&mut entry, &[0xda45]);
        assert_eq!(0x45, dc.read_mem_cell(&entry));
        assert_eq!(0xd1, dc.write_mem_cell(&entry));
        // next config
        let config = InfParMachineConfig {
            state_len: 40,
            data_part_len: 28,
            cell_len_bits: 5,
        };
        let env_config = InfParEnvConfig {
            proc_num: 1 << 8,
            flat_memory: true,
            max_temp_buffer_len: 84,
            max_mem_size: Some(20 * (1 << 40)),
        };
        let dh = vec![
            // entry 0 - values to read - can be nonsense
            0x5c0a14e3,         // mem_address lo
            0x558a1,            // mem_address hi
            0xabcdef11,         // temp buffer 0
            0x12bc3ac5,         // temp buffer 1
            0xc0a0359a,         // temp buffer 2
            0x1a2b3c4d,         // mem_address_pos, temp_buffer_pos, proc_id_pos
            0xa0491b6,          // read_mem_cell
            0x2ab0c04,          // write_mem_cell
            0x5349c0d5,         // read_data_part
            0b1010011001 << 22, // rest (memrw, dp_rw, dp_move_done, stop_machine)
        ];
        let pidr = ProcIntDataReader::new(config, env_config, dh);
        let dc = pidr.data_config();
        assert_eq!(0x558a15c0a14e3, dc.mem_address(&pidr[0]));
        assert_eq!(vec![0x5c0a14e3, 0x558a1], dc.mem_address_all(&pidr[0]));
        assert_eq!(2, dc.mem_address_slice(&pidr[0], &mut temps));
        assert_eq!([0x5c0a14e3, 0x558a1], temps[0..2]);
        assert_eq!(
            vec![0xabcdef11, 0x12bc3ac5, 0x0359a],
            dc.temp_buffer(&pidr[0])
        );
        assert_eq!(3, dc.temp_buffer_slice(&pidr[0], &mut temps));
        assert_eq!([0xabcdef11, 0x12bc3ac5, 0x0359a], temps[0..3]);
        assert_eq!(0x4d, dc.mem_address_pos(&pidr[0]));
        assert_eq!(0x2b3c, dc.temp_buffer_pos(&pidr[0]));
        assert_eq!(0x1a, dc.proc_id_pos(&pidr[0]));
        assert_eq!(0xa0491b6, dc.read_mem_cell(&pidr[0]));
        assert_eq!(vec![0xa0491b6], dc.read_mem_cell_all(&pidr[0]));
        assert_eq!(1, dc.read_mem_cell_slice(&pidr[0], &mut temps));
        assert_eq!(0xa0491b6, temps[0]);
        assert_eq!(0x2ab0c04, dc.write_mem_cell(&pidr[0]));
        assert_eq!(vec![0x2ab0c04], dc.write_mem_cell_all(&pidr[0]));
        assert_eq!(1, dc.write_mem_cell_slice(&pidr[0], &mut temps));
        assert_eq!(0x2ab0c04, temps[0]);
        assert_eq!(0x349c0d5, dc.read_data_part(&pidr[0]));
        assert_eq!(vec![0x349c0d5], dc.read_data_part_all(&pidr[0]));
        assert_eq!(1, dc.read_data_part_slice(&pidr[0], &mut temps));
        assert_eq!(0x349c0d5, temps[0]);
        assert_eq!(DataAccess::ReadOnly, dc.mem_access(&pidr[0]));
        assert_eq!(DataAccess::WriteOnly, dc.data_part_access(&pidr[0]));
        assert_eq!(DataPartMove::Forward, dc.data_move_dir(&pidr[0]));
        assert_eq!(DataKind::ProcId, dc.data_kind(&pidr[0]));
        assert_eq!(true, dc.data_part_move_done(&pidr[0]));
        assert_eq!(false, dc.stop_machine(&pidr[0]));
        // check set_read_mem_cell_all
        let mut entry = pidr[0].to_vec();
        dc.set_read_mem_cell_all(&mut entry, &[0x3725d023]);
        assert_eq!(0x3725d023, dc.read_mem_cell(&entry));
        assert_eq!(0x2ab0c04, dc.write_mem_cell(&entry));
        // next config
        let config = InfParMachineConfig {
            state_len: 40,
            data_part_len: 90,
            cell_len_bits: 7,
        };
        let env_config = InfParEnvConfig {
            proc_num: 1 << 8,
            flat_memory: true,
            max_temp_buffer_len: 140,
            max_mem_size: Some(20 * (1 << 40)),
        };
        let dh = vec![
            // entry 0 - values to read - can be nonsense
            0x5c0a14e3,         // mem_address lo
            0x558a1,            // mem_address hi
            0xabcdef11,         // temp buffer 0
            0x12bc3ac5,         // temp buffer 1
            0xc0a0359a,         // temp buffer 2
            0x3a0c0da1,         // temp buffer 3
            0x145cda46,         // temp buffer 4
            0x1a2b3c4d,         // mem_address_pos, temp_buffer_pos, proc_id_pos
            0x1122bc0a,         // read_mem_cell 0
            0xc0a0494d,         // read_mem_cell 1
            0x05850aa0,         // read_mem_cell 2
            0xe0485016,         // read_mem_cell 3
            0x0a332114,         // write_mem_cell 0
            0x596bc02b,         // write_mem_cell 1
            0xb0c9a094,         // write_mem_cell 2
            0x958bb301,         // write_mem_cell 3
            0x104ca040,         // read_data_part 0
            0xc0a94041,         // read_data_part 1
            0xf048401c,         // read_data_part 2
            0b1000001001 << 22, // rest (memrw, dp_rw, dp_move_done, stop_machine)
        ];
        let pidr = ProcIntDataReader::new(config, env_config, dh);
        let dc = pidr.data_config();
        assert_eq!(0x558a15c0a14e3, dc.mem_address(&pidr[0]));
        assert_eq!(vec![0x5c0a14e3, 0x558a1], dc.mem_address_all(&pidr[0]));
        assert_eq!(2, dc.mem_address_slice(&pidr[0], &mut temps));
        assert_eq!([0x5c0a14e3, 0x558a1], temps[0..2]);
        assert_eq!(
            vec![0xabcdef11, 0x12bc3ac5, 0xc0a0359a, 0x3a0c0da1, 0xa46],
            dc.temp_buffer(&pidr[0])
        );
        assert_eq!(5, dc.temp_buffer_slice(&pidr[0], &mut temps));
        assert_eq!(
            [0xabcdef11, 0x12bc3ac5, 0xc0a0359a, 0x3a0c0da1, 0xa46],
            temps[0..5]
        );
        assert_eq!(0x4d, dc.mem_address_pos(&pidr[0]));
        assert_eq!(0x2b3c, dc.temp_buffer_pos(&pidr[0]));
        assert_eq!(0x1a, dc.proc_id_pos(&pidr[0]));
        assert_eq!(0xc0a0494d1122bc0a, dc.read_mem_cell(&pidr[0]));
        assert_eq!(
            vec![0x1122bc0a, 0xc0a0494d, 0x05850aa0, 0xe0485016],
            dc.read_mem_cell_all(&pidr[0])
        );
        assert_eq!(4, dc.read_mem_cell_slice(&pidr[0], &mut temps));
        assert_eq!(
            [0x1122bc0a, 0xc0a0494d, 0x05850aa0, 0xe0485016],
            temps[0..4]
        );
        assert_eq!(0x596bc02b0a332114, dc.write_mem_cell(&pidr[0]));
        assert_eq!(
            vec![0x0a332114, 0x596bc02b, 0xb0c9a094, 0x958bb301],
            dc.write_mem_cell_all(&pidr[0])
        );
        assert_eq!(4, dc.write_mem_cell_slice(&pidr[0], &mut temps));
        assert_eq!(
            [0x0a332114, 0x596bc02b, 0xb0c9a094, 0x958bb301],
            temps[0..4]
        );
        assert_eq!(0xc0a94041104ca040, dc.read_data_part(&pidr[0]));
        assert_eq!(
            vec![0x104ca040, 0xc0a94041, 0x0048401c],
            dc.read_data_part_all(&pidr[0])
        );
        assert_eq!(3, dc.read_data_part_slice(&pidr[0], &mut temps));
        assert_eq!([0x104ca040, 0xc0a94041, 0x0048401c], temps[0..3]);
        assert_eq!(DataAccess::ReadOnly, dc.mem_access(&pidr[0]));
        assert_eq!(DataAccess::WriteOnly, dc.data_part_access(&pidr[0]));
        assert_eq!(DataPartMove::Nothing, dc.data_move_dir(&pidr[0]));
        assert_eq!(DataKind::MemAddress, dc.data_kind(&pidr[0]));
        assert_eq!(true, dc.data_part_move_done(&pidr[0]));
        assert_eq!(false, dc.stop_machine(&pidr[0]));
        // check set_read_mem_cell_all
        let mut entry = pidr[0].to_vec();
        dc.set_read_mem_cell_all(&mut entry, &[0x1133aa, 0xfdca01, 0xa0131, 0x240abc]);
        assert_eq!(
            vec![0x1133aa, 0xfdca01, 0xa0131, 0x240abc],
            dc.read_mem_cell_all(&entry)
        );
        assert_eq!(
            vec![0x0a332114, 0x596bc02b, 0xb0c9a094, 0x958bb301],
            dc.write_mem_cell_all(&entry)
        );
        // next config
        let config = InfParMachineConfig {
            state_len: 40,
            data_part_len: 96 - 10,
            cell_len_bits: 7,
        };
        let env_config = InfParEnvConfig {
            proc_num: 1 << 8,
            flat_memory: true,
            max_temp_buffer_len: 140,
            max_mem_size: Some(20 * (1 << 40)),
        };
        let dh = vec![
            // entry 0 - values to read - can be nonsense
            0x5c0a14e3,                        // mem_address lo
            0x558a1,                           // mem_address hi
            0xabcdef11,                        // temp buffer 0
            0x12bc3ac5,                        // temp buffer 1
            0xc0a0359a,                        // temp buffer 2
            0x3a0c0da1,                        // temp buffer 3
            0x145cda46,                        // temp buffer 4
            0x1a2b3c4d,                        // mem_address_pos, temp_buffer_pos, proc_id_pos
            0x1122bc0a,                        // read_mem_cell 0
            0xc0a0494d,                        // read_mem_cell 1
            0x05850aa0,                        // read_mem_cell 2
            0xe0485016,                        // read_mem_cell 3
            0x0a332114,                        // write_mem_cell 0
            0x596bc02b,                        // write_mem_cell 1
            0xb0c9a094,                        // write_mem_cell 2
            0x958bb301,                        // write_mem_cell 3
            0x104ca040,                        // read_data_part 0
            0xc0a94041,                        // read_data_part 1
            0x0008401c | (0b1000001001 << 22), // read_data_part 2, rest
        ];
        let pidr = ProcIntDataReader::new(config, env_config, dh);
        let dc = pidr.data_config();
        assert_eq!(0x558a15c0a14e3, dc.mem_address(&pidr[0]));
        assert_eq!(vec![0x5c0a14e3, 0x558a1], dc.mem_address_all(&pidr[0]));
        assert_eq!(2, dc.mem_address_slice(&pidr[0], &mut temps));
        assert_eq!([0x5c0a14e3, 0x558a1], temps[0..2]);
        assert_eq!(
            vec![0xabcdef11, 0x12bc3ac5, 0xc0a0359a, 0x3a0c0da1, 0xa46],
            dc.temp_buffer(&pidr[0])
        );
        assert_eq!(0xc0a94041104ca040, dc.read_data_part(&pidr[0]));
        assert_eq!(
            vec![0x104ca040, 0xc0a94041, 0x0008401c],
            dc.read_data_part_all(&pidr[0])
        );
        assert_eq!(3, dc.read_data_part_slice(&pidr[0], &mut temps));
        assert_eq!([0x104ca040, 0xc0a94041, 0x0008401c], temps[0..3]);
        assert_eq!(DataAccess::ReadOnly, dc.mem_access(&pidr[0]));
        assert_eq!(DataAccess::WriteOnly, dc.data_part_access(&pidr[0]));
        assert_eq!(DataPartMove::Nothing, dc.data_move_dir(&pidr[0]));
        assert_eq!(DataKind::MemAddress, dc.data_kind(&pidr[0]));
        assert_eq!(true, dc.data_part_move_done(&pidr[0]));
        assert_eq!(false, dc.stop_machine(&pidr[0]));
        // next config
        let config = InfParMachineConfig {
            state_len: 40,
            data_part_len: 96 - 9,
            cell_len_bits: 7,
        };
        let env_config = InfParEnvConfig {
            proc_num: 1 << 8,
            flat_memory: true,
            max_temp_buffer_len: 140,
            max_mem_size: Some(20 * (1 << 40)),
        };
        let dh = vec![
            // entry 0 - values to read - can be nonsense
            0x5c0a14e3,           // mem_address lo
            0x558a1,              // mem_address hi
            0xabcdef11,           // temp buffer 0
            0x12bc3ac5,           // temp buffer 1
            0xc0a0359a,           // temp buffer 2
            0x3a0c0da1,           // temp buffer 3
            0x145cda46,           // temp buffer 4
            0x1a2b3c4d,           // mem_address_pos, temp_buffer_pos, proc_id_pos
            0x1122bc0a,           // read_mem_cell 0
            0xc0a0494d,           // read_mem_cell 1
            0x05850aa0,           // read_mem_cell 2
            0xe0485016,           // read_mem_cell 3
            0x0a332114,           // write_mem_cell 0
            0x596bc02b,           // write_mem_cell 1
            0xb0c9a094,           // write_mem_cell 2
            0x958bb301,           // write_mem_cell 3
            0x104ca040,           // read_data_part 0
            0xc0a94041,           // read_data_part 1
            0x1da8401c,           // read_data_part 2
            (0b1000001001 << 22), // rest
        ];
        let pidr = ProcIntDataReader::new(config, env_config, dh);
        let dc = pidr.data_config();
        assert_eq!(0x558a15c0a14e3, dc.mem_address(&pidr[0]));
        assert_eq!(vec![0x5c0a14e3, 0x558a1], dc.mem_address_all(&pidr[0]));
        assert_eq!(2, dc.mem_address_slice(&pidr[0], &mut temps));
        assert_eq!([0x5c0a14e3, 0x558a1], temps[0..2]);
        assert_eq!(
            vec![0xabcdef11, 0x12bc3ac5, 0xc0a0359a, 0x3a0c0da1, 0xa46],
            dc.temp_buffer(&pidr[0])
        );
        assert_eq!(0xc0a94041104ca040, dc.read_data_part(&pidr[0]));
        assert_eq!(
            vec![0x104ca040, 0xc0a94041, 0x0028401c],
            dc.read_data_part_all(&pidr[0])
        );
        assert_eq!(3, dc.read_data_part_slice(&pidr[0], &mut temps));
        assert_eq!([0x104ca040, 0xc0a94041, 0x0028401c], temps[0..3]);
        assert_eq!(DataAccess::ReadOnly, dc.mem_access(&pidr[0]));
        assert_eq!(DataAccess::WriteOnly, dc.data_part_access(&pidr[0]));
        assert_eq!(DataPartMove::Nothing, dc.data_move_dir(&pidr[0]));
        assert_eq!(DataKind::MemAddress, dc.data_kind(&pidr[0]));
        assert_eq!(true, dc.data_part_move_done(&pidr[0]));
        assert_eq!(false, dc.stop_machine(&pidr[0]));
        // next config
        let config = InfParMachineConfig {
            state_len: 40,
            data_part_len: 96,
            cell_len_bits: 7,
        };
        let env_config = InfParEnvConfig {
            proc_num: 1 << 8,
            flat_memory: true,
            max_temp_buffer_len: 140,
            max_mem_size: Some(20 * (1 << 40)),
        };
        let dh = vec![
            // entry 0 - values to read - can be nonsense
            0x5c0a14e3,           // mem_address lo
            0x558a1,              // mem_address hi
            0xabcdef11,           // temp buffer 0
            0x12bc3ac5,           // temp buffer 1
            0xc0a0359a,           // temp buffer 2
            0x3a0c0da1,           // temp buffer 3
            0x145cda46,           // temp buffer 4
            0x1a2b3c4d,           // mem_address_pos, temp_buffer_pos, proc_id_pos
            0x1122bc0a,           // read_mem_cell 0
            0xc0a0494d,           // read_mem_cell 1
            0x05850aa0,           // read_mem_cell 2
            0xe0485016,           // read_mem_cell 3
            0x0a332114,           // write_mem_cell 0
            0x596bc02b,           // write_mem_cell 1
            0xb0c9a094,           // write_mem_cell 2
            0x958bb301,           // write_mem_cell 3
            0x104ca040,           // read_data_part 0
            0xc0a94041,           // read_data_part 1
            0xb568401c,           // read_data_part 2
            (0b1000001001 << 22), // rest
        ];
        let pidr = ProcIntDataReader::new(config, env_config, dh);
        let dc = pidr.data_config();
        assert_eq!(0x558a15c0a14e3, dc.mem_address(&pidr[0]));
        assert_eq!(vec![0x5c0a14e3, 0x558a1], dc.mem_address_all(&pidr[0]));
        assert_eq!(2, dc.mem_address_slice(&pidr[0], &mut temps));
        assert_eq!([0x5c0a14e3, 0x558a1], temps[0..2]);
        assert_eq!(
            vec![0xabcdef11, 0x12bc3ac5, 0xc0a0359a, 0x3a0c0da1, 0xa46],
            dc.temp_buffer(&pidr[0])
        );
        assert_eq!(0xc0a94041104ca040, dc.read_data_part(&pidr[0]));
        assert_eq!(
            vec![0x104ca040, 0xc0a94041, 0xb568401c],
            dc.read_data_part_all(&pidr[0])
        );
        assert_eq!(3, dc.read_data_part_slice(&pidr[0], &mut temps));
        assert_eq!([0x104ca040, 0xc0a94041, 0xb568401c], temps[0..3]);
        assert_eq!(DataAccess::ReadOnly, dc.mem_access(&pidr[0]));
        assert_eq!(DataAccess::WriteOnly, dc.data_part_access(&pidr[0]));
        assert_eq!(DataPartMove::Nothing, dc.data_move_dir(&pidr[0]));
        assert_eq!(DataKind::MemAddress, dc.data_kind(&pidr[0]));
        assert_eq!(true, dc.data_part_move_done(&pidr[0]));
        assert_eq!(false, dc.stop_machine(&pidr[0]));
    }
}