[][src]Type Definition imxrt1062_flexspi::mcr0::R

type R = R<u32, MCR0>;

Reader of register MCR0

Methods

impl R[src]

pub fn swreset(&self) -> SWRESET_R[src]

Bit 0 - Software Reset

pub fn mdis(&self) -> MDIS_R[src]

Bit 1 - Module Disable

pub fn rxclksrc(&self) -> RXCLKSRC_R[src]

Bits 4:5 - Sample Clock source selection for Flash Reading

pub fn ardfen(&self) -> ARDFEN_R[src]

Bit 6 - Enable AHB bus Read Access to IP RX FIFO.

pub fn atdfen(&self) -> ATDFEN_R[src]

Bit 7 - Enable AHB bus Write Access to IP TX FIFO.

pub fn hsen(&self) -> HSEN_R[src]

Bit 11 - Half Speed Serial Flash access Enable.

pub fn dozeen(&self) -> DOZEEN_R[src]

Bit 12 - Doze mode enable bit

pub fn combinationen(&self) -> COMBINATIONEN_R[src]

Bit 13 - This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]).

pub fn sckfreerunen(&self) -> SCKFREERUNEN_R[src]

Bit 14 - This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2).

pub fn ipgrantwait(&self) -> IPGRANTWAIT_R[src]

Bits 16:23 - Time out wait cycle for IP command grant.

pub fn ahbgrantwait(&self) -> AHBGRANTWAIT_R[src]

Bits 24:31 - Timeout wait cycle for AHB command grant.