Struct imxrt1062_flexspi::R

pub struct R<U, T> { /* fields omitted */ }

Register/field reader

Result of the read method of a register. Also it can be used in the modify method

Methods

impl<U, T> R<U, T> where
    U: Copy, 

pub fn bits(&self) -> U

Read raw bits from register/field

impl<FI> R<bool, FI>

pub fn bit(&self) -> bool

Value of the field as raw bits

pub fn bit_is_clear(&self) -> bool

Returns true if the bit is clear (0)

pub fn bit_is_set(&self) -> bool

Returns true if the bit is set (1)

impl R<u8, RXCLKSRC_A>

pub fn variant(&self) -> Variant<u8, RXCLKSRC_A>

Get enumerated values variant

pub fn is_rxclksrc_0(&self) -> bool

Checks if the value of the field is RXCLKSRC_0

pub fn is_rxclksrc_1(&self) -> bool

Checks if the value of the field is RXCLKSRC_1

pub fn is_rxclksrc_3(&self) -> bool

Checks if the value of the field is RXCLKSRC_3

impl R<bool, ARDFEN_A>

pub fn variant(&self) -> ARDFEN_A

Get enumerated values variant

pub fn is_ardfen_0(&self) -> bool

Checks if the value of the field is ARDFEN_0

pub fn is_ardfen_1(&self) -> bool

Checks if the value of the field is ARDFEN_1

impl R<bool, ATDFEN_A>

pub fn variant(&self) -> ATDFEN_A

Get enumerated values variant

pub fn is_atdfen_0(&self) -> bool

Checks if the value of the field is ATDFEN_0

pub fn is_atdfen_1(&self) -> bool

Checks if the value of the field is ATDFEN_1

impl R<bool, HSEN_A>

pub fn variant(&self) -> HSEN_A

Get enumerated values variant

pub fn is_hsen_0(&self) -> bool

Checks if the value of the field is HSEN_0

pub fn is_hsen_1(&self) -> bool

Checks if the value of the field is HSEN_1

impl R<bool, DOZEEN_A>

pub fn variant(&self) -> DOZEEN_A

Get enumerated values variant

pub fn is_dozeen_0(&self) -> bool

Checks if the value of the field is DOZEEN_0

pub fn is_dozeen_1(&self) -> bool

Checks if the value of the field is DOZEEN_1

impl R<bool, COMBINATIONEN_A>

pub fn variant(&self) -> COMBINATIONEN_A

Get enumerated values variant

pub fn is_combinationen_0(&self) -> bool

Checks if the value of the field is COMBINATIONEN_0

pub fn is_combinationen_1(&self) -> bool

Checks if the value of the field is COMBINATIONEN_1

impl R<bool, SCKFREERUNEN_A>

pub fn variant(&self) -> SCKFREERUNEN_A

Get enumerated values variant

pub fn is_sckfreerunen_0(&self) -> bool

Checks if the value of the field is SCKFREERUNEN_0

pub fn is_sckfreerunen_1(&self) -> bool

Checks if the value of the field is SCKFREERUNEN_1

impl R<u32, Reg<u32, _MCR0>>

pub fn swreset(&self) -> SWRESET_R

Bit 0 - Software Reset

pub fn mdis(&self) -> MDIS_R

Bit 1 - Module Disable

pub fn rxclksrc(&self) -> RXCLKSRC_R

Bits 4:5 - Sample Clock source selection for Flash Reading

pub fn ardfen(&self) -> ARDFEN_R

Bit 6 - Enable AHB bus Read Access to IP RX FIFO.

pub fn atdfen(&self) -> ATDFEN_R

Bit 7 - Enable AHB bus Write Access to IP TX FIFO.

pub fn hsen(&self) -> HSEN_R

Bit 11 - Half Speed Serial Flash access Enable.

pub fn dozeen(&self) -> DOZEEN_R

Bit 12 - Doze mode enable bit

pub fn combinationen(&self) -> COMBINATIONEN_R

Bit 13 - This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]).

pub fn sckfreerunen(&self) -> SCKFREERUNEN_R

Bit 14 - This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2).

pub fn ipgrantwait(&self) -> IPGRANTWAIT_R

Bits 16:23 - Time out wait cycle for IP command grant.

pub fn ahbgrantwait(&self) -> AHBGRANTWAIT_R

Bits 24:31 - Timeout wait cycle for AHB command grant.

impl R<u32, Reg<u32, _MCR1>>

pub fn ahbbuswait(&self) -> AHBBUSWAIT_R

Bits 0:15 - AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmited after AHBBUSWAIT * 1024 ahb clock cycles, AHB Bus will get an error response

pub fn seqwait(&self) -> SEQWAIT_R

Bits 16:31 - Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles

impl R<bool, CLRAHBBUFOPT_A>

pub fn variant(&self) -> CLRAHBBUFOPT_A

Get enumerated values variant

pub fn is_clrahbbufopt_0(&self) -> bool

Checks if the value of the field is CLRAHBBUFOPT_0

pub fn is_clrahbbufopt_1(&self) -> bool

Checks if the value of the field is CLRAHBBUFOPT_1

impl R<bool, SAMEDEVICEEN_A>

pub fn variant(&self) -> SAMEDEVICEEN_A

Get enumerated values variant

pub fn is_samedeviceen_0(&self) -> bool

Checks if the value of the field is SAMEDEVICEEN_0

pub fn is_samedeviceen_1(&self) -> bool

Checks if the value of the field is SAMEDEVICEEN_1

impl R<bool, SCKBDIFFOPT_A>

pub fn variant(&self) -> SCKBDIFFOPT_A

Get enumerated values variant

pub fn is_sckbdiffopt_0(&self) -> bool

Checks if the value of the field is SCKBDIFFOPT_0

pub fn is_sckbdiffopt_1(&self) -> bool

Checks if the value of the field is SCKBDIFFOPT_1

impl R<u32, Reg<u32, _MCR2>>

pub fn clrahbbufopt(&self) -> CLRAHBBUFOPT_R

Bit 11 - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.

pub fn clrlearnphase(&self) -> CLRLEARNPHASE_R

Bit 14 - The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately.

pub fn samedeviceen(&self) -> SAMEDEVICEEN_R

Bit 15 - All external devices are same devices (both in types and size) for A1/A2/B1/B2.

pub fn sckbdiffopt(&self) -> SCKBDIFFOPT_R

Bit 19 - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set.

pub fn resumewait(&self) -> RESUMEWAIT_R

Bits 24:31 - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.

impl R<bool, APAREN_A>

pub fn variant(&self) -> APAREN_A

Get enumerated values variant

pub fn is_aparen_0(&self) -> bool

Checks if the value of the field is APAREN_0

pub fn is_aparen_1(&self) -> bool

Checks if the value of the field is APAREN_1

impl R<bool, CACHABLEEN_A>

pub fn variant(&self) -> CACHABLEEN_A

Get enumerated values variant

pub fn is_cachableen_0(&self) -> bool

Checks if the value of the field is CACHABLEEN_0

pub fn is_cachableen_1(&self) -> bool

Checks if the value of the field is CACHABLEEN_1

impl R<bool, BUFFERABLEEN_A>

pub fn variant(&self) -> BUFFERABLEEN_A

Get enumerated values variant

pub fn is_bufferableen_0(&self) -> bool

Checks if the value of the field is BUFFERABLEEN_0

pub fn is_bufferableen_1(&self) -> bool

Checks if the value of the field is BUFFERABLEEN_1

impl R<bool, READADDROPT_A>

pub fn variant(&self) -> READADDROPT_A

Get enumerated values variant

pub fn is_readaddropt_0(&self) -> bool

Checks if the value of the field is READADDROPT_0

pub fn is_readaddropt_1(&self) -> bool

Checks if the value of the field is READADDROPT_1

impl R<u32, Reg<u32, _AHBCR>>

pub fn aparen(&self) -> APAREN_R

Bit 0 - Parallel mode enabled for AHB triggered Command (both read and write) .

pub fn cachableen(&self) -> CACHABLEEN_R

Bit 3 - Enable AHB bus cachable read access support.

pub fn bufferableen(&self) -> BUFFERABLEEN_R

Bit 4 - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write.

pub fn prefetchen(&self) -> PREFETCHEN_R

Bit 5 - AHB Read Prefetch Enable.

pub fn readaddropt(&self) -> READADDROPT_R

Bit 6 - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.

impl R<u32, Reg<u32, _INTEN>>

pub fn ipcmddoneen(&self) -> IPCMDDONEEN_R

Bit 0 - IP triggered Command Sequences Execution finished interrupt enable.

pub fn ipcmdgeen(&self) -> IPCMDGEEN_R

Bit 1 - IP triggered Command Sequences Grant Timeout interrupt enable.

pub fn ahbcmdgeen(&self) -> AHBCMDGEEN_R

Bit 2 - AHB triggered Command Sequences Grant Timeout interrupt enable.

pub fn ipcmderren(&self) -> IPCMDERREN_R

Bit 3 - IP triggered Command Sequences Error Detected interrupt enable.

pub fn ahbcmderren(&self) -> AHBCMDERREN_R

Bit 4 - AHB triggered Command Sequences Error Detected interrupt enable.

pub fn iprxwaen(&self) -> IPRXWAEN_R

Bit 5 - IP RX FIFO WaterMark available interrupt enable.

pub fn iptxween(&self) -> IPTXWEEN_R

Bit 6 - IP TX FIFO WaterMark empty interrupt enable.

pub fn sckstopbyrden(&self) -> SCKSTOPBYRDEN_R

Bit 8 - SCK is stopped during command sequence because Async RX FIFO full interrupt enable.

pub fn sckstopbywren(&self) -> SCKSTOPBYWREN_R

Bit 9 - SCK is stopped during command sequence because Async TX FIFO empty interrupt enable.

pub fn ahbbustimeouten(&self) -> AHBBUSTIMEOUTEN_R

Bit 10 - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.

pub fn seqtimeouten(&self) -> SEQTIMEOUTEN_R

Bit 11 - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.

impl R<u32, Reg<u32, _INTR>>

pub fn ipcmddone(&self) -> IPCMDDONE_R

Bit 0 - IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated.

pub fn ipcmdge(&self) -> IPCMDGE_R

Bit 1 - IP triggered Command Sequences Grant Timeout interrupt.

pub fn ahbcmdge(&self) -> AHBCMDGE_R

Bit 2 - AHB triggered Command Sequences Grant Timeout interrupt.

pub fn ipcmderr(&self) -> IPCMDERR_R

Bit 3 - IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all.

pub fn ahbcmderr(&self) -> AHBCMDERR_R

Bit 4 - AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all.

pub fn iprxwa(&self) -> IPRXWA_R

Bit 5 - IP RX FIFO watermark available interrupt.

pub fn iptxwe(&self) -> IPTXWE_R

Bit 6 - IP TX FIFO watermark empty interrupt.

pub fn sckstopbyrd(&self) -> SCKSTOPBYRD_R

Bit 8 - SCK is stopped during command sequence because Async RX FIFO full interrupt.

pub fn sckstopbywr(&self) -> SCKSTOPBYWR_R

Bit 9 - SCK is stopped during command sequence because Async TX FIFO empty interrupt.

pub fn ahbbustimeout(&self) -> AHBBUSTIMEOUT_R

Bit 10 - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.

pub fn seqtimeout(&self) -> SEQTIMEOUT_R

Bit 11 - Sequence execution timeout interrupt.

impl R<u32, Reg<u32, _LUTKEY>>

pub fn key(&self) -> KEY_R

Bits 0:31 - The Key to lock or unlock LUT.

impl R<u32, Reg<u32, _LUTCR>>

pub fn lock(&self) -> LOCK_R

Bit 0 - Lock LUT

pub fn unlock(&self) -> UNLOCK_R

Bit 1 - Unlock LUT

impl R<u32, Reg<u32, _AHBRXBUF0CR0>>

pub fn bufsz(&self) -> BUFSZ_R

Bits 0:7 - AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details.

pub fn mstrid(&self) -> MSTRID_R

Bits 16:19 - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation.

pub fn priority(&self) -> PRIORITY_R

Bits 24:25 - This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details.

pub fn prefetchen(&self) -> PREFETCHEN_R

Bit 31 - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.

impl R<u32, Reg<u32, _AHBRXBUF1CR0>>

pub fn bufsz(&self) -> BUFSZ_R

Bits 0:7 - AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details.

pub fn mstrid(&self) -> MSTRID_R

Bits 16:19 - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation.

pub fn priority(&self) -> PRIORITY_R

Bits 24:25 - This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details.

pub fn prefetchen(&self) -> PREFETCHEN_R

Bit 31 - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.

impl R<u32, Reg<u32, _AHBRXBUF2CR0>>

pub fn bufsz(&self) -> BUFSZ_R

Bits 0:7 - AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details.

pub fn mstrid(&self) -> MSTRID_R

Bits 16:19 - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation.

pub fn priority(&self) -> PRIORITY_R

Bits 24:25 - This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details.

pub fn prefetchen(&self) -> PREFETCHEN_R

Bit 31 - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.

impl R<u32, Reg<u32, _AHBRXBUF3CR0>>

pub fn bufsz(&self) -> BUFSZ_R

Bits 0:7 - AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details.

pub fn mstrid(&self) -> MSTRID_R

Bits 16:19 - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation.

pub fn priority(&self) -> PRIORITY_R

Bits 24:25 - This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details.

pub fn prefetchen(&self) -> PREFETCHEN_R

Bit 31 - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.

impl R<u32, Reg<u32, _FLSHA1CR0>>

pub fn flshsz(&self) -> FLSHSZ_R

Bits 0:22 - Flash Size in KByte.

impl R<u32, Reg<u32, _FLSHA2CR0>>

pub fn flshsz(&self) -> FLSHSZ_R

Bits 0:22 - Flash Size in KByte.

impl R<u32, Reg<u32, _FLSHB1CR0>>

pub fn flshsz(&self) -> FLSHSZ_R

Bits 0:22 - Flash Size in KByte.

impl R<u32, Reg<u32, _FLSHB2CR0>>

pub fn flshsz(&self) -> FLSHSZ_R

Bits 0:22 - Flash Size in KByte.

impl R<bool, CSINTERVALUNIT_A>

pub fn variant(&self) -> CSINTERVALUNIT_A

Get enumerated values variant

pub fn is_csintervalunit_0(&self) -> bool

Checks if the value of the field is CSINTERVALUNIT_0

pub fn is_csintervalunit_1(&self) -> bool

Checks if the value of the field is CSINTERVALUNIT_1

impl R<u32, Reg<u32, _FLSHCR1>>

pub fn tcss(&self) -> TCSS_R

Bits 0:4 - Serial Flash CS setup time.

pub fn tcsh(&self) -> TCSH_R

Bits 5:9 - Serial Flash CS Hold time.

pub fn wa(&self) -> WA_R

Bit 10 - Word Addressable.

pub fn cas(&self) -> CAS_R

Bits 11:14 - Column Address Size.

pub fn csintervalunit(&self) -> CSINTERVALUNIT_R

Bit 15 - CS interval unit

pub fn csinterval(&self) -> CSINTERVAL_R

Bits 16:31 - This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0.

impl R<u8, AWRWAITUNIT_A>

pub fn variant(&self) -> AWRWAITUNIT_A

Get enumerated values variant

pub fn is_awrwaitunit_0(&self) -> bool

Checks if the value of the field is AWRWAITUNIT_0

pub fn is_awrwaitunit_1(&self) -> bool

Checks if the value of the field is AWRWAITUNIT_1

pub fn is_awrwaitunit_2(&self) -> bool

Checks if the value of the field is AWRWAITUNIT_2

pub fn is_awrwaitunit_3(&self) -> bool

Checks if the value of the field is AWRWAITUNIT_3

pub fn is_awrwaitunit_4(&self) -> bool

Checks if the value of the field is AWRWAITUNIT_4

pub fn is_awrwaitunit_5(&self) -> bool

Checks if the value of the field is AWRWAITUNIT_5

pub fn is_awrwaitunit_6(&self) -> bool

Checks if the value of the field is AWRWAITUNIT_6

pub fn is_awrwaitunit_7(&self) -> bool

Checks if the value of the field is AWRWAITUNIT_7

impl R<u32, Reg<u32, _FLSHCR2>>

pub fn ardseqid(&self) -> ARDSEQID_R

Bits 0:3 - Sequence Index for AHB Read triggered Command in LUT.

pub fn ardseqnum(&self) -> ARDSEQNUM_R

Bits 5:7 - Sequence Number for AHB Read triggered Command in LUT.

pub fn awrseqid(&self) -> AWRSEQID_R

Bits 8:11 - Sequence Index for AHB Write triggered Command.

pub fn awrseqnum(&self) -> AWRSEQNUM_R

Bits 13:15 - Sequence Number for AHB Write triggered Command.

pub fn awrwait(&self) -> AWRWAIT_R

Bits 16:27 - For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface

pub fn awrwaitunit(&self) -> AWRWAITUNIT_R

Bits 28:30 - AWRWAIT unit

pub fn clrinstrptr(&self) -> CLRINSTRPTR_R

Bit 31 - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details.

impl R<bool, WMOPT1_A>

pub fn variant(&self) -> WMOPT1_A

Get enumerated values variant

pub fn is_wmopt1_0(&self) -> bool

Checks if the value of the field is WMOPT1_0

pub fn is_wmopt1_1(&self) -> bool

Checks if the value of the field is WMOPT1_1

impl R<bool, WMENA_A>

pub fn variant(&self) -> WMENA_A

Get enumerated values variant

pub fn is_wmena_0(&self) -> bool

Checks if the value of the field is WMENA_0

pub fn is_wmena_1(&self) -> bool

Checks if the value of the field is WMENA_1

impl R<bool, WMENB_A>

pub fn variant(&self) -> WMENB_A

Get enumerated values variant

pub fn is_wmenb_0(&self) -> bool

Checks if the value of the field is WMENB_0

pub fn is_wmenb_1(&self) -> bool

Checks if the value of the field is WMENB_1

impl R<u32, Reg<u32, _FLSHCR4>>

pub fn wmopt1(&self) -> WMOPT1_R

Bit 0 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.

pub fn wmena(&self) -> WMENA_R

Bit 2 - Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set.

pub fn wmenb(&self) -> WMENB_R

Bit 3 - Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set.

impl R<u32, Reg<u32, _IPCR0>>

pub fn sfar(&self) -> SFAR_R

Bits 0:31 - Serial Flash Address for IP command.

impl R<bool, IPAREN_A>

pub fn variant(&self) -> IPAREN_A

Get enumerated values variant

pub fn is_iparen_0(&self) -> bool

Checks if the value of the field is IPAREN_0

pub fn is_iparen_1(&self) -> bool

Checks if the value of the field is IPAREN_1

impl R<u32, Reg<u32, _IPCR1>>

pub fn idatsz(&self) -> IDATSZ_R

Bits 0:15 - Flash Read/Program Data Size (in Bytes) for IP command.

pub fn iseqid(&self) -> ISEQID_R

Bits 16:19 - Sequence Index in LUT for IP command.

pub fn iseqnum(&self) -> ISEQNUM_R

Bits 24:26 - Sequence Number for IP command: ISEQNUM+1.

pub fn iparen(&self) -> IPAREN_R

Bit 31 - Parallel mode Enabled for IP command.

impl R<u32, Reg<u32, _IPCMD>>

pub fn trg(&self) -> TRG_R

Bit 0 - Setting this bit will trigger an IP Command.

impl R<bool, RXDMAEN_A>

pub fn variant(&self) -> RXDMAEN_A

Get enumerated values variant

pub fn is_rxdmaen_0(&self) -> bool

Checks if the value of the field is RXDMAEN_0

pub fn is_rxdmaen_1(&self) -> bool

Checks if the value of the field is RXDMAEN_1

impl R<u32, Reg<u32, _IPRXFCR>>

pub fn clriprxf(&self) -> CLRIPRXF_R

Bit 0 - Clear all valid data entries in IP RX FIFO.

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 1 - IP RX FIFO reading by DMA enabled.

pub fn rxwmrk(&self) -> RXWMRK_R

Bits 2:5 - Watermark level is (RXWMRK+1)*64 Bits.

impl R<bool, TXDMAEN_A>

pub fn variant(&self) -> TXDMAEN_A

Get enumerated values variant

pub fn is_txdmaen_0(&self) -> bool

Checks if the value of the field is TXDMAEN_0

pub fn is_txdmaen_1(&self) -> bool

Checks if the value of the field is TXDMAEN_1

impl R<u32, Reg<u32, _IPTXFCR>>

pub fn clriptxf(&self) -> CLRIPTXF_R

Bit 0 - Clear all valid data entries in IP TX FIFO.

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 1 - IP TX FIFO filling by DMA enabled.

pub fn txwmrk(&self) -> TXWMRK_R

Bits 2:5 - Watermark level is (TXWMRK+1)*64 Bits.

impl R<u32, Reg<u32, _DLLCR>>

pub fn dllen(&self) -> DLLEN_R

Bit 0 - DLL calibration enable.

pub fn dllreset(&self) -> DLLRESET_R

Bit 1 - Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation).

pub fn slvdlytarget(&self) -> SLVDLYTARGET_R

Bits 3:6 - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial clock).

pub fn ovrden(&self) -> OVRDEN_R

Bit 8 - Slave clock delay line delay cell number selection override enable.

pub fn ovrdval(&self) -> OVRDVAL_R

Bits 9:14 - Slave clock delay line delay cell number selection override value.

impl R<u8, ARBCMDSRC_A>

pub fn variant(&self) -> ARBCMDSRC_A

Get enumerated values variant

pub fn is_arbcmdsrc_0(&self) -> bool

Checks if the value of the field is ARBCMDSRC_0

pub fn is_arbcmdsrc_1(&self) -> bool

Checks if the value of the field is ARBCMDSRC_1

pub fn is_arbcmdsrc_2(&self) -> bool

Checks if the value of the field is ARBCMDSRC_2

pub fn is_arbcmdsrc_3(&self) -> bool

Checks if the value of the field is ARBCMDSRC_3

impl R<u32, Reg<u32, _STS0>>

pub fn seqidle(&self) -> SEQIDLE_R

Bit 0 - This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface.

pub fn arbidle(&self) -> ARBIDLE_R

Bit 1 - This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.

pub fn arbcmdsrc(&self) -> ARBCMDSRC_R

Bits 2:3 - This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).

impl R<u8, AHBCMDERRCODE_A>

pub fn variant(&self) -> Variant<u8, AHBCMDERRCODE_A>

Get enumerated values variant

pub fn is_ahbcmderrcode_0(&self) -> bool

Checks if the value of the field is AHBCMDERRCODE_0

pub fn is_ahbcmderrcode_2(&self) -> bool

Checks if the value of the field is AHBCMDERRCODE_2

pub fn is_ahbcmderrcode_3(&self) -> bool

Checks if the value of the field is AHBCMDERRCODE_3

pub fn is_ahbcmderrcode_4(&self) -> bool

Checks if the value of the field is AHBCMDERRCODE_4

pub fn is_ahbcmderrcode_5(&self) -> bool

Checks if the value of the field is AHBCMDERRCODE_5

pub fn is_ahbcmderrcode_14(&self) -> bool

Checks if the value of the field is AHBCMDERRCODE_14

impl R<u8, IPCMDERRCODE_A>

pub fn variant(&self) -> Variant<u8, IPCMDERRCODE_A>

Get enumerated values variant

pub fn is_ipcmderrcode_0(&self) -> bool

Checks if the value of the field is IPCMDERRCODE_0

pub fn is_ipcmderrcode_2(&self) -> bool

Checks if the value of the field is IPCMDERRCODE_2

pub fn is_ipcmderrcode_3(&self) -> bool

Checks if the value of the field is IPCMDERRCODE_3

pub fn is_ipcmderrcode_4(&self) -> bool

Checks if the value of the field is IPCMDERRCODE_4

pub fn is_ipcmderrcode_5(&self) -> bool

Checks if the value of the field is IPCMDERRCODE_5

pub fn is_ipcmderrcode_6(&self) -> bool

Checks if the value of the field is IPCMDERRCODE_6

pub fn is_ipcmderrcode_14(&self) -> bool

Checks if the value of the field is IPCMDERRCODE_14

pub fn is_ipcmderrcode_15(&self) -> bool

Checks if the value of the field is IPCMDERRCODE_15

impl R<u32, Reg<u32, _STS1>>

pub fn ahbcmderrid(&self) -> AHBCMDERRID_R

Bits 0:3 - Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).

pub fn ahbcmderrcode(&self) -> AHBCMDERRCODE_R

Bits 8:11 - Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).

pub fn ipcmderrid(&self) -> IPCMDERRID_R

Bits 16:19 - Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c).

pub fn ipcmderrcode(&self) -> IPCMDERRCODE_R

Bits 24:27 - Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c).

impl R<u32, Reg<u32, _STS2>>

pub fn aslvlock(&self) -> ASLVLOCK_R

Bit 0 - Flash A sample clock slave delay line locked.

pub fn areflock(&self) -> AREFLOCK_R

Bit 1 - Flash A sample clock reference delay line locked.

pub fn aslvsel(&self) -> ASLVSEL_R

Bits 2:7 - Flash A sample clock slave delay line delay cell number selection .

pub fn arefsel(&self) -> AREFSEL_R

Bits 8:13 - Flash A sample clock reference delay line delay cell number selection.

pub fn bslvlock(&self) -> BSLVLOCK_R

Bit 16 - Flash B sample clock slave delay line locked.

pub fn breflock(&self) -> BREFLOCK_R

Bit 17 - Flash B sample clock reference delay line locked.

pub fn bslvsel(&self) -> BSLVSEL_R

Bits 18:23 - Flash B sample clock slave delay line delay cell number selection.

pub fn brefsel(&self) -> BREFSEL_R

Bits 24:29 - Flash B sample clock reference delay line delay cell number selection.

impl R<u32, Reg<u32, _AHBSPNDSTS>>

pub fn active(&self) -> ACTIVE_R

Bit 0 - Indicates if an AHB read prefetch command sequence has been suspended.

pub fn bufid(&self) -> BUFID_R

Bits 1:3 - AHB RX BUF ID for suspended command sequence.

pub fn datlft(&self) -> DATLFT_R

Bits 16:31 - Left Data size for suspended command sequence (in byte).

impl R<u32, Reg<u32, _IPRXFSTS>>

pub fn fill(&self) -> FILL_R

Bits 0:7 - Fill level of IP RX FIFO.

pub fn rdcntr(&self) -> RDCNTR_R

Bits 16:31 - Total Read Data Counter: RDCNTR * 64 Bits.

impl R<u32, Reg<u32, _IPTXFSTS>>

pub fn fill(&self) -> FILL_R

Bits 0:7 - Fill level of IP TX FIFO.

pub fn wrcntr(&self) -> WRCNTR_R

Bits 16:31 - Total Write Data Counter: WRCNTR * 64 Bits.

impl R<u32, Reg<u32, _RFDR>>

pub fn rxdata(&self) -> RXDATA_R

Bits 0:31 - RX Data

impl R<u32, Reg<u32, _LUT>>

pub fn operand0(&self) -> OPERAND0_R

Bits 0:7 - OPERAND0

pub fn num_pads0(&self) -> NUM_PADS0_R

Bits 8:9 - NUM_PADS0

pub fn opcode0(&self) -> OPCODE0_R

Bits 10:15 - OPCODE

pub fn operand1(&self) -> OPERAND1_R

Bits 16:23 - OPERAND1

pub fn num_pads1(&self) -> NUM_PADS1_R

Bits 24:25 - NUM_PADS1

pub fn opcode1(&self) -> OPCODE1_R

Bits 26:31 - OPCODE1

Trait Implementations

impl<U, T, FI> PartialEq<FI> for R<U, T> where
    U: PartialEq,
    FI: Copy + Into<U>, 

fn eq(&self, other: &FI) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]fn ne(&self, other: &Rhs) -> bool

This method tests for !=.