Enum imxrt1062_ccm::cdcdr::SPDIF0_CLK_PODF_A

#[repr(u8)]pub enum SPDIF0_CLK_PODF_A {
    DIVIDE_1,
    DIVIDE_2,
    DIVIDE_3,
    DIVIDE_4,
    DIVIDE_5,
    DIVIDE_6,
    DIVIDE_7,
    DIVIDE_8,
}

Divider for spdif0 clock podf. Divider should be updated when output clock is gated.

Value on reset: 7

Variants

DIVIDE_1

0: Divide by 1

DIVIDE_2

1: Divide by 2

DIVIDE_3

2: Divide by 3

DIVIDE_4

3: Divide by 4

DIVIDE_5

4: Divide by 5

DIVIDE_6

5: Divide by 6

DIVIDE_7

6: Divide by 7

DIVIDE_8

7: Divide by 8

Trait Implementations

impl Clone for SPDIF0_CLK_PODF_A

fn clone(&self) -> SPDIF0_CLK_PODF_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for SPDIF0_CLK_PODF_A

impl Debug for SPDIF0_CLK_PODF_A

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.

impl From<SPDIF0_CLK_PODF_A> for u8

fn from(variant: SPDIF0_CLK_PODF_A) -> Self

Performs the conversion.

impl PartialEq<SPDIF0_CLK_PODF_A> for SPDIF0_CLK_PODF_A

fn eq(&self, other: &SPDIF0_CLK_PODF_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl StructuralPartialEq for SPDIF0_CLK_PODF_A