imxrt-ral 0.2.1-alpha

#![allow(non_snake_case, non_upper_case_globals)]
#![allow(non_camel_case_types)]
//! Crossbar Switch
//!
//! Used by: imxrt1051, imxrt1052

use crate::RWRegister;
#[cfg(not(feature = "nosync"))]
use core::marker::PhantomData;

/// Crossbar B Select Register 0
pub mod SEL0 {

    /// Input (XBARB_INn) to be muxed to XBARB_OUT0 (refer to Functional Description section for input/output assignment)
    pub mod SEL0 {
        /// Offset (0 bits)
        pub const offset: u16 = 0;
        /// Mask (6 bits: 0x3f << 0)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }

    /// Input (XBARB_INn) to be muxed to XBARB_OUT1 (refer to Functional Description section for input/output assignment)
    pub mod SEL1 {
        /// Offset (8 bits)
        pub const offset: u16 = 8;
        /// Mask (6 bits: 0x3f << 8)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }
}

/// Crossbar B Select Register 1
pub mod SEL1 {

    /// Input (XBARB_INn) to be muxed to XBARB_OUT2 (refer to Functional Description section for input/output assignment)
    pub mod SEL2 {
        /// Offset (0 bits)
        pub const offset: u16 = 0;
        /// Mask (6 bits: 0x3f << 0)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }

    /// Input (XBARB_INn) to be muxed to XBARB_OUT3 (refer to Functional Description section for input/output assignment)
    pub mod SEL3 {
        /// Offset (8 bits)
        pub const offset: u16 = 8;
        /// Mask (6 bits: 0x3f << 8)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }
}

/// Crossbar B Select Register 2
pub mod SEL2 {

    /// Input (XBARB_INn) to be muxed to XBARB_OUT4 (refer to Functional Description section for input/output assignment)
    pub mod SEL4 {
        /// Offset (0 bits)
        pub const offset: u16 = 0;
        /// Mask (6 bits: 0x3f << 0)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }

    /// Input (XBARB_INn) to be muxed to XBARB_OUT5 (refer to Functional Description section for input/output assignment)
    pub mod SEL5 {
        /// Offset (8 bits)
        pub const offset: u16 = 8;
        /// Mask (6 bits: 0x3f << 8)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }
}

/// Crossbar B Select Register 3
pub mod SEL3 {

    /// Input (XBARB_INn) to be muxed to XBARB_OUT6 (refer to Functional Description section for input/output assignment)
    pub mod SEL6 {
        /// Offset (0 bits)
        pub const offset: u16 = 0;
        /// Mask (6 bits: 0x3f << 0)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }

    /// Input (XBARB_INn) to be muxed to XBARB_OUT7 (refer to Functional Description section for input/output assignment)
    pub mod SEL7 {
        /// Offset (8 bits)
        pub const offset: u16 = 8;
        /// Mask (6 bits: 0x3f << 8)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }
}

/// Crossbar B Select Register 4
pub mod SEL4 {

    /// Input (XBARB_INn) to be muxed to XBARB_OUT8 (refer to Functional Description section for input/output assignment)
    pub mod SEL8 {
        /// Offset (0 bits)
        pub const offset: u16 = 0;
        /// Mask (6 bits: 0x3f << 0)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }

    /// Input (XBARB_INn) to be muxed to XBARB_OUT9 (refer to Functional Description section for input/output assignment)
    pub mod SEL9 {
        /// Offset (8 bits)
        pub const offset: u16 = 8;
        /// Mask (6 bits: 0x3f << 8)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }
}

/// Crossbar B Select Register 5
pub mod SEL5 {

    /// Input (XBARB_INn) to be muxed to XBARB_OUT10 (refer to Functional Description section for input/output assignment)
    pub mod SEL10 {
        /// Offset (0 bits)
        pub const offset: u16 = 0;
        /// Mask (6 bits: 0x3f << 0)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }

    /// Input (XBARB_INn) to be muxed to XBARB_OUT11 (refer to Functional Description section for input/output assignment)
    pub mod SEL11 {
        /// Offset (8 bits)
        pub const offset: u16 = 8;
        /// Mask (6 bits: 0x3f << 8)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }
}

/// Crossbar B Select Register 6
pub mod SEL6 {

    /// Input (XBARB_INn) to be muxed to XBARB_OUT12 (refer to Functional Description section for input/output assignment)
    pub mod SEL12 {
        /// Offset (0 bits)
        pub const offset: u16 = 0;
        /// Mask (6 bits: 0x3f << 0)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }

    /// Input (XBARB_INn) to be muxed to XBARB_OUT13 (refer to Functional Description section for input/output assignment)
    pub mod SEL13 {
        /// Offset (8 bits)
        pub const offset: u16 = 8;
        /// Mask (6 bits: 0x3f << 8)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }
}

/// Crossbar B Select Register 7
pub mod SEL7 {

    /// Input (XBARB_INn) to be muxed to XBARB_OUT14 (refer to Functional Description section for input/output assignment)
    pub mod SEL14 {
        /// Offset (0 bits)
        pub const offset: u16 = 0;
        /// Mask (6 bits: 0x3f << 0)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }

    /// Input (XBARB_INn) to be muxed to XBARB_OUT15 (refer to Functional Description section for input/output assignment)
    pub mod SEL15 {
        /// Offset (8 bits)
        pub const offset: u16 = 8;
        /// Mask (6 bits: 0x3f << 8)
        pub const mask: u16 = 0x3f << offset;
        /// Read-only values (empty)
        pub mod R {}
        /// Write-only values (empty)
        pub mod W {}
        /// Read-write values (empty)
        pub mod RW {}
    }
}
#[repr(C)]
pub struct RegisterBlock {
    /// Crossbar B Select Register 0
    pub SEL0: RWRegister<u16>,

    /// Crossbar B Select Register 1
    pub SEL1: RWRegister<u16>,

    /// Crossbar B Select Register 2
    pub SEL2: RWRegister<u16>,

    /// Crossbar B Select Register 3
    pub SEL3: RWRegister<u16>,

    /// Crossbar B Select Register 4
    pub SEL4: RWRegister<u16>,

    /// Crossbar B Select Register 5
    pub SEL5: RWRegister<u16>,

    /// Crossbar B Select Register 6
    pub SEL6: RWRegister<u16>,

    /// Crossbar B Select Register 7
    pub SEL7: RWRegister<u16>,
}
pub struct ResetValues {
    pub SEL0: u16,
    pub SEL1: u16,
    pub SEL2: u16,
    pub SEL3: u16,
    pub SEL4: u16,
    pub SEL5: u16,
    pub SEL6: u16,
    pub SEL7: u16,
}
#[cfg(not(feature = "nosync"))]
pub struct Instance {
    pub(crate) addr: u32,
    pub(crate) _marker: PhantomData<*const RegisterBlock>,
}
#[cfg(not(feature = "nosync"))]
impl ::core::ops::Deref for Instance {
    type Target = RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &RegisterBlock {
        unsafe { &*(self.addr as *const _) }
    }
}
#[cfg(feature = "rtfm")]
unsafe impl Send for Instance {}