imxrt-hal 0.5.14

Hardware abstraction layer for NXP i.MX RT microcontrollers.
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105

//! Custom RAL-like interface for SNVS components.
//!
//! This API allows us to separate the SNVS registers by functional
//! capabilities.

#![allow(unused, non_snake_case, non_upper_case_globals)] // Compatibility with RAL

/// Low power domain.
pub mod lp {
    /// Core SNVS registers.
    pub mod core {
        use crate::ral::RWRegister;

        /// Taken from the imxrt-ral definitions.
        #[repr(C)]
        pub struct RegisterBlock {
            /// SNVS_LP Lock Register
            pub LPLR: RWRegister<u32>,

            /// SNVS_LP Control Register
            pub LPCR: RWRegister<u32>,

            /// SNVS_LP Master Key Control Register
            pub LPMKCR: RWRegister<u32>,

            /// SNVS_LP Security Violation Control Register
            pub LPSVCR: RWRegister<u32>,

            _reserved1: [u32; 1],

            /// SNVS_LP Tamper Detectors Configuration Register
            pub LPTDCR: RWRegister<u32>,

            /// SNVS_LP Status Register
            pub LPSR: RWRegister<u32>,
        }

        pub mod LPLR {
            pub use crate::ral::snvs::LPLR::*;
        }

        pub mod LPCR {
            pub use crate::ral::snvs::LPCR::*;
        }

        pub mod LPSR {
            pub use crate::ral::snvs::LPSR::*;
        }
    }

    /// SRTC registers.
    pub mod srtc {
        use crate::ral::RWRegister;

        /// Taken from the imxrt-ral definitions.
        #[repr(C)]
        pub struct RegisterBlock {
            /// SNVS_LP Secure Real Time Counter MSB Register
            pub LPSRTCMR: RWRegister<u32>,

            /// SNVS_LP Secure Real Time Counter LSB Register
            pub LPSRTCLR: RWRegister<u32>,
        }

        pub mod LPSRTCMR {
            pub use crate::ral::snvs::LPSRTCMR::*;
        }
        pub mod LPSRTCLR {
            pub use crate::ral::snvs::LPSRTCLR::*;
        }
    }

    /// The core SNVS registers.
    pub type Core = super::Instance<core::RegisterBlock>;
    /// SRTC-specific registers.
    pub type Srtc = super::Instance<srtc::RegisterBlock>;
}

pub struct Instance<RB>(*const RB);
// Safety: OK to send, since pointer points to static peripheral memory.
unsafe impl<RB> Send for Instance<RB> {}

impl<RB> core::ops::Deref for Instance<RB> {
    type Target = RB;
    #[inline]
    fn deref(&self) -> &Self::Target {
        // Safety: inspection of this module shows that all pointers are derived from
        // valid static addresses.
        unsafe { &*self.0 }
    }
}

/// RAL components.
pub(super) struct Components {
    pub(super) lp_core: lp::Core,
    pub(super) lp_srtc: lp::Srtc,
}

/// Create SNVS components from the RAL instance.
pub(super) fn new(snvs: crate::ral::snvs::SNVS) -> Components {
    Components {
        lp_core: Instance(core::ptr::addr_of!(snvs.LPLR) as *const _),
        lp_srtc: Instance(core::ptr::addr_of!(snvs.LPSRTCMR) as *const _),
    }
}