ic_mu/
lib.rs

1#![no_std]
2
3use embedded_hal::spi::SpiDevice;
4use smallvec::SmallVec;
5
6pub struct ICMU<SPI> {
7    spi: SPI,
8    buf_tx: SmallVec<[u8; 256]>,
9    buf_rx: SmallVec<[u8; 256]>,
10}
11
12#[repr(u8)]
13enum Opcode {
14    Activate = 0xB0,
15    SdadTransmission = 0xA6,
16    SdadStatus = 0xF5,
17    ReadRegister = 0x97,
18    WriteRegister = 0xD2,
19    RegisterStatusData = 0xAD,
20}
21
22impl<SPI: SpiDevice> ICMU<SPI> {
23    pub fn new(spi: SPI) -> Self {
24        Self {
25            spi,
26            buf_tx: SmallVec::new(),
27            buf_rx: SmallVec::new(),
28        }
29    }
30
31    pub fn activate(&mut self, active_vector: &[u8]) -> Result<(), SPI::Error> {
32        self.buf_tx.push(Opcode::Activate as u8);
33        self.buf_tx.extend_from_slice(active_vector);
34
35        let ret = self.spi.write(&self.buf_tx);
36        self.buf_tx.clear();
37        ret
38    }
39
40    pub fn sdad_transmission(&mut self, data_rx: &mut [u8]) -> Result<(), SPI::Error> {
41        let bufsize = data_rx.len() + 1;
42        self.buf_tx.push(Opcode::SdadTransmission as u8);
43        self.buf_tx.resize(bufsize, 0);
44        self.buf_rx.resize(bufsize, 0);
45
46        let ret = self.spi.transfer(&mut self.buf_rx, &self.buf_tx);
47        data_rx.copy_from_slice(&self.buf_rx[1..bufsize]);
48        self.buf_tx.clear();
49        self.buf_rx.clear();
50        ret
51    }
52
53    pub fn sdad_status(&mut self, svalid_vector: &mut [u8]) -> Result<(), SPI::Error> {
54        let bufsize = svalid_vector.len() + 1;
55        self.buf_tx.push(Opcode::SdadStatus as u8);
56        self.buf_tx.resize(bufsize, 0);
57        self.buf_rx.resize(bufsize, 0);
58
59        let ret = self.spi.transfer(&mut self.buf_rx, &self.buf_tx);
60        svalid_vector.copy_from_slice(&self.buf_rx[1..bufsize]);
61        self.buf_tx.clear();
62        self.buf_rx.clear();
63        ret
64    }
65
66    pub fn read_register(&mut self, addr: u8) -> Result<(), SPI::Error> {
67        self.buf_tx.push(Opcode::ReadRegister as u8);
68        self.buf_tx.push(addr);
69
70        let ret = self.spi.write(&self.buf_tx);
71        self.buf_tx.clear();
72        ret
73    }
74
75    pub fn write_register(&mut self, addr: u8, data_tx: u8) -> Result<(), SPI::Error> {
76        self.buf_tx.push(Opcode::WriteRegister as u8);
77        self.buf_tx.push(addr);
78        self.buf_tx.push(data_tx);
79
80        let ret = self.spi.write(&self.buf_tx);
81        self.buf_tx.clear();
82        ret
83    }
84
85    pub fn register_status_data(&mut self) -> Result<(u8, u8), SPI::Error> {
86        self.buf_tx.push(Opcode::RegisterStatusData as u8);
87        self.buf_tx.resize(3, 0);
88
89        let ret = self.spi.transfer(&mut self.buf_rx, &self.buf_tx);
90        let status_rx = self.buf_rx[1];
91        let data_rx = self.buf_rx[2];
92        self.buf_tx.clear();
93        self.buf_rx.clear();
94        ret?;
95        Ok((status_rx, data_rx))
96    }
97}
ic_mu/lib.rs

ic_mu/
lib.rs
