hypervisor/consts/
vmx_cap.rs

1/*
2Copyright (c) 2016 Saurav Sachidanand
3
4Permission is hereby granted, free of charge, to any person obtaining a copy
5of this software and associated documentation files (the "Software"), to deal
6in the Software without restriction, including without limitation the rights
7to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8copies of the Software, and to permit persons to whom the Software is
9furnished to do so, subject to the following conditions:
10
11The above copyright notice and this permission notice shall be included in
12all copies or substantial portions of the Software.
13
14THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20THE SOFTWARE.
21*/
22
23//! VMX capability field values
24
25use libc::*;
26
27pub const PIN_BASED_INTR                     : uint64_t = 1 <<  0;
28pub const PIN_BASED_NMI                      : uint64_t = 1 <<  3;
29pub const PIN_BASED_VIRTUAL_NMI              : uint64_t = 1 <<  5;
30pub const PIN_BASED_PREEMPTION_TIMER         : uint64_t = 1 <<  6;
31pub const PIN_BASED_POSTED_INTR              : uint64_t = 1 <<  7;
32
33pub const CPU_BASED_IRQ_WND                  : uint64_t = 1 <<  2;
34pub const CPU_BASED_TSC_OFFSET               : uint64_t = 1 <<  3;
35pub const CPU_BASED_HLT                      : uint64_t = 1 <<  7;
36pub const CPU_BASED_INVLPG                   : uint64_t = 1 <<  9;
37pub const CPU_BASED_MWAIT                    : uint64_t = 1 << 10;
38pub const CPU_BASED_RDPMC                    : uint64_t = 1 << 11;
39pub const CPU_BASED_RDTSC                    : uint64_t = 1 << 12;
40pub const CPU_BASED_CR3_LOAD                 : uint64_t = 1 << 15;
41pub const CPU_BASED_CR3_STORE                : uint64_t = 1 << 16;
42pub const CPU_BASED_CR8_LOAD                 : uint64_t = 1 << 19;
43pub const CPU_BASED_CR8_STORE                : uint64_t = 1 << 20;
44pub const CPU_BASED_TPR_SHADOW               : uint64_t = 1 << 21;
45pub const CPU_BASED_VIRTUAL_NMI_WND          : uint64_t = 1 << 22;
46pub const CPU_BASED_MOV_DR                   : uint64_t = 1 << 23;
47pub const CPU_BASED_UNCOND_IO                : uint64_t = 1 << 24;
48pub const CPU_BASED_IO_BITMAPS               : uint64_t = 1 << 25;
49pub const CPU_BASED_MTF                      : uint64_t = 1 << 27;
50pub const CPU_BASED_MSR_BITMAPS              : uint64_t = 1 << 28;
51pub const CPU_BASED_MONITOR                  : uint64_t = 1 << 29;
52pub const CPU_BASED_PAUSE                    : uint64_t = 1 << 30;
53pub const CPU_BASED_SECONDARY_CTLS           : uint64_t = 1 << 31;
54
55pub const CPU_BASED2_VIRTUAL_APIC            : uint64_t = 1 <<  0;
56pub const CPU_BASED2_EPT                     : uint64_t = 1 <<  1;
57pub const CPU_BASED2_DESC_TABLE              : uint64_t = 1 <<  2;
58pub const CPU_BASED2_RDTSCP                  : uint64_t = 1 <<  3;
59pub const CPU_BASED2_X2APIC                  : uint64_t = 1 <<  4;
60pub const CPU_BASED2_VPID                    : uint64_t = 1 <<  5;
61pub const CPU_BASED2_WBINVD                  : uint64_t = 1 <<  6;
62pub const CPU_BASED2_UNRESTRICTED            : uint64_t = 1 <<  7;
63pub const CPU_BASED2_APIC_REG_VIRT           : uint64_t = 1 <<  8;
64pub const CPU_BASED2_VIRT_INTR_DELIVERY      : uint64_t = 1 <<  9;
65pub const CPU_BASED2_PAUSE_LOOP              : uint64_t = 1 << 10;
66pub const CPU_BASED2_RDRAND                  : uint64_t = 1 << 11;
67pub const CPU_BASED2_INVPCID                 : uint64_t = 1 << 12;
68pub const CPU_BASED2_VMFUNC                  : uint64_t = 1 << 13;
69pub const CPU_BASED2_VMCS_SHADOW             : uint64_t = 1 << 14;
70pub const CPU_BASED2_RDSEED                  : uint64_t = 1 << 16;
71pub const CPU_BASED2_EPT_VE                  : uint64_t = 1 << 18;
72pub const CPU_BASED2_XSAVES_XRSTORS          : uint64_t = 1 << 20;
73
74pub const VMX_EPT_VPID_SUPPORT_AD            : uint64_t = 1 << 21;
75pub const VMX_EPT_VPID_SUPPORT_EXONLY        : uint64_t = 1 <<  0;
76
77pub const VMEXIT_SAVE_DBG_CONTROLS           : uint64_t = 1 <<  2;
78pub const VMEXIT_HOST_IA32E                  : uint64_t = 1 <<  9;
79pub const VMEXIT_LOAD_IA32_PERF_GLOBAL_CTRL  : uint64_t = 1 << 12;
80pub const VMEXIT_ACK_INTR                    : uint64_t = 1 << 15;
81pub const VMEXIT_SAVE_IA32_PAT               : uint64_t = 1 << 18;
82pub const VMEXIT_LOAD_IA32_PAT               : uint64_t = 1 << 19;
83pub const VMEXIT_SAVE_EFER                   : uint64_t = 1 << 20;
84pub const VMEXIT_LOAD_EFER                   : uint64_t = 1 << 21;
85pub const VMEXIT_SAVE_VMX_TIMER              : uint64_t = 1 << 22;
86
87pub const VMENTRY_LOAD_DBG_CONTROLS          : uint64_t = 1 <<  2;
88pub const VMENTRY_GUEST_IA32E                : uint64_t = 1 <<  9;
89pub const VMENTRY_SMM                        : uint64_t = 1 << 10;
90pub const VMENTRY_DEACTIVATE_DUAL_MONITOR    : uint64_t = 1 << 11;
91pub const VMENTRY_LOAD_IA32_PERF_GLOBAL_CTRL : uint64_t = 1 << 13;
92pub const VMENTRY_LOAD_IA32_PAT              : uint64_t = 1 << 14;
93pub const VMENTRY_LOAD_EFER                  : uint64_t = 1 << 15;
hypervisor/consts/vmx_cap.rs

hypervisor/consts/
vmx_cap.rs
