---
source: hugr-llvm/src/extension/int.rs
expression: mod_str
---
; ModuleID = 'test_context'
source_filename = "test_context"
@0 = private unnamed_addr constant [24 x i8] c"Attempted division by 0\00", align 1
@prelude.panic_template = private unnamed_addr constant [34 x i8] c"Program panicked (signal %i): %s\0A\00", align 1
define internal i8 @_hl.main.1(i8 %0, i8 %1) !dbg !3 {
alloca_block:
%"0" = alloca i8, align 1
%"2_0" = alloca i8, align 1
%"2_1" = alloca i8, align 1
%"4_0" = alloca i8, align 1
br label %entry_block
entry_block: ; preds = %alloca_block
store i8 %0, ptr %"2_0", align 1
store i8 %1, ptr %"2_1", align 1
%"2_01" = load i8, ptr %"2_0", align 1
%"2_12" = load i8, ptr %"2_1", align 1
%valid_div = icmp ne i8 %"2_12", 0, !dbg !8
br label %panic_if_0, !dbg !8
panic_if_0: ; preds = %entry_block
switch i1 %valid_div, label %panic [
i1 true, label %exit
], !dbg !8
panic: ; preds = %panic_if_0
%2 = call i32 (ptr, ...) @printf(ptr @prelude.panic_template, i32 2, ptr @0), !dbg !8
call void @abort(), !dbg !8
br label %exit, !dbg !8
exit: ; preds = %panic_if_0, %panic
%is_divisor_large = icmp ugt i8 %"2_12", 127, !dbg !8
%3 = zext i1 %is_divisor_large to i8, !dbg !8
%is_dividend_negative = icmp slt i8 %"2_01", 0, !dbg !8
%4 = zext i1 %is_dividend_negative to i8, !dbg !8
%5 = shl i8 %3, 1, !dbg !8
%tag = or i8 %5, %4, !dbg !8
%quotient = sdiv i8 %"2_01", %"2_12", !dbg !8
%remainder = srem i8 %"2_01", %"2_12", !dbg !8
%result = alloca { i8, i8 }, align 8, !dbg !8
switch i8 %tag, label %non_negative_smoldiv [
i8 1, label %negative_smoldiv
i8 2, label %non_negative_bigdiv
i8 3, label %negative_bigdiv
], !dbg !8
negative_bigdiv: ; preds = %exit
%6 = add i8 %"2_01", %"2_12", !dbg !8
%7 = insertvalue { i8, i8 } { i8 -1, i8 poison }, i8 %6, 1, !dbg !8
store { i8, i8 } %7, ptr %result, align 1, !dbg !8
br label %finish, !dbg !8
negative_smoldiv: ; preds = %exit
%8 = insertvalue { i8, i8 } poison, i8 %quotient, 0, !dbg !8
%9 = insertvalue { i8, i8 } %8, i8 0, 1, !dbg !8
%10 = sub i8 %quotient, 1, !dbg !8
%11 = add i8 %"2_12", %remainder, !dbg !8
%12 = insertvalue { i8, i8 } poison, i8 %10, 0, !dbg !8
%13 = insertvalue { i8, i8 } %12, i8 %11, 1, !dbg !8
%is_rem_0 = icmp eq i8 %remainder, 0, !dbg !8
%14 = select i1 %is_rem_0, { i8, i8 } %9, { i8, i8 } %13, !dbg !8
store { i8, i8 } %14, ptr %result, align 1, !dbg !8
br label %finish, !dbg !8
non_negative_bigdiv: ; preds = %exit
%15 = insertvalue { i8, i8 } { i8 0, i8 poison }, i8 %"2_01", 1, !dbg !8
store { i8, i8 } %15, ptr %result, align 1, !dbg !8
br label %finish, !dbg !8
non_negative_smoldiv: ; preds = %exit
%16 = insertvalue { i8, i8 } poison, i8 %quotient, 0, !dbg !8
%17 = insertvalue { i8, i8 } %16, i8 %remainder, 1, !dbg !8
store { i8, i8 } %17, ptr %result, align 1, !dbg !8
br label %finish, !dbg !8
finish: ; preds = %negative_bigdiv, %non_negative_bigdiv, %negative_smoldiv, %non_negative_smoldiv
%result3 = load { i8, i8 }, ptr %result, align 1, !dbg !8
%18 = extractvalue { i8, i8 } %result3, 0, !dbg !8
%19 = extractvalue { i8, i8 } %result3, 1, !dbg !8
store i8 %19, ptr %"4_0", align 1, !dbg !8
%"4_04" = load i8, ptr %"4_0", align 1
store i8 %"4_04", ptr %"0", align 1
%"05" = load i8, ptr %"0", align 1
ret i8 %"05"
}
declare i32 @printf(ptr, ...)
declare void @abort()
!llvm.module.flags = !{!0}
!llvm.dbg.cu = !{!1}
!0 = !{i32 2, !"Debug Info Version", i32 3}
!1 = distinct !DICompileUnit(language: DW_LANG_Python, file: !2, producer: "hugr_llvm_test", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug)
!2 = !DIFile(filename: "/cmJrSnVYeXFf/zCkHdtWCCnkJhPKiWSKICgZuRNRvR/mbrfVq.gpy.py", directory: "/lPNzlV/ClAphFG/yrhvZs/eDgUn/eIVwAutKJHaZEPSZwPXPeycUvnujGxZ")
!3 = distinct !DISubprogram(name: "_hl.main.1", linkageName: "_hl.main.1", scope: null, file: !4, line: 25254, type: !5, scopeLine: 25255, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition, unit: !1)
!4 = !DIFile(filename: "/cmJrSnVYeXFf/zCkHdtWCCnkJhPKiWSKICgZuRNRvR/mbrfVq.gpy.py", directory: "")
!5 = !DISubroutineType(types: !6)
!6 = !{!7, !7, !7}
!7 = !DIBasicType(name: "i8", size: 8, encoding: DW_ATE_unsigned)
!8 = !DILocation(line: 27062, column: 402, scope: !3)