#[doc = "AHBENR"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahbenr(pub u32);
impl Ahbenr {
#[doc = "SRAM interface clock enable"]
#[must_use]
#[inline(always)]
pub const fn sramen(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "SRAM interface clock enable"]
#[inline(always)]
pub const fn set_sramen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "FLASH interface clock enable"]
#[must_use]
#[inline(always)]
pub const fn fliten(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "FLASH interface clock enable"]
#[inline(always)]
pub const fn set_fliten(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "I/O port A clock enable"]
#[must_use]
#[inline(always)]
pub const fn iopaen(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "I/O port A clock enable"]
#[inline(always)]
pub const fn set_iopaen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "I/O port B clock enable"]
#[must_use]
#[inline(always)]
pub const fn iopben(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "I/O port B clock enable"]
#[inline(always)]
pub const fn set_iopben(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "I/O port C clock enable"]
#[must_use]
#[inline(always)]
pub const fn iopcen(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "I/O port C clock enable"]
#[inline(always)]
pub const fn set_iopcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "CRC clock enable"]
#[must_use]
#[inline(always)]
pub const fn crcen(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "CRC clock enable"]
#[inline(always)]
pub const fn set_crcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
}
impl Default for Ahbenr {
#[inline(always)]
fn default() -> Ahbenr {
Ahbenr(0)
}
}
impl core::fmt::Debug for Ahbenr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahbenr")
.field("sramen", &self.sramen())
.field("fliten", &self.fliten())
.field("iopaen", &self.iopaen())
.field("iopben", &self.iopben())
.field("iopcen", &self.iopcen())
.field("crcen", &self.crcen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahbenr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahbenr {{ sramen: {=bool:?}, fliten: {=bool:?}, iopaen: {=bool:?}, iopben: {=bool:?}, iopcen: {=bool:?}, crcen: {=bool:?} }}" , self . sramen () , self . fliten () , self . iopaen () , self . iopben () , self . iopcen () , self . crcen ())
}
}
#[doc = "AHBRSTR"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ahbrstr(pub u32);
impl Ahbrstr {
#[doc = "Reset I/O port A"]
#[must_use]
#[inline(always)]
pub const fn ioparst(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Reset I/O port A"]
#[inline(always)]
pub const fn set_ioparst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "Reset I/O port B"]
#[must_use]
#[inline(always)]
pub const fn iopbrst(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "Reset I/O port B"]
#[inline(always)]
pub const fn set_iopbrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "Reset I/O port C"]
#[must_use]
#[inline(always)]
pub const fn iopcrst(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Reset I/O port C"]
#[inline(always)]
pub const fn set_iopcrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Reset CRC"]
#[must_use]
#[inline(always)]
pub const fn crcrst(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "Reset CRC"]
#[inline(always)]
pub const fn set_crcrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
}
impl Default for Ahbrstr {
#[inline(always)]
fn default() -> Ahbrstr {
Ahbrstr(0)
}
}
impl core::fmt::Debug for Ahbrstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ahbrstr")
.field("ioparst", &self.ioparst())
.field("iopbrst", &self.iopbrst())
.field("iopcrst", &self.iopcrst())
.field("crcrst", &self.crcrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ahbrstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Ahbrstr {{ ioparst: {=bool:?}, iopbrst: {=bool:?}, iopcrst: {=bool:?}, crcrst: {=bool:?} }}" , self . ioparst () , self . iopbrst () , self . iopcrst () , self . crcrst ())
}
}
#[doc = "APB1ENR"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1enr(pub u32);
impl Apb1enr {
#[doc = "TIMC5 clock enable"]
#[must_use]
#[inline(always)]
pub const fn timc5en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "TIMC5 clock enable"]
#[inline(always)]
pub const fn set_timc5en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIM6 clock enable"]
#[must_use]
#[inline(always)]
pub const fn tim6en(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "TIM6 clock enable"]
#[inline(always)]
pub const fn set_tim6en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "WWDG clock enable"]
#[must_use]
#[inline(always)]
pub const fn wwdgen(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "WWDG clock enable"]
#[inline(always)]
pub const fn set_wwdgen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "UART2 clock enable"]
#[must_use]
#[inline(always)]
pub const fn uart2en(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "UART2 clock enable"]
#[inline(always)]
pub const fn set_uart2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "I2C clock enable"]
#[must_use]
#[inline(always)]
pub const fn i2cen(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "I2C clock enable"]
#[inline(always)]
pub const fn set_i2cen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "PWR clock enable"]
#[must_use]
#[inline(always)]
pub const fn pwren(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "PWR clock enable"]
#[inline(always)]
pub const fn set_pwren(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "LPTIM clock enable"]
#[must_use]
#[inline(always)]
pub const fn lptimen(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "LPTIM clock enable"]
#[inline(always)]
pub const fn set_lptimen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Apb1enr {
#[inline(always)]
fn default() -> Apb1enr {
Apb1enr(0)
}
}
impl core::fmt::Debug for Apb1enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1enr")
.field("timc5en", &self.timc5en())
.field("tim6en", &self.tim6en())
.field("wwdgen", &self.wwdgen())
.field("uart2en", &self.uart2en())
.field("i2cen", &self.i2cen())
.field("pwren", &self.pwren())
.field("lptimen", &self.lptimen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1enr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb1enr {{ timc5en: {=bool:?}, tim6en: {=bool:?}, wwdgen: {=bool:?}, uart2en: {=bool:?}, i2cen: {=bool:?}, pwren: {=bool:?}, lptimen: {=bool:?} }}" , self . timc5en () , self . tim6en () , self . wwdgen () , self . uart2en () , self . i2cen () , self . pwren () , self . lptimen ())
}
}
#[doc = "APB1RSTR"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb1rstr(pub u32);
impl Apb1rstr {
#[doc = "Reset TIMC5"]
#[must_use]
#[inline(always)]
pub const fn timc5rst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Reset TIMC5"]
#[inline(always)]
pub const fn set_timc5rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Reset TIM6"]
#[must_use]
#[inline(always)]
pub const fn tim6rst(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "Reset TIM6"]
#[inline(always)]
pub const fn set_tim6rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "Reset WWDG"]
#[must_use]
#[inline(always)]
pub const fn wwdgrst(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[doc = "Reset WWDG"]
#[inline(always)]
pub const fn set_wwdgrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
#[doc = "Reset UART2"]
#[must_use]
#[inline(always)]
pub const fn uart2rst(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "Reset UART2"]
#[inline(always)]
pub const fn set_uart2rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "Reset I2C"]
#[must_use]
#[inline(always)]
pub const fn i2crst(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "Reset I2C"]
#[inline(always)]
pub const fn set_i2crst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "Reset PWR interface"]
#[must_use]
#[inline(always)]
pub const fn pwrrst(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Reset PWR interface"]
#[inline(always)]
pub const fn set_pwrrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "Reset LPTIM"]
#[must_use]
#[inline(always)]
pub const fn lptimrst(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "Reset LPTIM"]
#[inline(always)]
pub const fn set_lptimrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Apb1rstr {
#[inline(always)]
fn default() -> Apb1rstr {
Apb1rstr(0)
}
}
impl core::fmt::Debug for Apb1rstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb1rstr")
.field("timc5rst", &self.timc5rst())
.field("tim6rst", &self.tim6rst())
.field("wwdgrst", &self.wwdgrst())
.field("uart2rst", &self.uart2rst())
.field("i2crst", &self.i2crst())
.field("pwrrst", &self.pwrrst())
.field("lptimrst", &self.lptimrst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb1rstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb1rstr {{ timc5rst: {=bool:?}, tim6rst: {=bool:?}, wwdgrst: {=bool:?}, uart2rst: {=bool:?}, i2crst: {=bool:?}, pwrrst: {=bool:?}, lptimrst: {=bool:?} }}" , self . timc5rst () , self . tim6rst () , self . wwdgrst () , self . uart2rst () , self . i2crst () , self . pwrrst () , self . lptimrst ())
}
}
#[doc = "APB2ENR"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb2enr(pub u32);
impl Apb2enr {
#[doc = "SYSCFG clock enable"]
#[must_use]
#[inline(always)]
pub const fn syscfgen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "SYSCFG clock enable"]
#[inline(always)]
pub const fn set_syscfgen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "TIMC11 clock enable"]
#[must_use]
#[inline(always)]
pub const fn timc11en(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "TIMC11 clock enable"]
#[inline(always)]
pub const fn set_timc11en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "ADC clock enable"]
#[must_use]
#[inline(always)]
pub const fn adcen(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "ADC clock enable"]
#[inline(always)]
pub const fn set_adcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "SPI clock enable"]
#[must_use]
#[inline(always)]
pub const fn spien(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "SPI clock enable"]
#[inline(always)]
pub const fn set_spien(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "UART1 clock enable"]
#[must_use]
#[inline(always)]
pub const fn uart1en(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "UART1 clock enable"]
#[inline(always)]
pub const fn set_uart1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "DBGMCU clock enable"]
#[must_use]
#[inline(always)]
pub const fn dbgmcuen(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "DBGMCU clock enable"]
#[inline(always)]
pub const fn set_dbgmcuen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "COMP clock enable"]
#[must_use]
#[inline(always)]
pub const fn compen(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "COMP clock enable"]
#[inline(always)]
pub const fn set_compen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
}
impl Default for Apb2enr {
#[inline(always)]
fn default() -> Apb2enr {
Apb2enr(0)
}
}
impl core::fmt::Debug for Apb2enr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb2enr")
.field("syscfgen", &self.syscfgen())
.field("timc11en", &self.timc11en())
.field("adcen", &self.adcen())
.field("spien", &self.spien())
.field("uart1en", &self.uart1en())
.field("dbgmcuen", &self.dbgmcuen())
.field("compen", &self.compen())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb2enr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb2enr {{ syscfgen: {=bool:?}, timc11en: {=bool:?}, adcen: {=bool:?}, spien: {=bool:?}, uart1en: {=bool:?}, dbgmcuen: {=bool:?}, compen: {=bool:?} }}" , self . syscfgen () , self . timc11en () , self . adcen () , self . spien () , self . uart1en () , self . dbgmcuen () , self . compen ())
}
}
#[doc = "APB2RSTR"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Apb2rstr(pub u32);
impl Apb2rstr {
#[doc = "Reset SYSCFG"]
#[must_use]
#[inline(always)]
pub const fn syscfgrst(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Reset SYSCFG"]
#[inline(always)]
pub const fn set_syscfgrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Reset TIMC11"]
#[must_use]
#[inline(always)]
pub const fn timc11rst(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Reset TIMC11"]
#[inline(always)]
pub const fn set_timc11rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "Reset ADC"]
#[must_use]
#[inline(always)]
pub const fn adcrst(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "Reset ADC"]
#[inline(always)]
pub const fn set_adcrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "Reset SPI"]
#[must_use]
#[inline(always)]
pub const fn spirst(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "Reset SPI"]
#[inline(always)]
pub const fn set_spirst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "Reset UART1"]
#[must_use]
#[inline(always)]
pub const fn uart1rst(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "Reset UART1"]
#[inline(always)]
pub const fn set_uart1rst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "Reset DBGMCU"]
#[must_use]
#[inline(always)]
pub const fn dbgmcurst(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "Reset DBGMCU"]
#[inline(always)]
pub const fn set_dbgmcurst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "Reset COMP"]
#[must_use]
#[inline(always)]
pub const fn comprst(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Reset COMP"]
#[inline(always)]
pub const fn set_comprst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
}
impl Default for Apb2rstr {
#[inline(always)]
fn default() -> Apb2rstr {
Apb2rstr(0)
}
}
impl core::fmt::Debug for Apb2rstr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Apb2rstr")
.field("syscfgrst", &self.syscfgrst())
.field("timc11rst", &self.timc11rst())
.field("adcrst", &self.adcrst())
.field("spirst", &self.spirst())
.field("uart1rst", &self.uart1rst())
.field("dbgmcurst", &self.dbgmcurst())
.field("comprst", &self.comprst())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Apb2rstr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Apb2rstr {{ syscfgrst: {=bool:?}, timc11rst: {=bool:?}, adcrst: {=bool:?}, spirst: {=bool:?}, uart1rst: {=bool:?}, dbgmcurst: {=bool:?}, comprst: {=bool:?} }}" , self . syscfgrst () , self . timc11rst () , self . adcrst () , self . spirst () , self . uart1rst () , self . dbgmcurst () , self . comprst ())
}
}
#[doc = "BDCR"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Bdcr(pub u32);
impl Bdcr {
#[doc = "LSE oscillator enable"]
#[must_use]
#[inline(always)]
pub const fn lseon(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator enable"]
#[inline(always)]
pub const fn set_lseon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE oscillator ready"]
#[must_use]
#[inline(always)]
pub const fn lserdy(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator ready"]
#[inline(always)]
pub const fn set_lserdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "LSE oscillator bypass"]
#[must_use]
#[inline(always)]
pub const fn lsebyp(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "LSE oscillator bypass"]
#[inline(always)]
pub const fn set_lsebyp(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "LSE oscillator drive capability"]
#[must_use]
#[inline(always)]
pub const fn lsedrv(&self) -> u8 {
let val = (self.0 >> 3usize) & 0x03;
val as u8
}
#[doc = "LSE oscillator drive capability"]
#[inline(always)]
pub const fn set_lsedrv(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 3usize)) | (((val as u32) & 0x03) << 3usize);
}
}
impl Default for Bdcr {
#[inline(always)]
fn default() -> Bdcr {
Bdcr(0)
}
}
impl core::fmt::Debug for Bdcr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Bdcr")
.field("lseon", &self.lseon())
.field("lserdy", &self.lserdy())
.field("lsebyp", &self.lsebyp())
.field("lsedrv", &self.lsedrv())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Bdcr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Bdcr {{ lseon: {=bool:?}, lserdy: {=bool:?}, lsebyp: {=bool:?}, lsedrv: {=u8:?} }}",
self.lseon(),
self.lserdy(),
self.lsebyp(),
self.lsedrv()
)
}
}
#[doc = "CFGR"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cfgr(pub u32);
impl Cfgr {
#[doc = "System clock switch"]
#[must_use]
#[inline(always)]
pub const fn sw(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x07;
val as u8
}
#[doc = "System clock switch"]
#[inline(always)]
pub const fn set_sw(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
}
#[doc = "System clock switch status"]
#[must_use]
#[inline(always)]
pub const fn sws(&self) -> u8 {
let val = (self.0 >> 3usize) & 0x07;
val as u8
}
#[doc = "System clock switch status"]
#[inline(always)]
pub const fn set_sws(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
}
#[doc = "HCLK prescaler factor"]
#[must_use]
#[inline(always)]
pub const fn hpre(&self) -> u8 {
let val = (self.0 >> 6usize) & 0x03;
val as u8
}
#[doc = "HCLK prescaler factor"]
#[inline(always)]
pub const fn set_hpre(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 6usize)) | (((val as u32) & 0x03) << 6usize);
}
#[doc = "APB PCLK prescaler factor"]
#[must_use]
#[inline(always)]
pub const fn ppre(&self) -> u8 {
let val = (self.0 >> 10usize) & 0x03;
val as u8
}
#[doc = "APB PCLK prescaler factor"]
#[inline(always)]
pub const fn set_ppre(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
}
#[doc = "External clock pin selection"]
#[must_use]
#[inline(always)]
pub const fn extclk_sel(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "External clock pin selection"]
#[inline(always)]
pub const fn set_extclk_sel(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "Microcontroller clock output"]
#[must_use]
#[inline(always)]
pub const fn mco(&self) -> u8 {
let val = (self.0 >> 24usize) & 0x0f;
val as u8
}
#[doc = "Microcontroller clock output"]
#[inline(always)]
pub const fn set_mco(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
}
}
impl Default for Cfgr {
#[inline(always)]
fn default() -> Cfgr {
Cfgr(0)
}
}
impl core::fmt::Debug for Cfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cfgr")
.field("sw", &self.sw())
.field("sws", &self.sws())
.field("hpre", &self.hpre())
.field("ppre", &self.ppre())
.field("extclk_sel", &self.extclk_sel())
.field("mco", &self.mco())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cfgr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cfgr {{ sw: {=u8:?}, sws: {=u8:?}, hpre: {=u8:?}, ppre: {=u8:?}, extclk_sel: {=bool:?}, mco: {=u8:?} }}" , self . sw () , self . sws () , self . hpre () , self . ppre () , self . extclk_sel () , self . mco ())
}
}
#[doc = "CFGR3"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cfgr3(pub u32);
impl Cfgr3 {
#[doc = "LPTIM clock input selection"]
#[must_use]
#[inline(always)]
pub const fn lptim_sel(&self) -> u8 {
let val = (self.0 >> 3usize) & 0x03;
val as u8
}
#[doc = "LPTIM clock input selection"]
#[inline(always)]
pub const fn set_lptim_sel(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 3usize)) | (((val as u32) & 0x03) << 3usize);
}
}
impl Default for Cfgr3 {
#[inline(always)]
fn default() -> Cfgr3 {
Cfgr3(0)
}
}
impl core::fmt::Debug for Cfgr3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cfgr3")
.field("lptim_sel", &self.lptim_sel())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cfgr3 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Cfgr3 {{ lptim_sel: {=u8:?} }}", self.lptim_sel())
}
}
#[doc = "CIR"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cir(pub u32);
impl Cir {
#[doc = "LSI ready interrupt flag"]
#[must_use]
#[inline(always)]
pub const fn lsirdyf(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt flag"]
#[inline(always)]
pub const fn set_lsirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSE ready interrupt flag"]
#[must_use]
#[inline(always)]
pub const fn lserdyf(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt flag"]
#[inline(always)]
pub const fn set_lserdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "HSI ready interrupt flag"]
#[must_use]
#[inline(always)]
pub const fn hsirdyf(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt flag"]
#[inline(always)]
pub const fn set_hsirdyf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "CSSLSE interrupt flag"]
#[must_use]
#[inline(always)]
pub const fn csslsef(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "CSSLSE interrupt flag"]
#[inline(always)]
pub const fn set_csslsef(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "LSI ready interrupt enable"]
#[must_use]
#[inline(always)]
pub const fn lsirdyie(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt enable"]
#[inline(always)]
pub const fn set_lsirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "LSE ready interrupt enable"]
#[must_use]
#[inline(always)]
pub const fn lserdyie(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt enable"]
#[inline(always)]
pub const fn set_lserdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "HSI ready interrupt enable"]
#[must_use]
#[inline(always)]
pub const fn hsirdyie(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt enable"]
#[inline(always)]
pub const fn set_hsirdyie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "CSSLSE interrupt enable"]
#[must_use]
#[inline(always)]
pub const fn csslseie(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "CSSLSE interrupt enable"]
#[inline(always)]
pub const fn set_csslseie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "LSI ready interrupt clear"]
#[must_use]
#[inline(always)]
pub const fn lsirdyc(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "LSI ready interrupt clear"]
#[inline(always)]
pub const fn set_lsirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "LSE ready interrupt clear"]
#[must_use]
#[inline(always)]
pub const fn lserdyc(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "LSE ready interrupt clear"]
#[inline(always)]
pub const fn set_lserdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "HSI ready interrupt clear"]
#[must_use]
#[inline(always)]
pub const fn hsirdyc(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "HSI ready interrupt clear"]
#[inline(always)]
pub const fn set_hsirdyc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "Clock security system LSE interrupt flag clear"]
#[must_use]
#[inline(always)]
pub const fn csslsec(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "Clock security system LSE interrupt flag clear"]
#[inline(always)]
pub const fn set_csslsec(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
}
impl Default for Cir {
#[inline(always)]
fn default() -> Cir {
Cir(0)
}
}
impl core::fmt::Debug for Cir {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cir")
.field("lsirdyf", &self.lsirdyf())
.field("lserdyf", &self.lserdyf())
.field("hsirdyf", &self.hsirdyf())
.field("csslsef", &self.csslsef())
.field("lsirdyie", &self.lsirdyie())
.field("lserdyie", &self.lserdyie())
.field("hsirdyie", &self.hsirdyie())
.field("csslseie", &self.csslseie())
.field("lsirdyc", &self.lsirdyc())
.field("lserdyc", &self.lserdyc())
.field("hsirdyc", &self.hsirdyc())
.field("csslsec", &self.csslsec())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cir {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cir {{ lsirdyf: {=bool:?}, lserdyf: {=bool:?}, hsirdyf: {=bool:?}, csslsef: {=bool:?}, lsirdyie: {=bool:?}, lserdyie: {=bool:?}, hsirdyie: {=bool:?}, csslseie: {=bool:?}, lsirdyc: {=bool:?}, lserdyc: {=bool:?}, hsirdyc: {=bool:?}, csslsec: {=bool:?} }}" , self . lsirdyf () , self . lserdyf () , self . hsirdyf () , self . csslsef () , self . lsirdyie () , self . lserdyie () , self . hsirdyie () , self . csslseie () , self . lsirdyc () , self . lserdyc () , self . hsirdyc () , self . csslsec ())
}
}
#[doc = "CR"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cr(pub u32);
impl Cr {
#[doc = "HSI clock enable"]
#[must_use]
#[inline(always)]
pub const fn hsion(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "HSI clock enable"]
#[inline(always)]
pub const fn set_hsion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "HSI clock ready flag"]
#[must_use]
#[inline(always)]
pub const fn hsirdy(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "HSI clock ready flag"]
#[inline(always)]
pub const fn set_hsirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "HSI clock trimming"]
#[must_use]
#[inline(always)]
pub const fn hsiftrim(&self) -> u8 {
let val = (self.0 >> 2usize) & 0x0f;
val as u8
}
#[doc = "HSI clock trimming"]
#[inline(always)]
pub const fn set_hsiftrim(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 2usize)) | (((val as u32) & 0x0f) << 2usize);
}
#[doc = "HSI clock calibration"]
#[must_use]
#[inline(always)]
pub const fn hsictrim(&self) -> u8 {
let val = (self.0 >> 6usize) & 0x3f;
val as u8
}
#[doc = "HSI clock calibration"]
#[inline(always)]
pub const fn set_hsictrim(&mut self, val: u8) {
self.0 = (self.0 & !(0x3f << 6usize)) | (((val as u32) & 0x3f) << 6usize);
}
#[doc = "HSI prescaler"]
#[must_use]
#[inline(always)]
pub const fn hsi_pre(&self) -> u8 {
let val = (self.0 >> 12usize) & 0x07;
val as u8
}
#[doc = "HSI prescaler"]
#[inline(always)]
pub const fn set_hsi_pre(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 12usize)) | (((val as u32) & 0x07) << 12usize);
}
#[doc = "HSI frequency selection"]
#[must_use]
#[inline(always)]
pub const fn hsifresel(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "HSI frequency selection"]
#[inline(always)]
pub const fn set_hsifresel(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "HSI stabilize wait time"]
#[must_use]
#[inline(always)]
pub const fn hsiwt(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x3f;
val as u8
}
#[doc = "HSI stabilize wait time"]
#[inline(always)]
pub const fn set_hsiwt(&mut self, val: u8) {
self.0 = (self.0 & !(0x3f << 16usize)) | (((val as u32) & 0x3f) << 16usize);
}
}
impl Default for Cr {
#[inline(always)]
fn default() -> Cr {
Cr(0)
}
}
impl core::fmt::Debug for Cr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cr")
.field("hsion", &self.hsion())
.field("hsirdy", &self.hsirdy())
.field("hsiftrim", &self.hsiftrim())
.field("hsictrim", &self.hsictrim())
.field("hsi_pre", &self.hsi_pre())
.field("hsifresel", &self.hsifresel())
.field("hsiwt", &self.hsiwt())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cr {{ hsion: {=bool:?}, hsirdy: {=bool:?}, hsiftrim: {=u8:?}, hsictrim: {=u8:?}, hsi_pre: {=u8:?}, hsifresel: {=bool:?}, hsiwt: {=u8:?} }}" , self . hsion () , self . hsirdy () , self . hsiftrim () , self . hsictrim () , self . hsi_pre () , self . hsifresel () , self . hsiwt ())
}
}
#[doc = "CSR"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Csr(pub u32);
impl Csr {
#[doc = "LSI oscillator enable"]
#[must_use]
#[inline(always)]
pub const fn lsion(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "LSI oscillator enable"]
#[inline(always)]
pub const fn set_lsion(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "LSI oscillator ready"]
#[must_use]
#[inline(always)]
pub const fn lsirdy(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "LSI oscillator ready"]
#[inline(always)]
pub const fn set_lsirdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "LSI fine trimming"]
#[must_use]
#[inline(always)]
pub const fn lsi_fine(&self) -> u8 {
let val = (self.0 >> 2usize) & 0x0f;
val as u8
}
#[doc = "LSI fine trimming"]
#[inline(always)]
pub const fn set_lsi_fine(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 2usize)) | (((val as u32) & 0x0f) << 2usize);
}
#[doc = "LSI coarse trimming"]
#[must_use]
#[inline(always)]
pub const fn lsi_coarse(&self) -> u8 {
let val = (self.0 >> 6usize) & 0x1f;
val as u8
}
#[doc = "LSI coarse trimming"]
#[inline(always)]
pub const fn set_lsi_coarse(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 6usize)) | (((val as u32) & 0x1f) << 6usize);
}
#[doc = "Remove reset flag"]
#[must_use]
#[inline(always)]
pub const fn rmvf(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Remove reset flag"]
#[inline(always)]
pub const fn set_rmvf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "NRST pin reset flag"]
#[must_use]
#[inline(always)]
pub const fn pinrstf(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "NRST pin reset flag"]
#[inline(always)]
pub const fn set_pinrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
#[doc = "POR/PDR reset flag"]
#[must_use]
#[inline(always)]
pub const fn porrstf(&self) -> bool {
let val = (self.0 >> 27usize) & 0x01;
val != 0
}
#[doc = "POR/PDR reset flag"]
#[inline(always)]
pub const fn set_porrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
}
#[doc = "Software reset flag"]
#[must_use]
#[inline(always)]
pub const fn sftrstf(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Software reset flag"]
#[inline(always)]
pub const fn set_sftrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "Independent watchdog reset flag"]
#[must_use]
#[inline(always)]
pub const fn iwdgrstf(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "Independent watchdog reset flag"]
#[inline(always)]
pub const fn set_iwdgrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "Window watchdog reset flag"]
#[must_use]
#[inline(always)]
pub const fn wwdgrstf(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "Window watchdog reset flag"]
#[inline(always)]
pub const fn set_wwdgrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "BOR reset flag"]
#[must_use]
#[inline(always)]
pub const fn borrstf(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "BOR reset flag"]
#[inline(always)]
pub const fn set_borrstf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Csr {
#[inline(always)]
fn default() -> Csr {
Csr(0)
}
}
impl core::fmt::Debug for Csr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Csr")
.field("lsion", &self.lsion())
.field("lsirdy", &self.lsirdy())
.field("lsi_fine", &self.lsi_fine())
.field("lsi_coarse", &self.lsi_coarse())
.field("rmvf", &self.rmvf())
.field("pinrstf", &self.pinrstf())
.field("porrstf", &self.porrstf())
.field("sftrstf", &self.sftrstf())
.field("iwdgrstf", &self.iwdgrstf())
.field("wwdgrstf", &self.wwdgrstf())
.field("borrstf", &self.borrstf())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Csr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Csr {{ lsion: {=bool:?}, lsirdy: {=bool:?}, lsi_fine: {=u8:?}, lsi_coarse: {=u8:?}, rmvf: {=bool:?}, pinrstf: {=bool:?}, porrstf: {=bool:?}, sftrstf: {=bool:?}, iwdgrstf: {=bool:?}, wwdgrstf: {=bool:?}, borrstf: {=bool:?} }}" , self . lsion () , self . lsirdy () , self . lsi_fine () , self . lsi_coarse () , self . rmvf () , self . pinrstf () , self . porrstf () , self . sftrstf () , self . iwdgrstf () , self . wwdgrstf () , self . borrstf ())
}
}
#[doc = "CSSCR"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Csscr(pub u32);
impl Csscr {
#[doc = "CSSLSE count lower Limit"]
#[must_use]
#[inline(always)]
pub const fn csslse_lt(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x1f;
val as u8
}
#[doc = "CSSLSE count lower Limit"]
#[inline(always)]
pub const fn set_csslse_lt(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
}
#[doc = "CSSLSE count upper limit"]
#[must_use]
#[inline(always)]
pub const fn csslse_ut(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x1f;
val as u8
}
#[doc = "CSSLSE count upper limit"]
#[inline(always)]
pub const fn set_csslse_ut(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
}
#[doc = "Enable CSSLSE"]
#[must_use]
#[inline(always)]
pub const fn csslseon(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "Enable CSSLSE"]
#[inline(always)]
pub const fn set_csslseon(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
}
impl Default for Csscr {
#[inline(always)]
fn default() -> Csscr {
Csscr(0)
}
}
impl core::fmt::Debug for Csscr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Csscr")
.field("csslse_lt", &self.csslse_lt())
.field("csslse_ut", &self.csslse_ut())
.field("csslseon", &self.csslseon())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Csscr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Csscr {{ csslse_lt: {=u8:?}, csslse_ut: {=u8:?}, csslseon: {=bool:?} }}",
self.csslse_lt(),
self.csslse_ut(),
self.csslseon()
)
}
}
#[doc = "HSIKEY"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Hsikey(pub u32);
impl Hsikey {
#[doc = "HSI Key"]
#[must_use]
#[inline(always)]
pub const fn hsikey(&self) -> u32 {
let val = (self.0 >> 0usize) & 0xffff_ffff;
val as u32
}
#[doc = "HSI Key"]
#[inline(always)]
pub const fn set_hsikey(&mut self, val: u32) {
self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
}
}
impl Default for Hsikey {
#[inline(always)]
fn default() -> Hsikey {
Hsikey(0)
}
}
impl core::fmt::Debug for Hsikey {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Hsikey")
.field("hsikey", &self.hsikey())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Hsikey {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Hsikey {{ hsikey: {=u32:?} }}", self.hsikey())
}
}