#[doc = "CFGR"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cfgr(pub u32);
impl Cfgr {
#[doc = "Comparator power mode selection bit"]
#[must_use]
#[inline(always)]
pub const fn iop(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Comparator power mode selection bit"]
#[inline(always)]
pub const fn set_iop(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Built-in voltage divider circuit output range selection configuration bit"]
#[must_use]
#[inline(always)]
pub const fn os(&self) -> u8 {
let val = (self.0 >> 11usize) & 0x07;
val as u8
}
#[doc = "Built-in voltage divider circuit output range selection configuration bit"]
#[inline(always)]
pub const fn set_os(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 11usize)) | (((val as u32) & 0x07) << 11usize);
}
#[doc = "Built-in voltage divider circuit voltage selection configuration bit"]
#[must_use]
#[inline(always)]
pub const fn ps(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "Built-in voltage divider circuit voltage selection configuration bit"]
#[inline(always)]
pub const fn set_ps(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
#[doc = "Resistance partial voltage enable bit"]
#[must_use]
#[inline(always)]
pub const fn div_en(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "Resistance partial voltage enable bit"]
#[inline(always)]
pub const fn set_div_en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "Window function enable bit"]
#[must_use]
#[inline(always)]
pub const fn winen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Window function enable bit"]
#[inline(always)]
pub const fn set_winen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Window function output status bit"]
#[must_use]
#[inline(always)]
pub const fn winout(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "Window function output status bit"]
#[inline(always)]
pub const fn set_winout(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
}
impl Default for Cfgr {
#[inline(always)]
fn default() -> Cfgr {
Cfgr(0)
}
}
impl core::fmt::Debug for Cfgr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cfgr")
.field("iop", &self.iop())
.field("os", &self.os())
.field("ps", &self.ps())
.field("div_en", &self.div_en())
.field("winen", &self.winen())
.field("winout", &self.winout())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cfgr {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Cfgr {{ iop: {=bool:?}, os: {=u8:?}, ps: {=bool:?}, div_en: {=bool:?}, winen: {=bool:?}, winout: {=bool:?} }}" , self . iop () , self . os () , self . ps () , self . div_en () , self . winen () , self . winout ())
}
}
#[doc = "CSR1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Csr1(pub u32);
impl Csr1 {
#[doc = "Comparator 1 enable bit"]
#[must_use]
#[inline(always)]
pub const fn comp1en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Comparator 1 enable bit"]
#[inline(always)]
pub const fn set_comp1en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Comparator 1 hysteresis voltage selection bit"]
#[must_use]
#[inline(always)]
pub const fn comp1hys(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Comparator 1 hysteresis voltage selection bit"]
#[inline(always)]
pub const fn set_comp1hys(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Comparator 1 negative input connection configuration bit"]
#[must_use]
#[inline(always)]
pub const fn comp1innsel(&self) -> u8 {
let val = (self.0 >> 4usize) & 0x0f;
val as u8
}
#[doc = "Comparator 1 negative input connection configuration bit"]
#[inline(always)]
pub const fn set_comp1innsel(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
}
#[doc = "Comparator 1 positive input connection configuration bit"]
#[must_use]
#[inline(always)]
pub const fn comp1inpsel(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x07;
val as u8
}
#[doc = "Comparator 1 positive input connection configuration bit"]
#[inline(always)]
pub const fn set_comp1inpsel(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize);
}
#[doc = "Comparator 1 polarity selection bit"]
#[must_use]
#[inline(always)]
pub const fn comp1polarity(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "Comparator 1 polarity selection bit"]
#[inline(always)]
pub const fn set_comp1polarity(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "Comparator 1 dead time selection bit"]
#[must_use]
#[inline(always)]
pub const fn comp1dt_sel(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x03;
val as u8
}
#[doc = "Comparator 1 dead time selection bit"]
#[inline(always)]
pub const fn set_comp1dt_sel(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
}
#[doc = "Comparator 1 filter enable bit"]
#[must_use]
#[inline(always)]
pub const fn comp1flten(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "Comparator 1 filter enable bit"]
#[inline(always)]
pub const fn set_comp1flten(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "Comparator 1 filter clock selection bit"]
#[must_use]
#[inline(always)]
pub const fn comp1fltcksel(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "Comparator 1 filter clock selection bit"]
#[inline(always)]
pub const fn set_comp1fltcksel(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "Comparator 1 filter sampling clock division configuration bits"]
#[must_use]
#[inline(always)]
pub const fn comp1fltclkdiv(&self) -> u8 {
let val = (self.0 >> 22usize) & 0x07;
val as u8
}
#[doc = "Comparator 1 filter sampling clock division configuration bits"]
#[inline(always)]
pub const fn set_comp1fltclkdiv(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 22usize)) | (((val as u32) & 0x07) << 22usize);
}
#[doc = "Comparator 1 filter time configuration bits"]
#[must_use]
#[inline(always)]
pub const fn comp1flttime(&self) -> u8 {
let val = (self.0 >> 25usize) & 0x03;
val as u8
}
#[doc = "Comparator 1 filter time configuration bits"]
#[inline(always)]
pub const fn set_comp1flttime(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 25usize)) | (((val as u32) & 0x03) << 25usize);
}
#[doc = "Comparator 1 output status bit"]
#[must_use]
#[inline(always)]
pub const fn comp1value(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "Comparator 1 output status bit"]
#[inline(always)]
pub const fn set_comp1value(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "COMP1_CSR register lock bit"]
#[must_use]
#[inline(always)]
pub const fn comp1lock(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "COMP1_CSR register lock bit"]
#[inline(always)]
pub const fn set_comp1lock(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Csr1 {
#[inline(always)]
fn default() -> Csr1 {
Csr1(0)
}
}
impl core::fmt::Debug for Csr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Csr1")
.field("comp1en", &self.comp1en())
.field("comp1hys", &self.comp1hys())
.field("comp1innsel", &self.comp1innsel())
.field("comp1inpsel", &self.comp1inpsel())
.field("comp1polarity", &self.comp1polarity())
.field("comp1dt_sel", &self.comp1dt_sel())
.field("comp1flten", &self.comp1flten())
.field("comp1fltcksel", &self.comp1fltcksel())
.field("comp1fltclkdiv", &self.comp1fltclkdiv())
.field("comp1flttime", &self.comp1flttime())
.field("comp1value", &self.comp1value())
.field("comp1lock", &self.comp1lock())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Csr1 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Csr1 {{ comp1en: {=bool:?}, comp1hys: {=bool:?}, comp1innsel: {=u8:?}, comp1inpsel: {=u8:?}, comp1polarity: {=bool:?}, comp1dt_sel: {=u8:?}, comp1flten: {=bool:?}, comp1fltcksel: {=bool:?}, comp1fltclkdiv: {=u8:?}, comp1flttime: {=u8:?}, comp1value: {=bool:?}, comp1lock: {=bool:?} }}" , self . comp1en () , self . comp1hys () , self . comp1innsel () , self . comp1inpsel () , self . comp1polarity () , self . comp1dt_sel () , self . comp1flten () , self . comp1fltcksel () , self . comp1fltclkdiv () , self . comp1flttime () , self . comp1value () , self . comp1lock ())
}
}
#[doc = "CSR2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Csr2(pub u32);
impl Csr2 {
#[doc = "Comparator 2 enable bit"]
#[must_use]
#[inline(always)]
pub const fn comp2en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Comparator 2 enable bit"]
#[inline(always)]
pub const fn set_comp2en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Comparator 2 hysteresis voltage selector bit"]
#[must_use]
#[inline(always)]
pub const fn comp2hys(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Comparator 2 hysteresis voltage selector bit"]
#[inline(always)]
pub const fn set_comp2hys(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Comparator 2 negative input connection configuration bit"]
#[must_use]
#[inline(always)]
pub const fn comp2innsel(&self) -> u8 {
let val = (self.0 >> 4usize) & 0x0f;
val as u8
}
#[doc = "Comparator 2 negative input connection configuration bit"]
#[inline(always)]
pub const fn set_comp2innsel(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
}
#[doc = "Comparator 2 positive input connection configuration bit"]
#[must_use]
#[inline(always)]
pub const fn comp2inpsel(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x07;
val as u8
}
#[doc = "Comparator 2 positive input connection configuration bit"]
#[inline(always)]
pub const fn set_comp2inpsel(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize);
}
#[doc = "Comparator 2 polarity selection bit"]
#[must_use]
#[inline(always)]
pub const fn comp2polarity(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "Comparator 2 polarity selection bit"]
#[inline(always)]
pub const fn set_comp2polarity(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "Comparator 2 dead time selection bit"]
#[must_use]
#[inline(always)]
pub const fn comp2dt_sel(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x03;
val as u8
}
#[doc = "Comparator 2 dead time selection bit"]
#[inline(always)]
pub const fn set_comp2dt_sel(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
}
#[doc = "Comparator 2 filter enable bit"]
#[must_use]
#[inline(always)]
pub const fn comp2flten(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "Comparator 2 filter enable bit"]
#[inline(always)]
pub const fn set_comp2flten(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "Comparator 2 filter clock selection bit"]
#[must_use]
#[inline(always)]
pub const fn comp2fltcksel(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "Comparator 2 filter clock selection bit"]
#[inline(always)]
pub const fn set_comp2fltcksel(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "Comparator 2 filter sampling clock division configuration bits"]
#[must_use]
#[inline(always)]
pub const fn comp2fltclkdiv(&self) -> u8 {
let val = (self.0 >> 22usize) & 0x07;
val as u8
}
#[doc = "Comparator 2 filter sampling clock division configuration bits"]
#[inline(always)]
pub const fn set_comp2fltclkdiv(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 22usize)) | (((val as u32) & 0x07) << 22usize);
}
#[doc = "Comparator 2 filter time configuration bits"]
#[must_use]
#[inline(always)]
pub const fn comp2flttime(&self) -> u8 {
let val = (self.0 >> 25usize) & 0x03;
val as u8
}
#[doc = "Comparator 2 filter time configuration bits"]
#[inline(always)]
pub const fn set_comp2flttime(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 25usize)) | (((val as u32) & 0x03) << 25usize);
}
#[doc = "Comparator 2 output status bit"]
#[must_use]
#[inline(always)]
pub const fn comp2value(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "Comparator 2 output status bit"]
#[inline(always)]
pub const fn set_comp2value(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "COMP2_CSR register lock bit"]
#[must_use]
#[inline(always)]
pub const fn comp2lock(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "COMP2_CSR register lock bit"]
#[inline(always)]
pub const fn set_comp2lock(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for Csr2 {
#[inline(always)]
fn default() -> Csr2 {
Csr2(0)
}
}
impl core::fmt::Debug for Csr2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Csr2")
.field("comp2en", &self.comp2en())
.field("comp2hys", &self.comp2hys())
.field("comp2innsel", &self.comp2innsel())
.field("comp2inpsel", &self.comp2inpsel())
.field("comp2polarity", &self.comp2polarity())
.field("comp2dt_sel", &self.comp2dt_sel())
.field("comp2flten", &self.comp2flten())
.field("comp2fltcksel", &self.comp2fltcksel())
.field("comp2fltclkdiv", &self.comp2fltclkdiv())
.field("comp2flttime", &self.comp2flttime())
.field("comp2value", &self.comp2value())
.field("comp2lock", &self.comp2lock())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Csr2 {
fn format(&self, f: defmt::Formatter) {
defmt :: write ! (f , "Csr2 {{ comp2en: {=bool:?}, comp2hys: {=bool:?}, comp2innsel: {=u8:?}, comp2inpsel: {=u8:?}, comp2polarity: {=bool:?}, comp2dt_sel: {=u8:?}, comp2flten: {=bool:?}, comp2fltcksel: {=bool:?}, comp2fltclkdiv: {=u8:?}, comp2flttime: {=u8:?}, comp2value: {=bool:?}, comp2lock: {=bool:?} }}" , self . comp2en () , self . comp2hys () , self . comp2innsel () , self . comp2inpsel () , self . comp2polarity () , self . comp2dt_sel () , self . comp2flten () , self . comp2fltcksel () , self . comp2fltclkdiv () , self . comp2flttime () , self . comp2value () , self . comp2lock ())
}
}