; The sweep the instruction-stepped layer is compared against.
;
; Assembled to stepped.bin, which is committed, so the crate needs no assembler to build or test.
; Needs FantASM 1.7.5 or later: 1.7.1 emits `jp cc,<forward label>` and `call cc,<forward label>`
; without their opcode, silently, which shifts every byte after them.
; To regenerate after editing:
;
; fantasm -n -N -f bin -O $8000 tests/programs/stepped.asm tests/programs/stepped.bin
;
; Registers are seeded by the test rather than here. Data lives at $4000, which the test fills;
; code lives at $8000. Every instruction in this file must be implemented by the stepped layer —
; the test fails loudly on one that is not, rather than skipping it.
org $8000
; --- eight-bit loads ---------------------------------------------------------
nop
ld b,c
ld c,d
ld d,e
ld e,h
ld h,l
ld a,b
ld a,l
ld b,a
ld b,$5a
ld c,$a5
ld a,$3c
ld b,(hl)
ld c,(hl)
ld a,(hl)
ld (hl),b
ld (hl),c
ld (hl),a
ld (hl),$99
ld a,(bc)
ld a,(de)
ld (bc),a
ld (de),a
ld a,($4010)
ld ($4018),a
; --- the arithmetic group, against each register and through (hl) ------------
add a,b
adc a,c
sub d
sbc a,e
and h
xor l
or b
cp a
add a,(hl)
adc a,(hl)
sub (hl)
sbc a,(hl)
and (hl)
xor (hl)
or (hl)
cp (hl)
add a,$7f
adc a,$01
sub $80
sbc a,$ff
and $0f
xor $aa
or $55
cp $00
; --- the increments, which set every flag but the carry ----------------------
inc b
inc c
inc d
inc e
inc h
inc l
inc a
dec b
dec c
dec d
dec e
dec h
dec l
dec a
inc (hl)
dec (hl)
; and again with the carry set, to catch one that is not preserved
ld a,$ff
add a,$01
inc a
dec a
inc (hl)
; --- the sixteen-bit family --------------------------------------------------
ld bc,$1234
ld de,$4008
ld hl,$4020
ld sp,$4080
inc bc
inc de
inc hl
inc sp
dec bc
dec de
dec hl
dec sp
push bc
push de
push hl
push af
pop af
pop hl
pop de
pop bc
ex de,hl
ex af,af'
exx
ex de,hl
ex af,af'
exx
ld hl,($4024)
ld ($402c),hl
ld hl,$7fff
add hl,bc
add hl,de
add hl,hl
add hl,sp
ld hl,$0001
ld bc,$ffff
add hl,bc
ld sp,hl
; --- the accumulator rotates, which hold sign, zero and overflow -------------
ld a,$95
rlca
rrca
rla
rra
ld a,$ff
add a,$01
rlca
rrca
; --- the prefixed rotates and shifts, against registers and through (hl) -----
ld hl,$4020
rlc b
rrc c
rl d
rr e
sla h
sra l
sll a
srl a
rlc (hl)
rrc (hl)
rl (hl)
rr (hl)
sla (hl)
sra (hl)
sll (hl)
srl (hl)
; --- the tests, which read and never write -----------------------------------
bit 0,b
bit 3,c
bit 5,d
bit 7,e
bit 0,(hl)
bit 3,(hl)
bit 6,(hl)
bit 7,(hl)
; --- set and reset, both ways ------------------------------------------------
set 0,b
set 5,c
set 7,d
res 0,e
set 0,(hl)
set 5,(hl)
res 6,(hl)
res 3,(hl)
; --- a test through memory takes its undocumented flags from the address latch
; These make the two candidate rules disagree: the latch ends at $2800, whose high byte has both
; bits set, while the byte tested has neither. A case where they agree proves nothing.
ld a,($27ff)
ld hl,$4020
ld (hl),$00
bit 0,(hl)
bit 6,(hl)
; --- the accumulator flag instructions ---------------------------------------
ld a,$3f
daa
ld a,$9a
daa
cpl
scf
ccf
scf
cpl
ccf
; --- jumps -------------------------------------------------------------------
jp taken
taken:
ld a,$00
jp z,not_taken ; zero is clear, so this one falls through
not_taken:
or a ; sets zero
jp z,is_taken
ld a,$ff ; skipped
is_taken:
ld hl,indirect
jp (hl)
indirect:
ld hl,$4020
; relative, both ways, and a loop that runs to its end
jr forward
forward:
ld a,$01
or a ; clears zero
jr z,skipped ; not taken
skipped:
jr nz,also_taken
ld a,$ff ; skipped
also_taken:
ld b,$03
loop:
dec (hl)
djnz loop
ld b,$01
djnz done ; falls through, the counter reaches zero
done:
; --- calls, returns and restarts ---------------------------------------------
ld sp,$4080
call subroutine
ld a,$00
or a ; sets zero
call z,subroutine ; taken
call nz,subroutine ; not taken, and three cycles rather than five
ld a,$01
or a ; clears zero
call nz,subroutine ; taken
call z,subroutine ; not taken
call conditional_return
rst $08 ; the test puts a RET at each restart target
rst $20
jr past
subroutine:
ld a,$7f
ret
conditional_return:
ld a,$00
or a ; sets zero
ret z ; taken
ld a,$ff ; skipped
ret
past:
; --- the index prefixes ------------------------------------------------------
; The prefix stands in for HL right up until the instruction names (HL), at which point the
; register halves go back to being H and L — which is why LD H,(IX+d) loads the real H.
ld ix,$4030
ld iy,$4038
ld a,(ix+2)
ld b,(ix-1)
ld h,(ix+3) ; the real H, not IXh
ld (ix+4),a
ld (ix+5),c
ld (ix+6),$77
ld a,(iy+0)
ld (iy+1),a
add a,(ix+2)
sub (iy+3)
inc (ix+7)
dec (iy+2)
; the register halves, which the prefix does substitute for
ld a,ixh
ld a,ixl
ld ixh,$12
ld ixl,$34
inc ixh
dec ixl
ld b,iyh
ld iyl,b
; and the sixteen-bit forms
inc ix
dec iy
add ix,bc
add iy,de
push ix
pop ix
push iy
pop iy
ld ix,($4024)
ld ($4028),iy
ld sp,ix
ld sp,$4080
; --- the doubly-prefixed bit operations --------------------------------------
; The displacement sits between the second prefix and the opcode, the opcode is read as data
; rather than fetched, and the result lands in a register as well as in memory.
ld ix,$4030
ld iy,$4038
rlc (ix+1)
rr (ix+2)
sla (iy+1)
srl (iy+2)
bit 0,(ix+3)
bit 7,(iy+3)
set 4,(ix+4)
res 2,(iy+4)
defb $dd,$cb,$05,$00 ; rlc (ix+5) -> b, the undocumented register write-back
defb $dd,$cb,$06,$16 ; rl (ix+6) -> d
defb $fd,$cb,$07,$3d ; srl (iy+7) -> l
defb $dd,$cb,$08,$c7 ; set 0,(ix+8) -> a
; --- the exchange through the stack ------------------------------------------
ld sp,$4080
ld hl,$1234
ex (sp),hl
ex (sp),hl
ld ix,$5678
ex (sp),ix
ex (sp),ix
; --- the block transfers -----------------------------------------------------
; The counter comes down whether the instruction repeats or not; repeating adds a fifth cycle
; and a program counter that goes back two, so the same instruction is fetched again.
ld hl,$4000
ld de,$4030
ld bc,$0003
ldi
ldi
ldi ; the counter reaches zero, so overflow clears
ld hl,$400f
ld de,$403f
ld bc,$0002
ldd
ldd
ld hl,$4000
ld de,$4020
ld bc,$0004
ldir
ld hl,$400f
ld de,$402f
ld bc,$0003
lddr
; --- the whole eight-bit load grid -------------------------------------------
ld b,b ld b,c ld b,d ld b,e ld b,h ld b,l ld b,a
ld c,b ld c,c ld c,d ld c,e ld c,h ld c,l ld c,a
ld d,b ld d,c ld d,d ld d,e ld d,h ld d,l ld d,a
ld e,b ld e,c ld e,d ld e,e ld e,h ld e,l ld e,a
ld h,b ld h,c ld h,d ld h,e ld h,h ld h,l ld h,a
ld l,b ld l,c ld l,d ld l,e ld l,h ld l,l ld l,a
ld a,b ld a,c ld a,d ld a,e ld a,h ld a,l ld a,a
ld b,(hl) ld c,(hl) ld d,(hl) ld e,(hl) ld h,(hl) ld l,(hl) ld a,(hl)
ld (hl),b ld (hl),c ld (hl),d ld (hl),e ld (hl),h ld (hl),l ld (hl),a
; --- the whole arithmetic grid, against every register and through (hl) ------
add a,b add a,c add a,d add a,e add a,h add a,l add a,a add a,(hl)
adc a,b adc a,c adc a,d adc a,e adc a,h adc a,l adc a,a adc a,(hl)
sub b sub c sub d sub e sub h sub l sub a sub (hl)
sbc a,b sbc a,c sbc a,d sbc a,e sbc a,h sbc a,l sbc a,a sbc a,(hl)
and b and c and d and e and h and l and a and (hl)
xor b xor c xor d xor e xor h xor l xor a xor (hl)
or b or c or d or e or h or l or a or (hl)
cp b cp c cp d cp e cp h cp l cp a cp (hl)
; --- every increment and decrement -------------------------------------------
inc b inc c inc d inc e inc h inc l inc a inc (hl)
dec b dec c dec d dec e dec h dec l dec a dec (hl)
; --- every shift and rotate against every register ---------------------------
rlc b rlc c rlc d rlc e rlc h rlc l rlc a rlc (hl)
rrc b rrc c rrc d rrc e rrc h rrc l rrc a rrc (hl)
rl b rl c rl d rl e rl h rl l rl a rl (hl)
rr b rr c rr d rr e rr h rr l rr a rr (hl)
sla b sla c sla d sla e sla h sla l sla a sla (hl)
sra b sra c sra d sra e sra h sra l sra a sra (hl)
sll b sll c sll d sll e sll h sll l sll a sll (hl)
srl b srl c srl d srl e srl h srl l srl a srl (hl)
; --- every bit tested, set and reset, in a register and through (hl) ---------
bit 0,b bit 0,c bit 0,d bit 0,e bit 0,h bit 0,l bit 0,a bit 0,(hl)
bit 1,b bit 1,c bit 1,d bit 1,e bit 1,h bit 1,l bit 1,a bit 1,(hl)
bit 2,b bit 2,c bit 2,d bit 2,e bit 2,h bit 2,l bit 2,a bit 2,(hl)
bit 3,b bit 3,c bit 3,d bit 3,e bit 3,h bit 3,l bit 3,a bit 3,(hl)
bit 4,b bit 4,c bit 4,d bit 4,e bit 4,h bit 4,l bit 4,a bit 4,(hl)
bit 5,b bit 5,c bit 5,d bit 5,e bit 5,h bit 5,l bit 5,a bit 5,(hl)
bit 6,b bit 6,c bit 6,d bit 6,e bit 6,h bit 6,l bit 6,a bit 6,(hl)
bit 7,b bit 7,c bit 7,d bit 7,e bit 7,h bit 7,l bit 7,a bit 7,(hl)
res 0,b res 0,c res 0,d res 0,e res 0,h res 0,l res 0,a res 0,(hl)
res 1,b res 1,c res 1,d res 1,e res 1,h res 1,l res 1,a res 1,(hl)
res 2,b res 2,c res 2,d res 2,e res 2,h res 2,l res 2,a res 2,(hl)
res 3,b res 3,c res 3,d res 3,e res 3,h res 3,l res 3,a res 3,(hl)
res 4,b res 4,c res 4,d res 4,e res 4,h res 4,l res 4,a res 4,(hl)
res 5,b res 5,c res 5,d res 5,e res 5,h res 5,l res 5,a res 5,(hl)
res 6,b res 6,c res 6,d res 6,e res 6,h res 6,l res 6,a res 6,(hl)
res 7,b res 7,c res 7,d res 7,e res 7,h res 7,l res 7,a res 7,(hl)
set 0,b set 0,c set 0,d set 0,e set 0,h set 0,l set 0,a set 0,(hl)
set 1,b set 1,c set 1,d set 1,e set 1,h set 1,l set 1,a set 1,(hl)
set 2,b set 2,c set 2,d set 2,e set 2,h set 2,l set 2,a set 2,(hl)
set 3,b set 3,c set 3,d set 3,e set 3,h set 3,l set 3,a set 3,(hl)
set 4,b set 4,c set 4,d set 4,e set 4,h set 4,l set 4,a set 4,(hl)
set 5,b set 5,c set 5,d set 5,e set 5,h set 5,l set 5,a set 5,(hl)
set 6,b set 6,c set 6,d set 6,e set 6,h set 6,l set 6,a set 6,(hl)
set 7,b set 7,c set 7,d set 7,e set 7,h set 7,l set 7,a set 7,(hl)
; --- the operand loads the grid above does not reach ---------------------------
ld d,$11
ld e,$22
ld h,$40
ld l,$20
; --- every condition, on every conditional instruction -------------------------
; Each conditional jump targets the instruction after it, so the run continues whether the
; condition holds or not; each conditional return is handed an address pointing there too.
; The conditional calls share a stub that does nothing but return.
jp nz,ja0
ja0:
jp z,ja1
ja1:
jp nc,ja2
ja2:
jp c,ja3
ja3:
jp po,ja4
ja4:
jp pe,ja5
ja5:
jp p,ja6
ja6:
jp m,ja7
ja7:
call nz,cstub
call z,cstub
call nc,cstub
call c,cstub
call po,cstub
call pe,cstub
call p,cstub
call m,cstub
ld sp,$4080
ld hl,rr0
push hl
ret nz
rr0:
ld hl,rr1
push hl
ret z
rr1:
ld hl,rr2
push hl
ret nc
rr2:
ld hl,rr3
push hl
ret c
rr3:
ld hl,rr4
push hl
ret po
rr4:
ld hl,rr5
push hl
ret pe
rr5:
ld hl,rr6
push hl
ret p
rr6:
ld hl,rr7
push hl
ret m
rr7:
ld sp,$4080
jr nc,jc0
jc0:
jr c,jc1
jc1:
rst $00
rst $08
rst $10
rst $18
rst $20
rst $28
rst $30
rst $38
jr past_stub
cstub:
ret
past_stub:
; --- the block compares -------------------------------------------------------
ld hl,$4000
ld bc,$0004
ld a,$03
cpi ; matches the first byte
cpi
ld hl,$400f
ld bc,$0003
cpd
cpd
ld hl,$4000
ld bc,$0008
ld a,$ff ; matches nothing, so it runs the counter out
cpir
ld hl,$4000
ld bc,$0008
ld a,$1f ; matches part way, so it stops early
cpir
ld hl,$400f
ld bc,$0006
ld a,$ff
cpdr
; --- the port blocks ----------------------------------------------------------
ld hl,$4020
ld bc,$03fe
ini
ini
ld hl,$4030
ld bc,$02fe
ind
ld hl,$4000
ld bc,$03fe
outi
outi
ld hl,$400f
ld bc,$02fe
outd
ld hl,$4020
ld bc,$03fe
inir
ld hl,$4000
ld bc,$03fe
otir
ld hl,$400f
ld bc,$02fe
otdr
ld hl,$4030
ld bc,$02fe
indr
; --- the interrupt and refresh registers, whose parity carries the enable flag
ld a,$7f
ld i,a
ld a,$40
ld r,a
ld a,i
ld a,r
ld a,$00
ld i,a
ld a,i
; --- the interrupt modes, including the six slots that alias them ------------
im 0
im 1
im 2
defb $ed,$4e ; im 0
defb $ed,$66 ; im 0
defb $ed,$6e ; im 0
defb $ed,$76 ; im 1
defb $ed,$7e ; im 2
; --- the sixteen-bit loads through an address --------------------------------
ld ($4100),bc
ld ($4102),de
defb $ed,$63,$04,$41 ; the prefixed form, which the plain $22 would displace
ld ($4106),sp
ld bc,($4104)
ld de,($4100)
defb $ed,$6b,$06,$41 ; likewise against the plain $2a
ld sp,($4102)
ld sp,$4200
; --- the sixteen-bit adds that carry in, including the ones that land on zero
ld hl,$1234
ld bc,$1111
ld de,$2222
scf
adc hl,bc
adc hl,de
adc hl,hl
ld hl,$0000
ld bc,$0000
and a
sbc hl,bc
sbc hl,hl
ld hl,$8000
ld de,$0001
scf
sbc hl,de
ld hl,$4000
ld sp,$4000
and a
sbc hl,sp
adc hl,sp
; --- negation, and the seven slots that alias it -----------------------------
ld a,$01
neg
neg
defb $ed,$4c
defb $ed,$54
defb $ed,$5c
defb $ed,$64
defb $ed,$6c
defb $ed,$74
defb $ed,$7c
; --- the nibble rotates through memory ---------------------------------------
ld hl,$4000
ld a,$5a
rld
rld
rrd
rrd
; --- the interrupt returns, which take their target off the stack ------------
ld sp,$4200
ld hl,after_retn
push hl
retn
after_retn:
ld hl,after_reti
push hl
reti
after_reti:
ld hl,after_aliases
push hl
defb $ed,$55 ; retn
after_aliases:
ld hl,alias_5d
push hl
defb $ed,$5d
alias_5d:
ld hl,alias_65
push hl
defb $ed,$65
alias_65:
ld hl,alias_6d
push hl
defb $ed,$6d
alias_6d:
ld hl,alias_75
push hl
defb $ed,$75
alias_75:
ld hl,alias_7d
push hl
defb $ed,$7d
alias_7d:
; --- the port group addressed by the accumulator ------------------------------
ld a,$7f
in a,($fe)
out ($fe),a
ld a,$ff
in a,($00)
out ($00),a
; --- the port group addressed by bc, including the two slots with no register
ld bc,$05fe
in a,(c)
in b,(c)
in c,(c)
ld bc,$07fe
in d,(c)
in e,(c)
in h,(c)
in l,(c)
defb $ed,$70 ; in (c), which keeps nothing but the flags
ld bc,$06fe
out (c),a
out (c),b
out (c),c
ld bc,$09fe
out (c),d
out (c),e
out (c),h
out (c),l
defb $ed,$71 ; out (c),0
; --- the interrupt enable pair -----------------------------------------------
; HALT is not here: it would never let the sweep reach the end. It is covered on its own and by
; the acceptance tests, which are the only place it can be left.
di
ei
di
ei
ld a,i ; the parity flag reads the second flip-flop back
di
ld a,i
; --- the index-prefixed forms the plain instruction does not cover ------------
; Only the opcodes a prefix actually changes are here. The rest of the DD page runs the unprefixed
; instruction byte for byte, which the sweep already covers and the isolation harness measures.
ld ix,$4030
dec ixh
inc ixl
ld ixh,b
ld ixh,c
ld ixh,d
ld ixh,e
ld ixh,ixl
ld ixh,a
ld ixl,c
ld ixl,d
ld ixl,e
ld ixl,ixh
ld ixl,a
ld b,ixl
ld c,ixl
ld d,ixl
ld e,ixl
add a,ixl
adc a,ixl
sub ixl
sbc a,ixl
and ixl
or ixl
xor ixl
cp ixl
ld ix,$4030
add ix,ix
ld ix,$2000
add ix,sp
ld ix,$4030
ld c,(ix+1)
ld d,(ix+2)
ld e,(ix+3)
ld l,(ix+4)
ld (ix+5),b
ld (ix+6),d
ld (ix+7),e
ld (ix+8),h ; the real H, not IXh
ld (ix+9),l
adc a,(ix+1)
sbc a,(ix+2)
and (ix+3)
xor (ix+4)
or (ix+5)
cp (ix+6)
ld ix,through_ix
jp (ix)
through_ix:
ld ix,$4030
; --- the whole doubly-prefixed grid ------------------------------------------
; Every opcode behind DD CB, at a displacement that walks the scratch page. They are all a
; read-modify-write through (IX+d) with an undocumented copy into a register, so none of them can
; disturb the sweep's control flow and the grid can be written out in full.
defb $dd,$cb,$01,$00, $dd,$cb,$02,$01, $dd,$cb,$03,$02, $dd,$cb,$04,$03
defb $dd,$cb,$05,$04, $dd,$cb,$06,$05, $dd,$cb,$07,$06, $dd,$cb,$08,$07
defb $dd,$cb,$01,$08, $dd,$cb,$02,$09, $dd,$cb,$03,$0a, $dd,$cb,$04,$0b
defb $dd,$cb,$05,$0c, $dd,$cb,$06,$0d, $dd,$cb,$07,$0e, $dd,$cb,$08,$0f
defb $dd,$cb,$01,$10, $dd,$cb,$02,$11, $dd,$cb,$03,$12, $dd,$cb,$04,$13
defb $dd,$cb,$05,$14, $dd,$cb,$06,$15, $dd,$cb,$07,$16, $dd,$cb,$08,$17
defb $dd,$cb,$01,$18, $dd,$cb,$02,$19, $dd,$cb,$03,$1a, $dd,$cb,$04,$1b
defb $dd,$cb,$05,$1c, $dd,$cb,$06,$1d, $dd,$cb,$07,$1e, $dd,$cb,$08,$1f
defb $dd,$cb,$01,$20, $dd,$cb,$02,$21, $dd,$cb,$03,$22, $dd,$cb,$04,$23
defb $dd,$cb,$05,$24, $dd,$cb,$06,$25, $dd,$cb,$07,$26, $dd,$cb,$08,$27
defb $dd,$cb,$01,$28, $dd,$cb,$02,$29, $dd,$cb,$03,$2a, $dd,$cb,$04,$2b
defb $dd,$cb,$05,$2c, $dd,$cb,$06,$2d, $dd,$cb,$07,$2e, $dd,$cb,$08,$2f
defb $dd,$cb,$01,$30, $dd,$cb,$02,$31, $dd,$cb,$03,$32, $dd,$cb,$04,$33
defb $dd,$cb,$05,$34, $dd,$cb,$06,$35, $dd,$cb,$07,$36, $dd,$cb,$08,$37
defb $dd,$cb,$01,$38, $dd,$cb,$02,$39, $dd,$cb,$03,$3a, $dd,$cb,$04,$3b
defb $dd,$cb,$05,$3c, $dd,$cb,$06,$3d, $dd,$cb,$07,$3e, $dd,$cb,$08,$3f
defb $dd,$cb,$01,$40, $dd,$cb,$02,$41, $dd,$cb,$03,$42, $dd,$cb,$04,$43
defb $dd,$cb,$05,$44, $dd,$cb,$06,$45, $dd,$cb,$07,$46, $dd,$cb,$08,$47
defb $dd,$cb,$01,$48, $dd,$cb,$02,$49, $dd,$cb,$03,$4a, $dd,$cb,$04,$4b
defb $dd,$cb,$05,$4c, $dd,$cb,$06,$4d, $dd,$cb,$07,$4e, $dd,$cb,$08,$4f
defb $dd,$cb,$01,$50, $dd,$cb,$02,$51, $dd,$cb,$03,$52, $dd,$cb,$04,$53
defb $dd,$cb,$05,$54, $dd,$cb,$06,$55, $dd,$cb,$07,$56, $dd,$cb,$08,$57
defb $dd,$cb,$01,$58, $dd,$cb,$02,$59, $dd,$cb,$03,$5a, $dd,$cb,$04,$5b
defb $dd,$cb,$05,$5c, $dd,$cb,$06,$5d, $dd,$cb,$07,$5e, $dd,$cb,$08,$5f
defb $dd,$cb,$01,$60, $dd,$cb,$02,$61, $dd,$cb,$03,$62, $dd,$cb,$04,$63
defb $dd,$cb,$05,$64, $dd,$cb,$06,$65, $dd,$cb,$07,$66, $dd,$cb,$08,$67
defb $dd,$cb,$01,$68, $dd,$cb,$02,$69, $dd,$cb,$03,$6a, $dd,$cb,$04,$6b
defb $dd,$cb,$05,$6c, $dd,$cb,$06,$6d, $dd,$cb,$07,$6e, $dd,$cb,$08,$6f
defb $dd,$cb,$01,$70, $dd,$cb,$02,$71, $dd,$cb,$03,$72, $dd,$cb,$04,$73
defb $dd,$cb,$05,$74, $dd,$cb,$06,$75, $dd,$cb,$07,$76, $dd,$cb,$08,$77
defb $dd,$cb,$01,$78, $dd,$cb,$02,$79, $dd,$cb,$03,$7a, $dd,$cb,$04,$7b
defb $dd,$cb,$05,$7c, $dd,$cb,$06,$7d, $dd,$cb,$07,$7e, $dd,$cb,$08,$7f
defb $dd,$cb,$01,$80, $dd,$cb,$02,$81, $dd,$cb,$03,$82, $dd,$cb,$04,$83
defb $dd,$cb,$05,$84, $dd,$cb,$06,$85, $dd,$cb,$07,$86, $dd,$cb,$08,$87
defb $dd,$cb,$01,$88, $dd,$cb,$02,$89, $dd,$cb,$03,$8a, $dd,$cb,$04,$8b
defb $dd,$cb,$05,$8c, $dd,$cb,$06,$8d, $dd,$cb,$07,$8e, $dd,$cb,$08,$8f
defb $dd,$cb,$01,$90, $dd,$cb,$02,$91, $dd,$cb,$03,$92, $dd,$cb,$04,$93
defb $dd,$cb,$05,$94, $dd,$cb,$06,$95, $dd,$cb,$07,$96, $dd,$cb,$08,$97
defb $dd,$cb,$01,$98, $dd,$cb,$02,$99, $dd,$cb,$03,$9a, $dd,$cb,$04,$9b
defb $dd,$cb,$05,$9c, $dd,$cb,$06,$9d, $dd,$cb,$07,$9e, $dd,$cb,$08,$9f
defb $dd,$cb,$01,$a0, $dd,$cb,$02,$a1, $dd,$cb,$03,$a2, $dd,$cb,$04,$a3
defb $dd,$cb,$05,$a4, $dd,$cb,$06,$a5, $dd,$cb,$07,$a6, $dd,$cb,$08,$a7
defb $dd,$cb,$01,$a8, $dd,$cb,$02,$a9, $dd,$cb,$03,$aa, $dd,$cb,$04,$ab
defb $dd,$cb,$05,$ac, $dd,$cb,$06,$ad, $dd,$cb,$07,$ae, $dd,$cb,$08,$af
defb $dd,$cb,$01,$b0, $dd,$cb,$02,$b1, $dd,$cb,$03,$b2, $dd,$cb,$04,$b3
defb $dd,$cb,$05,$b4, $dd,$cb,$06,$b5, $dd,$cb,$07,$b6, $dd,$cb,$08,$b7
defb $dd,$cb,$01,$b8, $dd,$cb,$02,$b9, $dd,$cb,$03,$ba, $dd,$cb,$04,$bb
defb $dd,$cb,$05,$bc, $dd,$cb,$06,$bd, $dd,$cb,$07,$be, $dd,$cb,$08,$bf
defb $dd,$cb,$01,$c0, $dd,$cb,$02,$c1, $dd,$cb,$03,$c2, $dd,$cb,$04,$c3
defb $dd,$cb,$05,$c4, $dd,$cb,$06,$c5, $dd,$cb,$07,$c6, $dd,$cb,$08,$c7
defb $dd,$cb,$01,$c8, $dd,$cb,$02,$c9, $dd,$cb,$03,$ca, $dd,$cb,$04,$cb
defb $dd,$cb,$05,$cc, $dd,$cb,$06,$cd, $dd,$cb,$07,$ce, $dd,$cb,$08,$cf
defb $dd,$cb,$01,$d0, $dd,$cb,$02,$d1, $dd,$cb,$03,$d2, $dd,$cb,$04,$d3
defb $dd,$cb,$05,$d4, $dd,$cb,$06,$d5, $dd,$cb,$07,$d6, $dd,$cb,$08,$d7
defb $dd,$cb,$01,$d8, $dd,$cb,$02,$d9, $dd,$cb,$03,$da, $dd,$cb,$04,$db
defb $dd,$cb,$05,$dc, $dd,$cb,$06,$dd, $dd,$cb,$07,$de, $dd,$cb,$08,$df
defb $dd,$cb,$01,$e0, $dd,$cb,$02,$e1, $dd,$cb,$03,$e2, $dd,$cb,$04,$e3
defb $dd,$cb,$05,$e4, $dd,$cb,$06,$e5, $dd,$cb,$07,$e6, $dd,$cb,$08,$e7
defb $dd,$cb,$01,$e8, $dd,$cb,$02,$e9, $dd,$cb,$03,$ea, $dd,$cb,$04,$eb
defb $dd,$cb,$05,$ec, $dd,$cb,$06,$ed, $dd,$cb,$07,$ee, $dd,$cb,$08,$ef
defb $dd,$cb,$01,$f0, $dd,$cb,$02,$f1, $dd,$cb,$03,$f2, $dd,$cb,$04,$f3
defb $dd,$cb,$05,$f4, $dd,$cb,$06,$f5, $dd,$cb,$07,$f6, $dd,$cb,$08,$f7
defb $dd,$cb,$01,$f8, $dd,$cb,$02,$f9, $dd,$cb,$03,$fa, $dd,$cb,$04,$fb
defb $dd,$cb,$05,$fc, $dd,$cb,$06,$fd, $dd,$cb,$07,$fe, $dd,$cb,$08,$ff
; --- the extended set --------------------------------------------------------
; Runs with the extended instructions enabled, so the rest of the sweep does too. Nothing before
; here decodes differently either way.
ld sp,$4200
defb $ed,$00 ; the page's no-operation, which most of it is
ld de,$1234
mul d,e
ld a,$5a
swapnib
mirror
nextreg 7,2
nextreg 7,a
ld hl,$4000
ld bc,$0010
ld de,$0020
add hl,a
add de,a
add bc,a
add hl,$1234
add de,$0100
add bc,$0001
test $55
test $00
ld b,$03
ld de,$1234
bsla de,b
bsra de,b
bsrl de,b
bsrf de,b
brlc de,b
ld hl,$4000
pixeldn
ld de,$0805
pixelad
setae
push $4002
pop hl
ld bc,$00fe
ld hl,$4000
outinb
; the copies, which skip the write when the byte matches the accumulator
ld a,$00
ld hl,$4000
ld de,$4020
ld bc,$0003
ldix
lddx
ld hl,$4000
ld de,$4020
ld bc,$0002
ldirx
ld hl,$400f
ld de,$4030
ld bc,$0002
lddrx
ld hl,$4000
ld de,$4020
ldws
ld hl,$4000
ld de,$4020
ld bc,$0002
defb $ed,$b6 ; ldirscale, which the assembler emits nothing for
ld hl,$4000
ld de,$4020
ld bc,$0002
ldpirx
; last, because where this one lands is decided by whatever answers the port
ld sp,$4200
ld bc,$00fe
jp (c)
program_end: