# Project History
### [1.0.0] - 2026-08-18
First public release — a Z80 and Z80N CPU core, stepped one clock edge at a time.
#### Added
- `tick()` advances one clock edge, half a T-state, so the bus transitions a real Z80 presents are
each visible on their own tick: the address becoming valid, the control lines asserting, the data
bus being latched.
- `step()` runs to the next instruction boundary and returns the T-states taken. It is the
optimised path, and the one a machine should run on — across the benchmark workloads it costs
roughly ten to thirty times less than `tick()`.
- The `Host` trait carries memory, ports and the signals reaching the CPU. Each access is given its
position within its machine cycle in T-states, which is what lets a host apply contention or wait
states at the moment the hardware would.
- Z80 and Z80N, switchable at run time. With Z80N off the extended `ED` opcodes decode as the
two-cycle no-operation a real Z80 gives them, so one instance models either part.
- All thirty Z80N instructions. Those with effects outside the processor surface as command tokens
carrying their operand, leaving the core free of any particular machine's memory-management or
register-file details.
- Save and restore at any half-T-state, with an optional `serde` feature on the state types.
- `no_std`, no allocator, and `#![forbid(unsafe_code)]`.
Checked against four oracles: 1350 of 1356 published test vectors, a T-state-for-T-state comparison
with a simulation of the T80/T80N FPGA core it is derived from, 185 seeded final-state probes,
and a save/restore round-trip. The six vector exceptions are named in the harness with their reasons.