---
source: hereticus-cli/tests/cli.rs
info:
program: hereticus
args:
- "--color"
- never
- "--diff-all"
- fixtures/build/O2/firmware.o
- fixtures/build/O2/firmware_v2.o
---
success: true
exit_code: 0
----- stdout -----
dispatch
- cmp r1, 0x2
- beq $+0x48
- cmp r1, 0x1
- beq $+0x28
+ push {r4, lr}
+ sub sp, sp, 0x8
mvn r2, 0x0
- cmp r1, 0x0
- bne $+0x2c
+ cmp r1, 0x3
+ bhi $+0x100
+ adr r3, pc, 0x4
+ ldr r1, [r3, r1, lsl 2]
+ add pc, r3, r1
+ andeq r0, r0, r0, lsl r0
+ andeq r0, r0, r0, asr 1
+ andeq r0, r0, r4, lsr 0
+ andeq r0, r0, ip, lsr 1
ldrh r0, [r0, 0x2]
mov r2, 0x0
- cmp r0, 0x400
+ cmp r0, 0x200
mvnhi r2, 0x0
- mov r0, r2
- bx lr
- ldrh r0, [r0]
- mov r1, 0x5a5a
- subs r2, r0, r1
- mvnne r2, 0x0
- mov r0, r2
- bx lr
- push {r4, lr}
- sub sp, sp, 0x4
+ b $+0xd0
ldrh lr, [r0, 0x2]
cmp lr, 0x0
beq $+0xc0
mov ip, 0x0
mov r2, 0x0
cmp lr, 0x4
blo $+0x50
bic ip, lr, 0x3
vmov.i32 q8, 0x0
add r2, r0, 0x4
- mov r3, sp
+ add r3, sp, 0x4
mov r1, ip
ldr r4, [r2], 0x4
subs r1, r1, 0x4
- str r4, [sp]
+ str r4, [sp, 0x4]
vld1.32 {d18[0]}, [r3:32]
vmovl.u8 q9, d18
vmovl.u16 q9, d18
vadd.i32 q8, q8, q9
bne $-0x1c
vadd.i32 d16, d16, d17
cmp ip, lr
vmov.32 r1, d16[1]
vmov.32 r2, d16[0]
add r2, r2, r1
beq $+0x68
add r0, ip, r0
sub r1, lr, ip
add r0, r0, 0x4
ldrb r3, [r0], 0x1
subs r1, r1, 0x1
add r2, r2, r3
bne $-0xc
b $+0x48
- mov r2, 0x0
- add sp, sp, 0x4
+ ldrh r1, [r0, 0x2]
+ add r0, r0, 0x4
+ add sp, sp, 0x8
pop {r4, lr}
+ b $+0x0
+ ldrh r1, [r0]
+ mov r3, 0x5a5a
+ cmp r1, r3
+ bne $+0x24
+ ldrh r1, [r0, 0x2]
+ add r0, r0, 0x4
+ bl $+0x0
+ mov r2, r0
+ cmp r0, 0x0
+ mvnne r2, 0x1
+ b $+0x8
+ mov r2, 0x0
mov r0, r2
- bx lr
+ add sp, sp, 0x8
+ pop {r4, pc}
check_header
- ldrh r0, [r0]
- mov r1, 0x5a5a
- subs r0, r0, r1
- mvnne r0, 0x0
+ ldrh r1, [r0]
+ mov r2, r0
+ mov r3, 0x5a5a
+ mvn r0, 0x0
+ cmp r1, r3
+ bxne lr
+ push {fp, lr}
+ ldrh r1, [r2, 0x2]
+ add r0, r2, 0x4
+ bl $+0x0
+ cmp r0, 0x0
+ mvnne r0, 0x1
+ pop {fp, lr}
bx lr
handle
- push {r4, lr}
+ push {r4, r5, r6, lr}
sub sp, sp, 0x8
- ldrh r2, [r0]
- mov r1, 0x1
- mov r3, 0x5a5a
- cmp r2, r3
+ mov r4, r0
+ ldrh r0, [r0]
+ mov r6, 0x1
+ mov r1, 0x5a5a
+ cmp r0, r1
bne $+0x2c
- ldrh lr, [r0, 0x2]
- mov r1, 0x2
- cmp lr, 0x400
+ add r5, r4, 0x4
+ ldrh r1, [r4, 0x2]
+ mov r0, r5
+ bl $+0x0
+ cmp r0, 0x0
+ bne $+0x14
+ ldrh r1, [r4, 0x2]
+ mov r6, 0x2
+ cmp r1, 0x200
bls $+0x18
mov r0, r6
bl $+0x0
- mvn r1, 0x0
- mov r0, r1
+ mvn r0, 0x0
add sp, sp, 0x8
- pop {r4, pc}
- cmp lr, 0x0
+ pop {r4, r5, r6, pc}
+ cmp r1, 0x0
beq $+0x7c
- mov ip, 0x0
- mov r1, 0x0
- cmp lr, 0x4
+ mov r2, 0x0
+ mov r0, 0x0
+ cmp r1, 0x4
blo $+0x4c
- mov r2, 0x7fc
- and ip, lr, r2
+ and r2, r1, 0x3fc
vmov.i32 q8, 0x0
- add r1, r0, 0x4
- add r3, sp, 0x4
- mov r2, ip
- ldr r4, [r1], 0x4
- subs r2, r2, 0x4
- str r4, [sp, 0x4]
- vld1.32 {d18[0]}, [r3:32]
+ add r0, sp, 0x4
+ mov r3, r2
+ ldr r6, [r5], 0x4
+ subs r3, r3, 0x4
+ str r6, [sp, 0x4]
+ vld1.32 {d18[0]}, [r0:32]
vmovl.u8 q9, d18
vmovl.u16 q9, d18
vadd.i32 q8, q8, q9
bne $-0x1c
vadd.i32 d16, d16, d17
- cmp ip, lr
- vmov.32 r1, d16[1]
- vmov.32 r2, d16[0]
- add r1, r2, r1
+ cmp r2, r1
+ vmov.32 r0, d16[1]
+ vmov.32 r3, d16[0]
+ add r0, r3, r0
beq $-0x64
- add r0, ip, r0
- sub r2, lr, ip
- add r0, r0, 0x4
- ldrb r3, [r0], 0x1
- subs r2, r2, 0x1
- add r1, r1, r3
+ sub r1, r1, r2
+ add r2, r2, r4
+ add r2, r2, 0x4
+ ldrb r3, [r2], 0x1
+ subs r1, r1, 0x1
+ add r0, r0, r3
bne $-0xc
b $-0x84
- mov r1, 0x0
- b $-0x98
+ mov r0, 0x0
+ add sp, sp, 0x8
+ pop {r4, r5, r6, pc}
----- stderr -----