#![no_std]
#[repr(C)]
#[derive(Copy, Clone, Debug, Default, Eq, Hash, Ord, PartialEq, PartialOrd)]
pub struct __BindgenBitfieldUnit<Storage> {
storage: Storage,
}
impl<Storage> __BindgenBitfieldUnit<Storage> {
#[inline]
pub const fn new(storage: Storage) -> Self {
Self { storage }
}
}
impl<Storage> __BindgenBitfieldUnit<Storage>
where
Storage: AsRef<[u8]> + AsMut<[u8]>,
{
#[inline]
fn extract_bit(byte: u8, index: usize) -> bool {
let bit_index = if cfg!(target_endian = "big") {
7 - (index % 8)
} else {
index % 8
};
let mask = 1 << bit_index;
byte & mask == mask
}
#[inline]
pub fn get_bit(&self, index: usize) -> bool {
debug_assert!(index / 8 < self.storage.as_ref().len());
let byte_index = index / 8;
let byte = self.storage.as_ref()[byte_index];
Self::extract_bit(byte, index)
}
#[inline]
pub unsafe fn raw_get_bit(this: *const Self, index: usize) -> bool {
debug_assert!(index / 8 < core::mem::size_of::<Storage>());
let byte_index = index / 8;
let byte = unsafe {
*(core::ptr::addr_of!((*this).storage) as *const u8).offset(byte_index as isize)
};
Self::extract_bit(byte, index)
}
#[inline]
fn change_bit(byte: u8, index: usize, val: bool) -> u8 {
let bit_index = if cfg!(target_endian = "big") {
7 - (index % 8)
} else {
index % 8
};
let mask = 1 << bit_index;
if val {
byte | mask
} else {
byte & !mask
}
}
#[inline]
pub fn set_bit(&mut self, index: usize, val: bool) {
debug_assert!(index / 8 < self.storage.as_ref().len());
let byte_index = index / 8;
let byte = &mut self.storage.as_mut()[byte_index];
*byte = Self::change_bit(*byte, index, val);
}
#[inline]
pub unsafe fn raw_set_bit(this: *mut Self, index: usize, val: bool) {
debug_assert!(index / 8 < core::mem::size_of::<Storage>());
let byte_index = index / 8;
let byte = unsafe {
(core::ptr::addr_of_mut!((*this).storage) as *mut u8).offset(byte_index as isize)
};
unsafe { *byte = Self::change_bit(*byte, index, val) };
}
#[inline]
pub fn get(&self, bit_offset: usize, bit_width: u8) -> u64 {
debug_assert!(bit_width <= 64);
debug_assert!(bit_offset / 8 < self.storage.as_ref().len());
debug_assert!((bit_offset + (bit_width as usize)) / 8 <= self.storage.as_ref().len());
let mut val = 0;
for i in 0..(bit_width as usize) {
if self.get_bit(i + bit_offset) {
let index = if cfg!(target_endian = "big") {
bit_width as usize - 1 - i
} else {
i
};
val |= 1 << index;
}
}
val
}
#[inline]
pub unsafe fn raw_get(this: *const Self, bit_offset: usize, bit_width: u8) -> u64 {
debug_assert!(bit_width <= 64);
debug_assert!(bit_offset / 8 < core::mem::size_of::<Storage>());
debug_assert!((bit_offset + (bit_width as usize)) / 8 <= core::mem::size_of::<Storage>());
let mut val = 0;
for i in 0..(bit_width as usize) {
if unsafe { Self::raw_get_bit(this, i + bit_offset) } {
let index = if cfg!(target_endian = "big") {
bit_width as usize - 1 - i
} else {
i
};
val |= 1 << index;
}
}
val
}
#[inline]
pub fn set(&mut self, bit_offset: usize, bit_width: u8, val: u64) {
debug_assert!(bit_width <= 64);
debug_assert!(bit_offset / 8 < self.storage.as_ref().len());
debug_assert!((bit_offset + (bit_width as usize)) / 8 <= self.storage.as_ref().len());
for i in 0..(bit_width as usize) {
let mask = 1 << i;
let val_bit_is_set = val & mask == mask;
let index = if cfg!(target_endian = "big") {
bit_width as usize - 1 - i
} else {
i
};
self.set_bit(index + bit_offset, val_bit_is_set);
}
}
#[inline]
pub unsafe fn raw_set(this: *mut Self, bit_offset: usize, bit_width: u8, val: u64) {
debug_assert!(bit_width <= 64);
debug_assert!(bit_offset / 8 < core::mem::size_of::<Storage>());
debug_assert!((bit_offset + (bit_width as usize)) / 8 <= core::mem::size_of::<Storage>());
for i in 0..(bit_width as usize) {
let mask = 1 << i;
let val_bit_is_set = val & mask == mask;
let index = if cfg!(target_endian = "big") {
bit_width as usize - 1 - i
} else {
i
};
unsafe { Self::raw_set_bit(this, index + bit_offset, val_bit_is_set) };
}
}
}
pub const __PERIPH_BIT_BAND_BASE: u32 = 1107296256;
pub const __PERIPH_BASE: u32 = 1073741824;
pub const LL_OK: u32 = 0;
pub const LL_ERR: i32 = -1;
pub const LL_ERR_UNINIT: i32 = -2;
pub const LL_ERR_INVD_PARAM: i32 = -3;
pub const LL_ERR_INVD_MD: i32 = -4;
pub const LL_ERR_NOT_RDY: i32 = -5;
pub const LL_ERR_BUSY: i32 = -6;
pub const LL_ERR_ADDR_ALIGN: i32 = -7;
pub const LL_ERR_TIMEOUT: i32 = -8;
pub const LL_ERR_BUF_EMPTY: i32 = -9;
pub const LL_ERR_BUF_FULL: i32 = -10;
pub const DDL_ON: u32 = 1;
pub const DDL_OFF: u32 = 0;
pub const BIT_MASK_00: u32 = 1;
pub const BIT_MASK_01: u32 = 2;
pub const BIT_MASK_02: u32 = 4;
pub const BIT_MASK_03: u32 = 8;
pub const BIT_MASK_04: u32 = 16;
pub const BIT_MASK_05: u32 = 32;
pub const BIT_MASK_06: u32 = 64;
pub const BIT_MASK_07: u32 = 128;
pub const BIT_MASK_08: u32 = 256;
pub const BIT_MASK_09: u32 = 512;
pub const BIT_MASK_10: u32 = 1024;
pub const BIT_MASK_11: u32 = 2048;
pub const BIT_MASK_12: u32 = 4096;
pub const BIT_MASK_13: u32 = 8192;
pub const BIT_MASK_14: u32 = 16384;
pub const BIT_MASK_15: u32 = 32768;
pub const BIT_MASK_16: u32 = 65536;
pub const BIT_MASK_17: u32 = 131072;
pub const BIT_MASK_18: u32 = 262144;
pub const BIT_MASK_19: u32 = 524288;
pub const BIT_MASK_20: u32 = 1048576;
pub const BIT_MASK_21: u32 = 2097152;
pub const BIT_MASK_22: u32 = 4194304;
pub const BIT_MASK_23: u32 = 8388608;
pub const BIT_MASK_24: u32 = 16777216;
pub const BIT_MASK_25: u32 = 33554432;
pub const BIT_MASK_26: u32 = 67108864;
pub const BIT_MASK_27: u32 = 134217728;
pub const BIT_MASK_28: u32 = 268435456;
pub const BIT_MASK_29: u32 = 536870912;
pub const BIT_MASK_30: u32 = 1073741824;
pub const BIT_MASK_31: u32 = 2147483648;
pub const USB_MAX_TX_FIFOS: u32 = 6;
pub const USB_MAX_CH_NUM: u32 = 12;
pub const USB_MAX_EP_NUM: u32 = 6;
pub const USBFS_CORE_ID: u32 = 0;
pub const USBHS_CORE_ID: u32 = 1;
pub const USBHS_PHY_EMBED: u32 = 0;
pub const USBHS_PHY_EXT: u32 = 1;
pub const USB_MAX_EP0_SIZE: u32 = 64;
pub const DEVICE_MODE: u32 = 0;
pub const HOST_MODE: u32 = 1;
pub const DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: u32 = 0;
pub const DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: u32 = 2;
pub const DSTS_ENUMSPD_LS_PHY_6MHZ: u32 = 4;
pub const DSTS_ENUMSPD_FS_PHY_48MHZ: u32 = 6;
pub const EP_TYPE_CTRL: u32 = 0;
pub const EP_TYPE_ISOC: u32 = 1;
pub const EP_TYPE_BULK: u32 = 2;
pub const EP_TYPE_INTR: u32 = 3;
pub const EP_TYPE_MSK: u32 = 3;
pub const PRTSPD_FULL_SPEED: u32 = 1;
pub const PRTSPD_LOW_SPEED: u32 = 2;
pub const HCFG_30_60_MHZ: u32 = 0;
pub const HCFG_48_MHZ: u32 = 1;
pub const HCFG_6_MHZ: u32 = 2;
pub const USB_EP_TX_DIS: u32 = 0;
pub const USB_EP_TX_STALL: u32 = 16;
pub const USB_EP_TX_NAK: u32 = 32;
pub const USB_EP_TX_VALID: u32 = 48;
pub const USB_EP_RX_DIS: u32 = 0;
pub const USB_EP_RX_STALL: u32 = 4096;
pub const USB_EP_RX_NAK: u32 = 8192;
pub const USB_EP_RX_VALID: u32 = 12288;
pub const USB_OK: u32 = 0;
pub const USB_ERROR: u32 = 1;
pub const USB_FRAME_INTERVAL_80: u32 = 0;
pub const USB_FRAME_INTERVAL_85: u32 = 2048;
pub const USB_FRAME_INTERVAL_90: u32 = 4096;
pub const USB_FRAME_INTERVAL_95: u32 = 6144;
pub const LL_PERIPH_EFM: u32 = 1;
pub const LL_PERIPH_FCG: u32 = 2;
pub const LL_PERIPH_GPIO: u32 = 4;
pub const LL_PERIPH_INTC: u32 = 8;
pub const LL_PERIPH_LVD: u32 = 16;
pub const LL_PERIPH_MPU: u32 = 32;
pub const LL_PERIPH_PWC_CLK_RMU: u32 = 64;
pub const LL_PERIPH_SRAM: u32 = 128;
pub const LL_PERIPH_ALL: u32 = 255;
pub const HC32_DDL_REV_MAIN: u32 = 3;
pub const HC32_DDL_REV_SUB1: u32 = 3;
pub const HC32_DDL_REV_SUB2: u32 = 0;
pub const HC32_DDL_REV_PATCH: u32 = 0;
pub const HC32_DDL_REV: u32 = 50528256;
pub const MAX_DATA_LENGTH: u32 = 512;
pub const ADC_SEQ_A: u32 = 0;
pub const ADC_SEQ_B: u32 = 1;
pub const ADC_CH0: u32 = 0;
pub const ADC_CH1: u32 = 1;
pub const ADC_CH2: u32 = 2;
pub const ADC_CH3: u32 = 3;
pub const ADC_CH4: u32 = 4;
pub const ADC_CH5: u32 = 5;
pub const ADC_CH6: u32 = 6;
pub const ADC_CH7: u32 = 7;
pub const ADC_CH8: u32 = 8;
pub const ADC_CH9: u32 = 9;
pub const ADC_CH10: u32 = 10;
pub const ADC_CH11: u32 = 11;
pub const ADC_CH12: u32 = 12;
pub const ADC_CH13: u32 = 13;
pub const ADC_CH14: u32 = 14;
pub const ADC_CH15: u32 = 15;
pub const ADC_CH16: u32 = 16;
pub const ADC1_EXT_CH: u32 = 16;
pub const ADC2_EXT_CH: u32 = 8;
pub const ADC_MX_CH0: u32 = 1;
pub const ADC_MX_CH1: u32 = 2;
pub const ADC_MX_CH2: u32 = 4;
pub const ADC_MX_CH3: u32 = 8;
pub const ADC_MX_CH4: u32 = 16;
pub const ADC_MX_CH5: u32 = 32;
pub const ADC_MX_CH6: u32 = 64;
pub const ADC_MX_CH7: u32 = 128;
pub const ADC_MX_CH8: u32 = 256;
pub const ADC_MX_CH9: u32 = 512;
pub const ADC_MX_CH10: u32 = 1024;
pub const ADC_MX_CH11: u32 = 2048;
pub const ADC_MX_CH12: u32 = 4096;
pub const ADC_MX_CH13: u32 = 8192;
pub const ADC_MX_CH14: u32 = 16384;
pub const ADC_MX_CH15: u32 = 32768;
pub const ADC_MX_CH16: u32 = 65536;
pub const ADC1_MX_CH_ALL: u32 = 65535;
pub const ADC2_MX_CH_ALL: u32 = 511;
pub const ADC_MD_SEQA_SINGLESHOT: u32 = 0;
pub const ADC_MD_SEQA_CONT: u32 = 1;
pub const ADC_MD_SEQA_SEQB_SINGLESHOT: u32 = 2;
pub const ADC_MD_SEQA_CONT_SEQB_SINGLESHOT: u32 = 3;
pub const ADC_RESOLUTION_12BIT: u32 = 0;
pub const ADC_RESOLUTION_10BIT: u32 = 16;
pub const ADC_RESOLUTION_8BIT: u32 = 32;
pub const ADC_DATAALIGN_RIGHT: u32 = 0;
pub const ADC_DATAALIGN_LEFT: u32 = 128;
pub const ADC_AVG_CNT2: u32 = 0;
pub const ADC_AVG_CNT4: u32 = 256;
pub const ADC_AVG_CNT8: u32 = 512;
pub const ADC_AVG_CNT16: u32 = 768;
pub const ADC_AVG_CNT32: u32 = 1024;
pub const ADC_AVG_CNT64: u32 = 1280;
pub const ADC_AVG_CNT128: u32 = 1536;
pub const ADC_AVG_CNT256: u32 = 1792;
pub const ADC_SEQA_RESUME_SCAN_CONT: u32 = 0;
pub const ADC_SEQA_RESUME_SCAN_RESTART: u32 = 4;
pub const ADC_HARDTRIG_ADTRG_PIN: u32 = 0;
pub const ADC_HARDTRIG_EVT0: u32 = 1;
pub const ADC_HARDTRIG_EVT1: u32 = 2;
pub const ADC_HARDTRIG_EVT0_EVT1: u32 = 3;
pub const ADC_INT_EOCA: u32 = 1;
pub const ADC_INT_EOCB: u32 = 2;
pub const ADC_INT_ALL: u32 = 3;
pub const ADC_FLAG_EOCA: u32 = 1;
pub const ADC_FLAG_EOCB: u32 = 2;
pub const ADC_FLAG_ALL: u32 = 3;
pub const ADC_SYNC_ADC1_ADC2: u32 = 0;
pub const ADC_SYNC_SINGLE_DELAY_TRIG: u32 = 0;
pub const ADC_SYNC_SINGLE_PARALLEL_TRIG: u32 = 32;
pub const ADC_SYNC_CYCLIC_DELAY_TRIG: u32 = 64;
pub const ADC_SYNC_CYCLIC_PARALLEL_TRIG: u32 = 96;
pub const ADC_AWD0: u32 = 0;
pub const ADC_AWD_INT_SEQA: u32 = 64;
pub const ADC_AWD_INT_SEQB: u32 = 128;
pub const ADC_AWD_INT_ALL: u32 = 192;
pub const ADC_AWD_MD_CMP_OUT: u32 = 0;
pub const ADC_AWD_MD_CMP_IN: u32 = 1;
pub const ADC_AWD_FLAG_CH0: u32 = 1;
pub const ADC_AWD_FLAG_CH1: u32 = 2;
pub const ADC_AWD_FLAG_CH2: u32 = 4;
pub const ADC_AWD_FLAG_CH3: u32 = 8;
pub const ADC_AWD_FLAG_CH4: u32 = 16;
pub const ADC_AWD_FLAG_CH5: u32 = 32;
pub const ADC_AWD_FLAG_CH6: u32 = 64;
pub const ADC_AWD_FLAG_CH7: u32 = 128;
pub const ADC_AWD_FLAG_CH8: u32 = 256;
pub const ADC_AWD_FLAG_CH9: u32 = 512;
pub const ADC_AWD_FLAG_CH10: u32 = 1024;
pub const ADC_AWD_FLAG_CH11: u32 = 2048;
pub const ADC_AWD_FLAG_CH12: u32 = 4096;
pub const ADC_AWD_FLAG_CH13: u32 = 8192;
pub const ADC_AWD_FLAG_CH14: u32 = 16384;
pub const ADC_AWD_FLAG_CH15: u32 = 32768;
pub const ADC_AWD_FLAG_CH16: u32 = 65536;
pub const ADC1_AWD_FLAG_ALL: u32 = 131071;
pub const ADC2_AWD_FLAG_ALL: u32 = 511;
pub const ADC_PGA1: u32 = 0;
pub const ADC_PGA_GAIN_2: u32 = 0;
pub const ADC_PGA_GAIN_2P133: u32 = 1;
pub const ADC_PGA_GAIN_2P286: u32 = 2;
pub const ADC_PGA_GAIN_2P667: u32 = 3;
pub const ADC_PGA_GAIN_2P909: u32 = 4;
pub const ADC_PGA_GAIN_3P2: u32 = 5;
pub const ADC_PGA_GAIN_3P556: u32 = 6;
pub const ADC_PGA_GAIN_4: u32 = 7;
pub const ADC_PGA_GAIN_4P571: u32 = 8;
pub const ADC_PGA_GAIN_5P333: u32 = 9;
pub const ADC_PGA_GAIN_6P4: u32 = 10;
pub const ADC_PGA_GAIN_8: u32 = 11;
pub const ADC_PGA_GAIN_10P667: u32 = 12;
pub const ADC_PGA_GAIN_16: u32 = 13;
pub const ADC_PGA_GAIN_32: u32 = 14;
pub const ADC_PGA_VSS_PGAVSS: u32 = 0;
pub const ADC_PGA_VSS_AVSS: u32 = 1;
pub const ADC_PGA_PIN_ADC1_PA0: u32 = 1;
pub const ADC_PGA_PIN_ADC1_PA1: u32 = 2;
pub const ADC_PGA_PIN_ADC1_PA2: u32 = 4;
pub const ADC_PGA_PIN_ADC1_PA3: u32 = 8;
pub const ADC_PGA_PIN_ADC1_PA4: u32 = 16;
pub const ADC_PGA_PIN_ADC1_PA5: u32 = 32;
pub const ADC_PGA_PIN_ADC1_PA6: u32 = 64;
pub const ADC_PGA_PIN_ADC1_PA7: u32 = 128;
pub const ADC_PGA_8BIT_DAC: u32 = 256;
pub const ADC1_PIN_PA0: u32 = 0;
pub const ADC1_PIN_PA1: u32 = 1;
pub const ADC1_PIN_PA2: u32 = 2;
pub const ADC1_PIN_PA3: u32 = 3;
pub const ADC1_PIN_PA4: u32 = 4;
pub const ADC1_PIN_PA5: u32 = 5;
pub const ADC1_PIN_PA6: u32 = 6;
pub const ADC1_PIN_PA7: u32 = 7;
pub const ADC1_PIN_PB0: u32 = 8;
pub const ADC1_PIN_PB1: u32 = 9;
pub const ADC1_PIN_PC0: u32 = 10;
pub const ADC1_PIN_PC1: u32 = 11;
pub const ADC1_PIN_PC2: u32 = 12;
pub const ADC1_PIN_PC3: u32 = 13;
pub const ADC1_PIN_PC4: u32 = 14;
pub const ADC1_PIN_PC5: u32 = 15;
pub const ADC2_PIN_PA4: u32 = 0;
pub const ADC2_PIN_PA5: u32 = 1;
pub const ADC2_PIN_PA6: u32 = 2;
pub const ADC2_PIN_PA7: u32 = 3;
pub const ADC2_PIN_PB0: u32 = 4;
pub const ADC2_PIN_PB1: u32 = 5;
pub const ADC2_PIN_PC0: u32 = 6;
pub const ADC2_PIN_PC1: u32 = 7;
pub const AES_KEY_SIZE_16BYTE: u32 = 16;
pub const AOS_COMM_TRIG1: u32 = 1073741824;
pub const AOS_COMM_TRIG2: u32 = 2147483648;
pub const AOS_COMM_TRIG_MASK: u32 = 3221225472;
pub const AOS_TRIG_SEL_MASK: u32 = 511;
pub const CAN_WORK_MD_NORMAL: u32 = 0;
pub const CAN_WORK_MD_SILENT: u32 = 1;
pub const CAN_WORK_MD_ILB: u32 = 2;
pub const CAN_WORK_MD_ELB: u32 = 3;
pub const CAN_WORK_MD_ELB_SILENT: u32 = 4;
pub const CAN_TX_BUF_PTB: u32 = 0;
pub const CAN_TX_BUF_STB: u32 = 1;
pub const CAN_DLC0: u32 = 0;
pub const CAN_DLC1: u32 = 1;
pub const CAN_DLC2: u32 = 2;
pub const CAN_DLC3: u32 = 3;
pub const CAN_DLC4: u32 = 4;
pub const CAN_DLC5: u32 = 5;
pub const CAN_DLC6: u32 = 6;
pub const CAN_DLC7: u32 = 7;
pub const CAN_DLC8: u32 = 8;
pub const CAN_PTB_SINGLESHOT_TX_DISABLE: u32 = 0;
pub const CAN_PTB_SINGLESHOT_TX_ENABLE: u32 = 16;
pub const CAN_STB_SINGLESHOT_TX_DISABLE: u32 = 0;
pub const CAN_STB_SINGLESHOT_TX_ENABLE: u32 = 8;
pub const CAN_TX_REQ_STB_ONE: u32 = 4;
pub const CAN_TX_REQ_STB_ALL: u32 = 2;
pub const CAN_TX_REQ_PTB: u32 = 16;
pub const CAN_STB_PRIO_MD_DISABLE: u32 = 0;
pub const CAN_STB_PRIO_MD_ENABLE: u32 = 32;
pub const CAN_TX_BUF_EMPTY: u32 = 0;
pub const CAN_TX_BUF_NOT_MORE_THAN_HALF: u32 = 1;
pub const CAN_TX_BUF_MORE_THAN_HALF: u32 = 2;
pub const CAN_TX_BUF_FULL: u32 = 3;
pub const CAN_RX_BUF_EMPTY: u32 = 0;
pub const CAN_RX_BUF_NOT_WARN: u32 = 1;
pub const CAN_RX_BUF_WARN: u32 = 2;
pub const CAN_RX_BUF_FULL: u32 = 3;
pub const CAN_RX_ALL_FRAME_DISABLE: u32 = 0;
pub const CAN_RX_ALL_FRAME_ENABLE: u32 = 8;
pub const CAN_RX_OVF_SAVE_NEW: u32 = 0;
pub const CAN_RX_OVF_DISCARD_NEW: u32 = 64;
pub const CAN_SELF_ACK_DISABLE: u32 = 0;
pub const CAN_SELF_ACK_ENABLE: u32 = 128;
pub const CAN_INT_ERR_INT: u32 = 2;
pub const CAN_INT_STB_TX: u32 = 4;
pub const CAN_INT_PTB_TX: u32 = 8;
pub const CAN_INT_RX_BUF_WARN: u32 = 16;
pub const CAN_INT_RX_BUF_FULL: u32 = 32;
pub const CAN_INT_RX_OVERRUN: u32 = 64;
pub const CAN_INT_RX: u32 = 128;
pub const CAN_INT_BUS_ERR: u32 = 512;
pub const CAN_INT_ARBITR_LOST: u32 = 2048;
pub const CAN_INT_ERR_PASSIVE: u32 = 8192;
pub const CAN_INT_ALL: u32 = 11006;
pub const CAN_FLAG_BUS_OFF: u32 = 1;
pub const CAN_FLAG_TX_GOING: u32 = 2;
pub const CAN_FLAG_RX_GOING: u32 = 4;
pub const CAN_FLAG_RX_BUF_OVF: u32 = 32;
pub const CAN_FLAG_TX_BUF_FULL: u32 = 256;
pub const CAN_FLAG_TX_ABORTED: u32 = 65536;
pub const CAN_FLAG_ERR_INT: u32 = 131072;
pub const CAN_FLAG_STB_TX: u32 = 262144;
pub const CAN_FLAG_PTB_TX: u32 = 524288;
pub const CAN_FLAG_RX_BUF_WARN: u32 = 1048576;
pub const CAN_FLAG_RX_BUF_FULL: u32 = 2097152;
pub const CAN_FLAG_RX_OVERRUN: u32 = 4194304;
pub const CAN_FLAG_RX: u32 = 8388608;
pub const CAN_FLAG_BUS_ERR: u32 = 16777216;
pub const CAN_FLAG_ARBITR_LOST: u32 = 67108864;
pub const CAN_FLAG_ERR_PASSIVE: u32 = 268435456;
pub const CAN_FLAG_ERR_PASSIVE_NODE: u32 = 1073741824;
pub const CAN_FLAG_TEC_REC_WARN: u32 = 2147483648;
pub const CAN_FLAG_ALL: u32 = 3590258983;
pub const CAN_FLAG_CLR_ALL: u32 = 369033216;
pub const CAN_ID_STD_EXT: u32 = 0;
pub const CAN_ID_STD: u32 = 1073741824;
pub const CAN_ID_EXT: u32 = 1610612736;
pub const CAN_STD_ID_MASK: u32 = 2047;
pub const CAN_EXT_ID_MASK: u32 = 536870911;
pub const CAN_ERR_NONE: u32 = 0;
pub const CAN_ERR_BIT: u32 = 1;
pub const CAN_ERR_FORM: u32 = 2;
pub const CAN_ERR_STUFF: u32 = 3;
pub const CAN_ERR_ACK: u32 = 4;
pub const CAN_ERR_CRC: u32 = 5;
pub const CAN_ERR_OTHER: u32 = 6;
pub const CAN_FILTER1: u32 = 1;
pub const CAN_FILTER2: u32 = 2;
pub const CAN_FILTER3: u32 = 4;
pub const CAN_FILTER4: u32 = 8;
pub const CAN_FILTER5: u32 = 16;
pub const CAN_FILTER6: u32 = 32;
pub const CAN_FILTER7: u32 = 64;
pub const CAN_FILTER8: u32 = 128;
pub const CAN_FILTER_ALL: u32 = 255;
pub const CAN_TTC_TX_BUF_MD_CAN: u32 = 0;
pub const CAN_TTC_TX_BUF_MD_TTCAN: u32 = 16;
pub const CAN_TTC_TX_BUF_PTB: u32 = 0;
pub const CAN_TTC_TX_BUF_STB1: u32 = 1;
pub const CAN_TTC_TX_BUF_STB2: u32 = 2;
pub const CAN_TTC_TX_BUF_STB3: u32 = 3;
pub const CAN_TTC_TX_BUF_STB4: u32 = 4;
pub const CAN_TTC_TX_BUF_MARK_EMPTY: u32 = 128;
pub const CAN_TTC_TX_BUF_MARK_FILLED: u32 = 64;
pub const CAN_TTC_INT_TIME_TRIG: u32 = 16;
pub const CAN_TTC_INT_WATCH_TRIG: u32 = 128;
pub const CAN_TTC_INT_ALL: u32 = 144;
pub const CAN_TTC_FLAG_TIME_TRIG: u32 = 8;
pub const CAN_TTC_FLAG_TRIG_ERR: u32 = 32;
pub const CAN_TTC_FLAG_WATCH_TRIG: u32 = 64;
pub const CAN_TTC_FLAG_ALL: u32 = 104;
pub const CAN_TTC_NTU_PRESCALER1: u32 = 0;
pub const CAN_TTC_NTU_PRESCALER2: u32 = 2;
pub const CAN_TTC_NTU_PRESCALER4: u32 = 4;
pub const CAN_TTC_NTU_PRESCALER8: u32 = 6;
pub const CAN_TTC_TRIG_IMMED_TRIG: u32 = 0;
pub const CAN_TTC_TRIG_TIME_TRIG: u32 = 256;
pub const CAN_TTC_TRIG_SINGLESHOT_TX_TRIG: u32 = 512;
pub const CAN_TTC_TRIG_TX_START_TRIG: u32 = 768;
pub const CAN_TTC_TRIG_TX_STOP_TRIG: u32 = 1024;
pub const CLK_PLLX_OFF: u32 = 1;
pub const CLK_PLLX_ON: u32 = 0;
pub const CLK_PLL_OFF: u32 = 1;
pub const CLK_PLL_ON: u32 = 0;
pub const CLK_PLL_SRC_XTAL: u32 = 0;
pub const CLK_PLL_SRC_HRC: u32 = 1;
pub const CLK_XTAL_OFF: u32 = 1;
pub const CLK_XTAL_ON: u32 = 0;
pub const CLK_XTAL_DRV_HIGH: u32 = 0;
pub const CLK_XTAL_DRV_MID: u32 = 16;
pub const CLK_XTAL_DRV_LOW: u32 = 32;
pub const CLK_XTAL_DRV_ULOW: u32 = 48;
pub const CLK_XTAL_SUPDRV_ON: u32 = 128;
pub const CLK_XTAL_SUPDRV_OFF: u32 = 0;
pub const CLK_XTAL_MD_OSC: u32 = 0;
pub const CLK_XTAL_MD_EXCLK: u32 = 64;
pub const CLK_XTAL_STB_133US: u32 = 1;
pub const CLK_XTAL_STB_255US: u32 = 2;
pub const CLK_XTAL_STB_499US: u32 = 3;
pub const CLK_XTAL_STB_988US: u32 = 4;
pub const CLK_XTAL_STB_2MS: u32 = 5;
pub const CLK_XTAL_STB_4MS: u32 = 6;
pub const CLK_XTAL_STB_8MS: u32 = 7;
pub const CLK_XTAL_STB_16MS: u32 = 8;
pub const CLK_XTAL_STB_31MS: u32 = 9;
pub const CLK_XTALSTD_OFF: u32 = 0;
pub const CLK_XTALSTD_ON: u32 = 128;
pub const CLK_XTALSTD_EXP_TYPE_NONE: u32 = 0;
pub const CLK_XTALSTD_EXP_TYPE_RST: u32 = 6;
pub const CLK_XTALSTD_EXP_TYPE_INT: u32 = 1;
pub const CLK_XTAL32_OFF: u32 = 1;
pub const CLK_XTAL32_ON: u32 = 0;
pub const CLK_XTAL32_DRV_MID: u32 = 0;
pub const CLK_XTAL32_DRV_HIGH: u32 = 1;
pub const CLK_XTAL32_FILTER_ALL_MD: u32 = 0;
pub const CLK_XTAL32_FILTER_RUN_MD: u32 = 1;
pub const CLK_XTAL32_FILTER_OFF: u32 = 3;
pub const CLK_HRC_OFF: u32 = 1;
pub const CLK_HRC_ON: u32 = 0;
pub const CLK_STB_FLAG_HRC: u32 = 1;
pub const CLK_STB_FLAG_XTAL: u32 = 8;
pub const CLK_STB_FLAG_PLL: u32 = 32;
pub const CLK_STB_FLAG_PLLX: u32 = 64;
pub const CLK_STB_FLAG_MASK: u32 = 105;
pub const CLK_SYSCLK_SRC_HRC: u32 = 0;
pub const CLK_SYSCLK_SRC_MRC: u32 = 1;
pub const CLK_SYSCLK_SRC_LRC: u32 = 2;
pub const CLK_SYSCLK_SRC_XTAL: u32 = 3;
pub const CLK_SYSCLK_SRC_XTAL32: u32 = 4;
pub const CLK_SYSCLK_SRC_PLL: u32 = 5;
pub const CLK_BUS_PCLK0: u32 = 7;
pub const CLK_BUS_PCLK1: u32 = 112;
pub const CLK_BUS_PCLK2: u32 = 1792;
pub const CLK_BUS_PCLK3: u32 = 28672;
pub const CLK_BUS_PCLK4: u32 = 458752;
pub const CLK_BUS_EXCLK: u32 = 7340032;
pub const CLK_BUS_HCLK: u32 = 117440512;
pub const CLK_BUS_CLK_ALL: u32 = 125269879;
pub const CLK_SYSCLK_DIV1: u32 = 0;
pub const CLK_SYSCLK_DIV2: u32 = 1;
pub const CLK_SYSCLK_DIV4: u32 = 2;
pub const CLK_SYSCLK_DIV8: u32 = 3;
pub const CLK_SYSCLK_DIV16: u32 = 4;
pub const CLK_SYSCLK_DIV32: u32 = 5;
pub const CLK_SYSCLK_DIV64: u32 = 6;
pub const CLK_HCLK_DIV1: u32 = 0;
pub const CLK_HCLK_DIV2: u32 = 16777216;
pub const CLK_HCLK_DIV4: u32 = 33554432;
pub const CLK_HCLK_DIV8: u32 = 50331648;
pub const CLK_HCLK_DIV16: u32 = 67108864;
pub const CLK_HCLK_DIV32: u32 = 83886080;
pub const CLK_HCLK_DIV64: u32 = 100663296;
pub const CLK_PCLK1_DIV1: u32 = 0;
pub const CLK_PCLK1_DIV2: u32 = 16;
pub const CLK_PCLK1_DIV4: u32 = 32;
pub const CLK_PCLK1_DIV8: u32 = 48;
pub const CLK_PCLK1_DIV16: u32 = 64;
pub const CLK_PCLK1_DIV32: u32 = 80;
pub const CLK_PCLK1_DIV64: u32 = 96;
pub const CLK_PCLK4_DIV1: u32 = 0;
pub const CLK_PCLK4_DIV2: u32 = 65536;
pub const CLK_PCLK4_DIV4: u32 = 131072;
pub const CLK_PCLK4_DIV8: u32 = 196608;
pub const CLK_PCLK4_DIV16: u32 = 262144;
pub const CLK_PCLK4_DIV32: u32 = 327680;
pub const CLK_PCLK4_DIV64: u32 = 393216;
pub const CLK_PCLK3_DIV1: u32 = 0;
pub const CLK_PCLK3_DIV2: u32 = 4096;
pub const CLK_PCLK3_DIV4: u32 = 8192;
pub const CLK_PCLK3_DIV8: u32 = 12288;
pub const CLK_PCLK3_DIV16: u32 = 16384;
pub const CLK_PCLK3_DIV32: u32 = 20480;
pub const CLK_PCLK3_DIV64: u32 = 24576;
pub const CLK_EXCLK_DIV1: u32 = 0;
pub const CLK_EXCLK_DIV2: u32 = 1048576;
pub const CLK_EXCLK_DIV4: u32 = 2097152;
pub const CLK_EXCLK_DIV8: u32 = 3145728;
pub const CLK_EXCLK_DIV16: u32 = 4194304;
pub const CLK_EXCLK_DIV32: u32 = 5242880;
pub const CLK_EXCLK_DIV64: u32 = 6291456;
pub const CLK_PCLK2_DIV1: u32 = 0;
pub const CLK_PCLK2_DIV2: u32 = 256;
pub const CLK_PCLK2_DIV4: u32 = 512;
pub const CLK_PCLK2_DIV8: u32 = 768;
pub const CLK_PCLK2_DIV16: u32 = 1024;
pub const CLK_PCLK2_DIV32: u32 = 1280;
pub const CLK_PCLK2_DIV64: u32 = 1536;
pub const CLK_PCLK0_DIV1: u32 = 0;
pub const CLK_PCLK0_DIV2: u32 = 1;
pub const CLK_PCLK0_DIV4: u32 = 2;
pub const CLK_PCLK0_DIV8: u32 = 3;
pub const CLK_PCLK0_DIV16: u32 = 4;
pub const CLK_PCLK0_DIV32: u32 = 5;
pub const CLK_PCLK0_DIV64: u32 = 6;
pub const CLK_USBCLK_SYSCLK_DIV2: u32 = 32;
pub const CLK_USBCLK_SYSCLK_DIV3: u32 = 48;
pub const CLK_USBCLK_SYSCLK_DIV4: u32 = 64;
pub const CLK_USBCLK_PLLP: u32 = 128;
pub const CLK_USBCLK_PLLQ: u32 = 144;
pub const CLK_USBCLK_PLLR: u32 = 160;
pub const CLK_USBCLK_PLLXP: u32 = 176;
pub const CLK_USBCLK_PLLXQ: u32 = 192;
pub const CLK_USBCLK_PLLXR: u32 = 208;
pub const CLK_PERIPHCLK_PCLK: u32 = 0;
pub const CLK_PERIPHCLK_PLLP: u32 = 8;
pub const CLK_PERIPHCLK_PLLQ: u32 = 9;
pub const CLK_PERIPHCLK_PLLR: u32 = 10;
pub const CLK_PERIPHCLK_PLLXP: u32 = 11;
pub const CLK_PERIPHCLK_PLLXQ: u32 = 12;
pub const CLK_PERIPHCLK_PLLXR: u32 = 13;
pub const CLK_I2S1: u32 = 0;
pub const CLK_I2S2: u32 = 1;
pub const CLK_I2S3: u32 = 2;
pub const CLK_I2S4: u32 = 3;
pub const CLK_TPIUCLK_DIV1: u32 = 0;
pub const CLK_TPIUCLK_DIV2: u32 = 1;
pub const CLK_TPIUCLK_DIV4: u32 = 2;
pub const CLK_MCO1: u32 = 0;
pub const CLK_MCO2: u32 = 1;
pub const CLK_MCO_SRC_HRC: u32 = 0;
pub const CLK_MCO_SRC_MRC: u32 = 1;
pub const CLK_MCO_SRC_LRC: u32 = 2;
pub const CLK_MCO_SRC_XTAL: u32 = 3;
pub const CLK_MCO_SRC_XTAL32: u32 = 4;
pub const CLK_MCO_SRC_PLLP: u32 = 6;
pub const CLK_MCO_SRC_PLLXP: u32 = 7;
pub const CLK_MCO_SRC_PLLQ: u32 = 8;
pub const CLK_MCO_SRC_PLLXQ: u32 = 9;
pub const CLK_MCO_SRC_HCLK: u32 = 11;
pub const CLK_MCO_DIV1: u32 = 0;
pub const CLK_MCO_DIV2: u32 = 16;
pub const CLK_MCO_DIV4: u32 = 32;
pub const CLK_MCO_DIV8: u32 = 48;
pub const CLK_MCO_DIV16: u32 = 64;
pub const CLK_MCO_DIV32: u32 = 80;
pub const CLK_MCO_DIV64: u32 = 96;
pub const CLK_MCO_DIV128: u32 = 112;
pub const VISR_OFFSET: u32 = 8;
pub const CMP_POSITIVE_NONE: u32 = 0;
pub const CMP1_POSITIVE_CMP1_INP1: u32 = 256;
pub const CMP1_POSITIVE_CMP1_INP2: u32 = 512;
pub const CMP1_POSITIVE_CMP1_INP3: u32 = 1024;
pub const CMP1_POSITIVE_PGAO: u32 = 6144;
pub const CMP1_POSITIVE_PGAO_BP: u32 = 10240;
pub const CMP1_POSITIVE_CMP1_INP4: u32 = 18432;
pub const CMP2_POSITIVE_CMP2_INP1: u32 = 256;
pub const CMP2_POSITIVE_CMP2_INP2: u32 = 512;
pub const CMP2_POSITIVE_CMP2_INP3: u32 = 1024;
pub const CMP2_POSITIVE_PGAO: u32 = 6144;
pub const CMP2_POSITIVE_PGAO_BP: u32 = 10240;
pub const CMP3_POSITIVE_CMP3_INP1: u32 = 256;
pub const CMP3_POSITIVE_CMP3_INP2: u32 = 512;
pub const CMP3_POSITIVE_CMP3_INP3: u32 = 1024;
pub const CMP3_POSITIVE_CMP3_INP4: u32 = 2048;
pub const CMP_SCAN_STAT_INP_NONE: u32 = 0;
pub const CMP_SCAN_STAT_INP1: u32 = 256;
pub const CMP_SCAN_STAT_INP2: u32 = 512;
pub const CMP_SCAN_STAT_INP3: u32 = 1024;
pub const CMP_SCAN_STAT_INP4: u32 = 2048;
pub const CMP_NEGATIVE_NONE: u32 = 0;
pub const CMP_NEGATIVE_INM1: u32 = 1;
pub const CMP_NEGATIVE_INM2: u32 = 2;
pub const CMP_NEGATIVE_INM3: u32 = 4;
pub const CMP_NEGATIVE_INM4: u32 = 8;
pub const CMP_OUT_INVT_OFF: u32 = 0;
pub const CMP_OUT_INVT_ON: u32 = 8192;
pub const CMP_DETECT_EDGS_NONE: u32 = 0;
pub const CMP_DETECT_EDGS_RISING: u32 = 32;
pub const CMP_DETECT_EDGS_FALLING: u32 = 64;
pub const CMP_DETECT_EDGS_BOTH: u32 = 96;
pub const CMP_OUT_FILTER_NONE: u32 = 0;
pub const CMP_OUT_FILTER_CLK: u32 = 1;
pub const CMP_OUT_FILTER_CLK_DIV2: u32 = 2;
pub const CMP_OUT_FILTER_CLK_DIV4: u32 = 3;
pub const CMP_OUT_FILTER_CLK_DIV8: u32 = 4;
pub const CMP_OUT_FILTER_CLK_DIV16: u32 = 5;
pub const CMP_OUT_FILTER_CLK_DIV32: u32 = 6;
pub const CMP_OUT_FILTER_CLK_DIV64: u32 = 7;
pub const CMP_ADC_REF_VREF: u32 = 16;
pub const CMP_ADC_REF_DA2: u32 = 2;
pub const CMP_ADC_REF_DA1: u32 = 1;
pub const CMP_8BITDAC_CH1: u32 = 1;
pub const CMP_8BITDAC_CH2: u32 = 2;
pub const CRC_CRC16: u32 = 0;
pub const CRC_CRC32: u32 = 2;
pub const CRC_DATA_WIDTH_8BIT: u32 = 1;
pub const CRC_DATA_WIDTH_16BIT: u32 = 2;
pub const CRC_DATA_WIDTH_32BIT: u32 = 4;
pub const CRC_INIT_VALUE_DEFAULT: u32 = 4294967295;
pub const CRC_REFIN_DISABLE: u32 = 0;
pub const CRC_REFIN_ENABLE: u32 = 4;
pub const CRC_REFOUT_DISABLE: u32 = 0;
pub const CRC_REFOUT_ENABLE: u32 = 8;
pub const CRC_XOROUT_DISABLE: u32 = 0;
pub const CRC_XOROUT_ENABLE: u32 = 16;
pub const DBGC_PERIPH_SWDT: u32 = 1;
pub const DBGC_PERIPH_WDT: u32 = 2;
pub const DBGC_PERIPH_RTC: u32 = 4;
pub const DBGC_PERIPH_TMR0_1: u32 = 16384;
pub const DBGC_PERIPH_TMR0_2: u32 = 32768;
pub const DBGC_PERIPH_TMR4_1: u32 = 1048576;
pub const DBGC_PERIPH_TMR4_2: u32 = 2097152;
pub const DBGC_PERIPH_TMR4_3: u32 = 4194304;
pub const DBGC_PERIPH_TMR6_1: u32 = 8388608;
pub const DBGC_PERIPH_TMR6_2: u32 = 16777216;
pub const DBGC_PERIPH_TMR6_3: u32 = 33554432;
pub const DBGC_PERIPH_TMRA_1: u32 = 67108864;
pub const DBGC_PERIPH_TMRA_2: u32 = 134217728;
pub const DBGC_PERIPH_TMRA_3: u32 = 268435456;
pub const DBGC_PERIPH_TMRA_4: u32 = 536870912;
pub const DBGC_PERIPH_TMRA_5: u32 = 1073741824;
pub const DBGC_PERIPH_TMRA_6: u32 = 2147483648;
pub const DBGC_TRACE_ASYNC: u32 = 0;
pub const DBGC_TRACE_SYNC_1BIT: u32 = 1;
pub const DBGC_TRACE_SYNC_2BIT: u32 = 2;
pub const DBGC_TRACE_SYNC_4BIT: u32 = 3;
pub const DCU_DATA_WIDTH_8BIT: u32 = 0;
pub const DCU_DATA_WIDTH_16BIT: u32 = 8;
pub const DCU_DATA_WIDTH_32BIT: u32 = 16;
pub const DCU_CMP_TRIG_DATA0: u32 = 0;
pub const DCU_CMP_TRIG_DATA0_DATA1_DATA2: u32 = 256;
pub const DCU_MD_INVD: u32 = 0;
pub const DCU_MD_ADD: u32 = 1;
pub const DCU_MD_SUB: u32 = 2;
pub const DCU_MD_HW_ADD: u32 = 3;
pub const DCU_MD_HW_SUB: u32 = 4;
pub const DCU_MD_CMP: u32 = 5;
pub const DCU_FLAG_CARRY: u32 = 1;
pub const DCU_FLAG_DATA0_LT_DATA2: u32 = 2;
pub const DCU_FLAG_DATA0_EQ_DATA2: u32 = 4;
pub const DCU_FLAG_DATA0_GT_DATA2: u32 = 8;
pub const DCU_FLAG_DATA0_LT_DATA1: u32 = 16;
pub const DCU_FLAG_DATA0_EQ_DATA1: u32 = 32;
pub const DCU_FLAG_DATA0_GT_DATA1: u32 = 64;
pub const DCU_FLAG_ALL: u32 = 127;
pub const DCU_CATEGORY_OP: u32 = 0;
pub const DCU_CATEGORY_CMP_WIN: u32 = 1;
pub const DCU_CATEGORY_CMP_NON_WIN: u32 = 2;
pub const DCU_INT_CMP_DATA0_LT_DATA2: u32 = 2;
pub const DCU_INT_CMP_DATA0_EQ_DATA2: u32 = 4;
pub const DCU_INT_CMP_DATA0_GT_DATA2: u32 = 8;
pub const DCU_INT_CMP_DATA0_LT_DATA1: u32 = 16;
pub const DCU_INT_CMP_DATA0_EQ_DATA1: u32 = 32;
pub const DCU_INT_CMP_DATA0_GT_DATA1: u32 = 64;
pub const DCU_INT_CMP_NON_WIN_ALL: u32 = 126;
pub const DCU_INT_CMP_WIN_INSIDE: u32 = 128;
pub const DCU_INT_CMP_WIN_OUTSIDE: u32 = 256;
pub const DCU_INT_CMP_WIN_ALL: u32 = 384;
pub const DCU_INT_OP_CARRY: u32 = 1;
pub const DCU_DATA0_IDX: u32 = 0;
pub const DCU_DATA1_IDX: u32 = 1;
pub const DCU_DATA2_IDX: u32 = 2;
pub const DMA_CH0: u32 = 0;
pub const DMA_CH1: u32 = 1;
pub const DMA_CH2: u32 = 2;
pub const DMA_CH3: u32 = 3;
pub const DMA_MX_CH0: u32 = 1;
pub const DMA_MX_CH1: u32 = 2;
pub const DMA_MX_CH2: u32 = 4;
pub const DMA_MX_CH3: u32 = 8;
pub const DMA_MX_CH_ALL: u32 = 15;
pub const DMA_FLAG_REQ_ERR_CH0: u32 = 65536;
pub const DMA_FLAG_REQ_ERR_CH1: u32 = 131072;
pub const DMA_FLAG_REQ_ERR_CH2: u32 = 262144;
pub const DMA_FLAG_REQ_ERR_CH3: u32 = 524288;
pub const DMA_FLAG_TRANS_ERR_CH0: u32 = 1;
pub const DMA_FLAG_TRANS_ERR_CH1: u32 = 2;
pub const DMA_FLAG_TRANS_ERR_CH2: u32 = 4;
pub const DMA_FLAG_TRANS_ERR_CH3: u32 = 8;
pub const DMA_FLAG_BTC_CH0: u32 = 65536;
pub const DMA_FLAG_BTC_CH1: u32 = 131072;
pub const DMA_FLAG_BTC_CH2: u32 = 262144;
pub const DMA_FLAG_BTC_CH3: u32 = 524288;
pub const DMA_FLAG_TC_CH0: u32 = 1;
pub const DMA_FLAG_TC_CH1: u32 = 2;
pub const DMA_FLAG_TC_CH2: u32 = 4;
pub const DMA_FLAG_TC_CH3: u32 = 8;
pub const DMA_INT_REQ_ERR_CH0: u32 = 65536;
pub const DMA_INT_REQ_ERR_CH1: u32 = 131072;
pub const DMA_INT_REQ_ERR_CH2: u32 = 262144;
pub const DMA_INT_REQ_ERR_CH3: u32 = 524288;
pub const DMA_INT_TRANS_ERR_CH0: u32 = 1;
pub const DMA_INT_TRANS_ERR_CH1: u32 = 2;
pub const DMA_INT_TRANS_ERR_CH2: u32 = 4;
pub const DMA_INT_TRANS_ERR_CH3: u32 = 8;
pub const DMA_INT_BTC_CH0: u32 = 65536;
pub const DMA_INT_BTC_CH1: u32 = 131072;
pub const DMA_INT_BTC_CH2: u32 = 262144;
pub const DMA_INT_BTC_CH3: u32 = 524288;
pub const DMA_INT_TC_CH0: u32 = 1;
pub const DMA_INT_TC_CH1: u32 = 2;
pub const DMA_INT_TC_CH2: u32 = 4;
pub const DMA_INT_TC_CH3: u32 = 8;
pub const DMA_FLAG_ERR_MASK: u32 = 983055;
pub const DMA_FLAG_TRANS_MASK: u32 = 983055;
pub const DMA_INT_ERR_MASK: u32 = 983055;
pub const DMA_INT_TRANS_MASK: u32 = 983055;
pub const DMA_STAT_REQ_RECONFIG: u32 = 32768;
pub const DMA_STAT_REQ_CH0: u32 = 1;
pub const DMA_STAT_REQ_CH1: u32 = 2;
pub const DMA_STAT_REQ_CH2: u32 = 4;
pub const DMA_STAT_REQ_CH3: u32 = 8;
pub const DMA_STAT_REQ_MASK: u32 = 32783;
pub const DMA_STAT_TRANS_CH0: u32 = 65536;
pub const DMA_STAT_TRANS_CH1: u32 = 131072;
pub const DMA_STAT_TRANS_CH2: u32 = 262144;
pub const DMA_STAT_TRANS_CH3: u32 = 524288;
pub const DMA_STAT_TRANS_DMA: u32 = 1;
pub const DMA_STAT_TRANS_RECONFIG: u32 = 2;
pub const DMA_STAT_TRANS_MASK: u32 = 983043;
pub const DMA_DATAWIDTH_8BIT: u32 = 0;
pub const DMA_DATAWIDTH_16BIT: u32 = 256;
pub const DMA_DATAWIDTH_32BIT: u32 = 512;
pub const DMA_LLP_DISABLE: u32 = 0;
pub const DMA_LLP_ENABLE: u32 = 1024;
pub const DMA_LLP_WAIT: u32 = 0;
pub const DMA_LLP_RUN: u32 = 2048;
pub const DMA_SRC_ADDR_FIX: u32 = 0;
pub const DMA_SRC_ADDR_INC: u32 = 1;
pub const DMA_SRC_ADDR_DEC: u32 = 2;
pub const DMA_DEST_ADDR_FIX: u32 = 0;
pub const DMA_DEST_ADDR_INC: u32 = 4;
pub const DMA_DEST_ADDR_DEC: u32 = 8;
pub const DMA_INT_ENABLE: u32 = 4096;
pub const DMA_INT_DISABLE: u32 = 0;
pub const DMA_RPT_NONE: u32 = 0;
pub const DMA_RPT_SRC: u32 = 16;
pub const DMA_RPT_DEST: u32 = 32;
pub const DMA_RPT_BOTH: u32 = 48;
pub const DMA_NON_SEQ_NONE: u32 = 0;
pub const DMA_NON_SEQ_SRC: u32 = 64;
pub const DMA_NON_SEQ_DEST: u32 = 128;
pub const DMA_NON_SEQ_BOTH: u32 = 192;
pub const DMA_RC_CNT_KEEP: u32 = 0;
pub const DMA_RC_CNT_SRC: u32 = 1048576;
pub const DMA_RC_CNT_DEST: u32 = 2097152;
pub const DMA_RC_DEST_ADDR_KEEP: u32 = 0;
pub const DMA_RC_DEST_ADDR_NS: u32 = 262144;
pub const DMA_RC_DEST_ADDR_RPT: u32 = 524288;
pub const DMA_RC_SRC_ADDR_KEEP: u32 = 0;
pub const DMA_RC_SRC_ADDR_NS: u32 = 65536;
pub const DMA_RC_SRC_ADDR_RPT: u32 = 131072;
pub const EFM_START_ADDR: u32 = 0;
pub const EFM_END_ADDR: u32 = 524287;
pub const EFM_OTP_START_ADDR: u32 = 50334720;
pub const EFM_OTP_END_ADDR: u32 = 50335739;
pub const EFM_OTP_LOCK_ADDR_START: u32 = 50335680;
pub const EFM_OTP_LOCK_ADDR_END: u32 = 50335740;
pub const EFM_SECURITY_START_ADDR: u32 = 51904480;
pub const EFM_SECURITY_END_ADDR: u32 = 51904511;
pub const EFM_CHIP_ALL: u32 = 1;
pub const EFM_BUS_HOLD: u32 = 0;
pub const EFM_BUS_RELEASE: u32 = 1;
pub const EFM_WAIT_CYCLE0: u32 = 0;
pub const EFM_WAIT_CYCLE1: u32 = 16;
pub const EFM_WAIT_CYCLE2: u32 = 32;
pub const EFM_WAIT_CYCLE3: u32 = 48;
pub const EFM_WAIT_CYCLE4: u32 = 64;
pub const EFM_WAIT_CYCLE5: u32 = 80;
pub const EFM_WAIT_CYCLE6: u32 = 96;
pub const EFM_WAIT_CYCLE7: u32 = 112;
pub const EFM_WAIT_CYCLE8: u32 = 128;
pub const EFM_WAIT_CYCLE9: u32 = 144;
pub const EFM_WAIT_CYCLE10: u32 = 160;
pub const EFM_WAIT_CYCLE11: u32 = 176;
pub const EFM_WAIT_CYCLE12: u32 = 192;
pub const EFM_WAIT_CYCLE13: u32 = 208;
pub const EFM_WAIT_CYCLE14: u32 = 224;
pub const EFM_WAIT_CYCLE15: u32 = 240;
pub const EFM_SWAP_ADDR: u32 = 524252;
pub const EFM_SWAP_DATA: u32 = 4294918945;
pub const EFM_MD_READONLY: u32 = 0;
pub const EFM_MD_PGM_SINGLE: u32 = 16;
pub const EFM_MD_PGM_READBACK: u32 = 32;
pub const EFM_MD_PGM_SEQ: u32 = 48;
pub const EFM_MD_ERASE_SECTOR: u32 = 64;
pub const EFM_MD_ERASE_ALL_CHIP: u32 = 80;
pub const EFM_FLAG_PEWERR: u32 = 1;
pub const EFM_FLAG_PGMISMTCH: u32 = 8;
pub const EFM_FLAG_OPTEND: u32 = 16;
pub const EFM_FLAG_COLERR: u32 = 32;
pub const EFM_FLAG_PEPRTERR: u32 = 2;
pub const EFM_FLAG_RDY: u32 = 256;
pub const EFM_FLAG_PGSZERR: u32 = 4;
pub const EFM_FLAG_ALL: u32 = 319;
pub const EFM_INT_PEERR: u32 = 1;
pub const EFM_INT_OPTEND: u32 = 2;
pub const EFM_INT_COLERR: u32 = 4;
pub const EFM_INT_ALL: u32 = 7;
pub const EFM_CACHE_ALL: u32 = 16842752;
pub const EFM_REG_UNLOCK_KEY1: u32 = 291;
pub const EFM_REG_UNLOCK_KEY2: u32 = 12816;
pub const EFM_REG_LOCK_KEY: u32 = 0;
pub const EFM_SECTOR_SIZE: u32 = 8192;
pub const EFM_OTP_BASE1_ADDR: u32 = 50334720;
pub const EFM_OTP_BASE1_SIZE: u32 = 64;
pub const EFM_OTP_BASE1_OFFSET: u32 = 0;
pub const EFM_OTP_LOCK_ADDR: u32 = 50335680;
pub const EFM_OTP_BLOCK0: u32 = 50334720;
pub const EFM_OTP_BLOCK1: u32 = 50334784;
pub const EFM_OTP_BLOCK2: u32 = 50334848;
pub const EFM_OTP_BLOCK3: u32 = 50334912;
pub const EFM_OTP_BLOCK4: u32 = 50334976;
pub const EFM_OTP_BLOCK5: u32 = 50335040;
pub const EFM_OTP_BLOCK6: u32 = 50335104;
pub const EFM_OTP_BLOCK7: u32 = 50335168;
pub const EFM_OTP_BLOCK8: u32 = 50335232;
pub const EFM_OTP_BLOCK9: u32 = 50335296;
pub const EFM_OTP_BLOCK10: u32 = 50335360;
pub const EFM_OTP_BLOCK11: u32 = 50335424;
pub const EFM_OTP_BLOCK12: u32 = 50335488;
pub const EFM_OTP_BLOCK13: u32 = 50335552;
pub const EFM_OTP_BLOCK14: u32 = 50335616;
pub const EFM_REMAP_REG_LOCK_KEY: u32 = 0;
pub const EFM_REMAP_REG_UNLOCK_KEY1: u32 = 291;
pub const EFM_REMAP_REG_UNLOCK_KEY2: u32 = 12816;
pub const EFM_REMAP_OFF: u32 = 0;
pub const EFM_REMAP_ON: u32 = 2147483648;
pub const EFM_REMAP_4K: u32 = 12;
pub const EFM_REMAP_8K: u32 = 13;
pub const EFM_REMAP_16K: u32 = 14;
pub const EFM_REMAP_32K: u32 = 15;
pub const EFM_REMAP_64K: u32 = 16;
pub const EFM_REMAP_128K: u32 = 17;
pub const EFM_REMAP_256K: u32 = 18;
pub const EFM_REMAP_512K: u32 = 19;
pub const EFM_REMAP_SIZE_MAX: u32 = 19;
pub const EFM_REMAP_IDX0: u32 = 0;
pub const EFM_REMAP_IDX1: u32 = 1;
pub const EFM_REMAP_BASE_ADDR0: u32 = 33554432;
pub const EFM_REMAP_BASE_ADDR1: u32 = 34078720;
pub const EFM_REMAP_ROM_END_ADDR: u32 = 524287;
pub const EFM_REMAP_RAM_START_ADDR: u32 = 536838144;
pub const EFM_REMAP_RAM_END_ADDR: u32 = 536870911;
pub const EFM_PROTECT_LEVEL1: u32 = 1;
pub const EFM_PROTECT_LEVEL2: u32 = 2;
pub const EFM_PROTECT_LEVEL_ALL: u32 = 3;
pub const EFM_MCU_PROTECT1_FREE: u32 = 0;
pub const EFM_MCU_PROTECT1_LOCK: u32 = 1;
pub const EFM_MCU_PROTECT1_UNLOCK: u32 = 2;
pub const EFM_MCU_PROTECT2_LOCK: u32 = 4;
pub const EMB_CMP1_DISABLE: u32 = 0;
pub const EMB_CMP2_DISABLE: u32 = 0;
pub const EMB_CMP3_DISABLE: u32 = 0;
pub const EMB_CMP1_ENABLE: u32 = 2;
pub const EMB_CMP2_ENABLE: u32 = 4;
pub const EMB_CMP3_ENABLE: u32 = 8;
pub const EMB_OSC_DISABLE: u32 = 0;
pub const EMB_OSC_ENABLE: u32 = 32;
pub const EMB_TMR4_PWM_W_DISABLE: u32 = 0;
pub const EMB_TMR4_PWM_V_DISABLE: u32 = 0;
pub const EMB_TMR4_PWM_U_DISABLE: u32 = 0;
pub const EMB_TMR4_PWM_W_ENABLE: u32 = 64;
pub const EMB_TMR4_PWM_V_ENABLE: u32 = 128;
pub const EMB_TMR4_PWM_U_ENABLE: u32 = 256;
pub const EMB_DETECT_TMR4_PWM_W_BOTH_LOW: u32 = 0;
pub const EMB_DETECT_TMR4_PWM_V_BOTH_LOW: u32 = 0;
pub const EMB_DETECT_TMR4_PWM_U_BOTH_LOW: u32 = 0;
pub const EMB_DETECT_TMR4_PWM_W_BOTH_HIGH: u32 = 1;
pub const EMB_DETECT_TMR4_PWM_V_BOTH_HIGH: u32 = 2;
pub const EMB_DETECT_TMR4_PWM_U_BOTH_HIGH: u32 = 4;
pub const EMB_TMR6_1_PWM_DISABLE: u32 = 0;
pub const EMB_TMR6_2_PWM_DISABLE: u32 = 0;
pub const EMB_TMR6_3_PWM_DISABLE: u32 = 0;
pub const EMB_TMR6_1_PWM_ENABLE: u32 = 64;
pub const EMB_TMR6_2_PWM_ENABLE: u32 = 128;
pub const EMB_TMR6_3_PWM_ENABLE: u32 = 256;
pub const EMB_DETECT_TMR6_1_PWM_BOTH_LOW: u32 = 0;
pub const EMB_DETECT_TMR6_2_PWM_BOTH_LOW: u32 = 0;
pub const EMB_DETECT_TMR6_3_PWM_BOTH_LOW: u32 = 0;
pub const EMB_DETECT_TMR6_1_PWM_BOTH_HIGH: u32 = 1;
pub const EMB_DETECT_TMR6_2_PWM_BOTH_HIGH: u32 = 2;
pub const EMB_DETECT_TMR6_3_PWM_BOTH_HIGH: u32 = 4;
pub const EMB_PORT1_DISABLE: u32 = 0;
pub const EMB_PORT1_ENABLE: u32 = 1;
pub const EMB_PORT1_DETECT_LVL_HIGH: u32 = 0;
pub const EMB_PORT1_DETECT_LVL_LOW: u32 = 2147483648;
pub const EMB_PORT1_FILTER_DISABLE: u32 = 0;
pub const EMB_PORT1_FILTER_ENABLE: u32 = 1073741824;
pub const EMB_PORT1_FILTER_CLK_DIV1: u32 = 0;
pub const EMB_PORT1_FILTER_CLK_DIV8: u32 = 268435456;
pub const EMB_PORT1_FILTER_CLK_DIV32: u32 = 536870912;
pub const EMB_PORT1_FILTER_CLK_DIV128: u32 = 805306368;
pub const EMB_FLAG_PWMS: u32 = 2;
pub const EMB_FLAG_CMP: u32 = 4;
pub const EMB_FLAG_OSC: u32 = 8;
pub const EMB_FLAG_PORT1: u32 = 1;
pub const EMB_STAT_PWMS: u32 = 32;
pub const EMB_STAT_PORT1: u32 = 16;
pub const EMB_FLAG_ALL: u32 = 63;
pub const EMB_FLAG_CLR_ALL: u32 = 15;
pub const EMB_INT_PWMS: u32 = 2;
pub const EMB_INT_CMP: u32 = 4;
pub const EMB_INT_OSC: u32 = 8;
pub const EMB_INT_PORT1: u32 = 1;
pub const EMB_INT_ALL: u32 = 15;
pub const EVT_PORT_1: u32 = 0;
pub const EVT_PORT_2: u32 = 1;
pub const EVT_PORT_3: u32 = 2;
pub const EVT_PORT_4: u32 = 3;
pub const EVT_PIN_00: u32 = 1;
pub const EVT_PIN_01: u32 = 2;
pub const EVT_PIN_02: u32 = 4;
pub const EVT_PIN_03: u32 = 8;
pub const EVT_PIN_04: u32 = 16;
pub const EVT_PIN_05: u32 = 32;
pub const EVT_PIN_06: u32 = 64;
pub const EVT_PIN_07: u32 = 128;
pub const EVT_PIN_08: u32 = 256;
pub const EVT_PIN_09: u32 = 512;
pub const EVT_PIN_10: u32 = 1024;
pub const EVT_PIN_11: u32 = 2048;
pub const EVT_PIN_12: u32 = 4096;
pub const EVT_PIN_13: u32 = 8192;
pub const EVT_PIN_14: u32 = 16384;
pub const EVT_PIN_15: u32 = 32768;
pub const EVT_PIN_All: u32 = 65535;
pub const EVT_PIN_MASK: u32 = 65535;
pub const EP_DIR_IN: u32 = 0;
pub const EP_DIR_OUT: u32 = 1;
pub const EP_FILTER_OFF: u32 = 0;
pub const EP_FILTER_ON: u32 = 1;
pub const EP_FCLK_DIV1: u32 = 0;
pub const EP_FCLK_DIV8: u32 = 2;
pub const EP_FCLK_DIV32: u32 = 4;
pub const EP_FCLK_DIV64: u32 = 6;
pub const EP_TRIG_NONE: u32 = 0;
pub const EP_TRIG_FALLING: u32 = 1;
pub const EP_TRIG_RISING: u32 = 2;
pub const EP_TRIG_BOTH: u32 = 3;
pub const EP_OPS_NONE: u32 = 0;
pub const EP_OPS_LOW: u32 = 1;
pub const EP_OPS_HIGH: u32 = 2;
pub const EP_OPS_TOGGLE: u32 = 3;
pub const FCG0_PERIPH_SRAMH: u32 = 1;
pub const FCG0_PERIPH_SRAM12: u32 = 16;
pub const FCG0_PERIPH_SRAM3: u32 = 256;
pub const FCG0_PERIPH_SRAMRET: u32 = 1024;
pub const FCG0_PERIPH_DMA1: u32 = 16384;
pub const FCG0_PERIPH_DMA2: u32 = 32768;
pub const FCG0_PERIPH_FCM: u32 = 65536;
pub const FCG0_PERIPH_AOS: u32 = 131072;
pub const FCG0_PERIPH_AES: u32 = 1048576;
pub const FCG0_PERIPH_HASH: u32 = 2097152;
pub const FCG0_PERIPH_TRNG: u32 = 4194304;
pub const FCG0_PERIPH_CRC: u32 = 8388608;
pub const FCG0_PERIPH_DCU1: u32 = 16777216;
pub const FCG0_PERIPH_DCU2: u32 = 33554432;
pub const FCG0_PERIPH_DCU3: u32 = 67108864;
pub const FCG0_PERIPH_DCU4: u32 = 134217728;
pub const FCG0_PERIPH_KEY: u32 = 2147483648;
pub const FCG1_PERIPH_CAN: u32 = 1;
pub const FCG1_PERIPH_QSPI: u32 = 8;
pub const FCG1_PERIPH_I2C1: u32 = 16;
pub const FCG1_PERIPH_I2C2: u32 = 32;
pub const FCG1_PERIPH_I2C3: u32 = 64;
pub const FCG1_PERIPH_USBFS: u32 = 256;
pub const FCG1_PERIPH_SDIOC1: u32 = 1024;
pub const FCG1_PERIPH_SDIOC2: u32 = 2048;
pub const FCG1_PERIPH_I2S1: u32 = 4096;
pub const FCG1_PERIPH_I2S2: u32 = 8192;
pub const FCG1_PERIPH_I2S3: u32 = 16384;
pub const FCG1_PERIPH_I2S4: u32 = 32768;
pub const FCG1_PERIPH_SPI1: u32 = 65536;
pub const FCG1_PERIPH_SPI2: u32 = 131072;
pub const FCG1_PERIPH_SPI3: u32 = 262144;
pub const FCG1_PERIPH_SPI4: u32 = 524288;
pub const FCG1_PERIPH_USART1: u32 = 16777216;
pub const FCG1_PERIPH_USART2: u32 = 33554432;
pub const FCG1_PERIPH_USART3: u32 = 67108864;
pub const FCG1_PERIPH_USART4: u32 = 134217728;
pub const FCG2_PERIPH_TMR0_1: u32 = 1;
pub const FCG2_PERIPH_TMR0_2: u32 = 2;
pub const FCG2_PERIPH_TMRA_1: u32 = 4;
pub const FCG2_PERIPH_TMRA_2: u32 = 8;
pub const FCG2_PERIPH_TMRA_3: u32 = 16;
pub const FCG2_PERIPH_TMRA_4: u32 = 32;
pub const FCG2_PERIPH_TMRA_5: u32 = 64;
pub const FCG2_PERIPH_TMRA_6: u32 = 128;
pub const FCG2_PERIPH_TMR4_1: u32 = 256;
pub const FCG2_PERIPH_TMR4_2: u32 = 512;
pub const FCG2_PERIPH_TMR4_3: u32 = 1024;
pub const FCG2_PERIPH_EMB: u32 = 32768;
pub const FCG2_PERIPH_TMR6_1: u32 = 65536;
pub const FCG2_PERIPH_TMR6_2: u32 = 131072;
pub const FCG2_PERIPH_TMR6_3: u32 = 262144;
pub const FCG3_PERIPH_ADC1: u32 = 1;
pub const FCG3_PERIPH_ADC2: u32 = 2;
pub const FCG3_PERIPH_CMP: u32 = 256;
pub const FCG3_PERIPH_OTS: u32 = 4096;
pub const FCG_FCG0_PERIPH_MASK: u32 = 2415117585;
pub const FCG_FCG1_PERIPH_MASK: u32 = 252706169;
pub const FCG_FCG2_PERIPH_MASK: u32 = 493567;
pub const FCG_FCG3_PERIPH_MASK: u32 = 4355;
pub const FCM_TARGET_CLK_XTAL: u32 = 0;
pub const FCM_TARGET_CLK_XTAL32: u32 = 16;
pub const FCM_TARGET_CLK_HRC: u32 = 32;
pub const FCM_TARGET_CLK_LRC: u32 = 48;
pub const FCM_TARGET_CLK_SWDTLRC: u32 = 64;
pub const FCM_TARGET_CLK_PCLK1: u32 = 80;
pub const FCM_TARGET_CLK_UPLLP: u32 = 96;
pub const FCM_TARGET_CLK_MRC: u32 = 112;
pub const FCM_TARGET_CLK_MPLLP: u32 = 128;
pub const FCM_TARGET_CLK_DIV1: u32 = 0;
pub const FCM_TARGET_CLK_DIV4: u32 = 1;
pub const FCM_TARGET_CLK_DIV8: u32 = 2;
pub const FCM_TARGET_CLK_DIV32: u32 = 3;
pub const FCM_EXT_REF_OFF: u32 = 0;
pub const FCM_EXT_REF_ON: u32 = 32768;
pub const FCM_REF_CLK_RISING: u32 = 0;
pub const FCM_REF_CLK_FALLING: u32 = 4096;
pub const FCM_REF_CLK_BOTH: u32 = 8192;
pub const FCM_DIG_FILTER_OFF: u32 = 0;
pub const FCM_DIG_FILTER_DIV1: u32 = 256;
pub const FCM_DIG_FILTER_DIV4: u32 = 512;
pub const FCM_DIG_FILTER_DIV16: u32 = 768;
pub const FCM_REF_CLK_EXTCLK: u32 = 0;
pub const FCM_REF_CLK_XTAL: u32 = 128;
pub const FCM_REF_CLK_XTAL32: u32 = 136;
pub const FCM_REF_CLK_HRC: u32 = 144;
pub const FCM_REF_CLK_LRC: u32 = 152;
pub const FCM_REF_CLK_SWDTLRC: u32 = 160;
pub const FCM_REF_CLK_PCLK1: u32 = 168;
pub const FCM_REF_CLK_UPLLP: u32 = 176;
pub const FCM_REF_CLK_MRC: u32 = 184;
pub const FCM_REF_CLK_MPLLP: u32 = 192;
pub const FCM_REF_CLK_DIV32: u32 = 0;
pub const FCM_REF_CLK_DIV128: u32 = 1;
pub const FCM_REF_CLK_DIV1024: u32 = 2;
pub const FCM_REF_CLK_DIV8192: u32 = 3;
pub const FCM_ERR_RST_OFF: u32 = 0;
pub const FCM_ERR_RST_ON: u32 = 128;
pub const FCM_EXP_TYPE_INT: u32 = 0;
pub const FCM_EXP_TYPE_RST: u32 = 16;
pub const FCM_INT_OVF: u32 = 4;
pub const FCM_INT_END: u32 = 2;
pub const FCM_INT_ERR: u32 = 1;
pub const FCM_FLAG_ERR: u32 = 1;
pub const FCM_FLAG_END: u32 = 2;
pub const FCM_FLAG_OVF: u32 = 4;
pub const GPIO_PIN_00: u32 = 1;
pub const GPIO_PIN_01: u32 = 2;
pub const GPIO_PIN_02: u32 = 4;
pub const GPIO_PIN_03: u32 = 8;
pub const GPIO_PIN_04: u32 = 16;
pub const GPIO_PIN_05: u32 = 32;
pub const GPIO_PIN_06: u32 = 64;
pub const GPIO_PIN_07: u32 = 128;
pub const GPIO_PIN_08: u32 = 256;
pub const GPIO_PIN_09: u32 = 512;
pub const GPIO_PIN_10: u32 = 1024;
pub const GPIO_PIN_11: u32 = 2048;
pub const GPIO_PIN_12: u32 = 4096;
pub const GPIO_PIN_13: u32 = 8192;
pub const GPIO_PIN_14: u32 = 16384;
pub const GPIO_PIN_15: u32 = 32768;
pub const GPIO_PIN_ALL: u32 = 65535;
pub const GPIO_PIN_A_ALL: u32 = 65535;
pub const GPIO_PIN_B_ALL: u32 = 65535;
pub const GPIO_PIN_C_ALL: u32 = 65535;
pub const GPIO_PIN_D_ALL: u32 = 65535;
pub const GPIO_PIN_E_ALL: u32 = 65535;
pub const GPIO_PIN_H_ALL: u32 = 7;
pub const GPIO_PORT_A: u32 = 0;
pub const GPIO_PORT_B: u32 = 1;
pub const GPIO_PORT_C: u32 = 2;
pub const GPIO_PORT_D: u32 = 3;
pub const GPIO_PORT_E: u32 = 4;
pub const GPIO_PORT_H: u32 = 5;
pub const GPIO_FUNC_0: u32 = 0;
pub const GPIO_FUNC_1: u32 = 1;
pub const GPIO_FUNC_2: u32 = 2;
pub const GPIO_FUNC_3: u32 = 3;
pub const GPIO_FUNC_4: u32 = 4;
pub const GPIO_FUNC_5: u32 = 5;
pub const GPIO_FUNC_6: u32 = 6;
pub const GPIO_FUNC_7: u32 = 7;
pub const GPIO_FUNC_8: u32 = 8;
pub const GPIO_FUNC_9: u32 = 9;
pub const GPIO_FUNC_10: u32 = 10;
pub const GPIO_FUNC_11: u32 = 11;
pub const GPIO_FUNC_12: u32 = 12;
pub const GPIO_FUNC_13: u32 = 13;
pub const GPIO_FUNC_14: u32 = 14;
pub const GPIO_FUNC_15: u32 = 15;
pub const GPIO_FUNC_32: u32 = 32;
pub const GPIO_FUNC_33: u32 = 33;
pub const GPIO_FUNC_34: u32 = 34;
pub const GPIO_FUNC_35: u32 = 35;
pub const GPIO_FUNC_36: u32 = 36;
pub const GPIO_FUNC_37: u32 = 37;
pub const GPIO_FUNC_38: u32 = 38;
pub const GPIO_FUNC_39: u32 = 39;
pub const GPIO_FUNC_40: u32 = 40;
pub const GPIO_FUNC_41: u32 = 41;
pub const GPIO_FUNC_42: u32 = 42;
pub const GPIO_FUNC_43: u32 = 43;
pub const GPIO_FUNC_44: u32 = 44;
pub const GPIO_FUNC_45: u32 = 45;
pub const GPIO_FUNC_46: u32 = 46;
pub const GPIO_FUNC_47: u32 = 47;
pub const GPIO_FUNC_48: u32 = 48;
pub const GPIO_FUNC_49: u32 = 49;
pub const GPIO_FUNC_50: u32 = 50;
pub const GPIO_FUNC_51: u32 = 51;
pub const GPIO_FUNC_52: u32 = 52;
pub const GPIO_FUNC_53: u32 = 53;
pub const GPIO_FUNC_54: u32 = 54;
pub const GPIO_FUNC_55: u32 = 55;
pub const GPIO_FUNC_56: u32 = 56;
pub const GPIO_FUNC_57: u32 = 57;
pub const GPIO_FUNC_58: u32 = 58;
pub const GPIO_FUNC_59: u32 = 59;
pub const GPIO_PIN_TCK: u32 = 1;
pub const GPIO_PIN_TMS: u32 = 2;
pub const GPIO_PIN_TDO: u32 = 4;
pub const GPIO_PIN_TDI: u32 = 8;
pub const GPIO_PIN_TRST: u32 = 16;
pub const GPIO_PIN_DEBUG_JTAG: u32 = 31;
pub const GPIO_PIN_SWCLK: u32 = 1;
pub const GPIO_PIN_SWDIO: u32 = 2;
pub const GPIO_PIN_SWO: u32 = 4;
pub const GPIO_PIN_DEBUG_SWD: u32 = 7;
pub const GPIO_PIN_DEBUG: u32 = 31;
pub const GPIO_RD_WAIT0: u32 = 0;
pub const GPIO_RD_WAIT1: u32 = 16384;
pub const GPIO_RD_WAIT2: u32 = 32768;
pub const GPIO_RD_WAIT3: u32 = 49152;
pub const PIN_STAT_RST: u32 = 0;
pub const PIN_STAT_SET: u32 = 1;
pub const PIN_DIR_IN: u32 = 0;
pub const PIN_DIR_OUT: u32 = 2;
pub const PIN_OUT_TYPE_CMOS: u32 = 0;
pub const PIN_OUT_TYPE_NMOS: u32 = 4;
pub const PIN_LOW_DRV: u32 = 0;
pub const PIN_MID_DRV: u32 = 16;
pub const PIN_HIGH_DRV: u32 = 32;
pub const PIN_LATCH_OFF: u32 = 0;
pub const PIN_LATCH_ON: u32 = 16384;
pub const PIN_PU_OFF: u32 = 0;
pub const PIN_PU_ON: u32 = 64;
pub const PIN_INVT_OFF: u32 = 0;
pub const PIN_INVT_ON: u32 = 512;
pub const PIN_EXTINT_OFF: u32 = 0;
pub const PIN_EXTINT_ON: u32 = 4096;
pub const PIN_ATTR_DIGITAL: u32 = 0;
pub const PIN_ATTR_ANALOG: u32 = 32768;
pub const PIN_SUBFUNC_DISABLE: u32 = 0;
pub const PIN_SUBFUNC_ENABLE: u32 = 256;
pub const GPIO_REG_LOCK_KEY: u32 = 42240;
pub const GPIO_REG_UNLOCK_KEY: u32 = 42241;
pub const I2C_WIDTH_MAX_IMME: u32 = 68;
pub const I2C_DIR_TX: u32 = 0;
pub const I2C_DIR_RX: u32 = 1;
pub const I2C_ADDR_DISABLE: u32 = 0;
pub const I2C_ADDR_7BIT: u32 = 4096;
pub const I2C_ADDR_10BIT: u32 = 36864;
pub const I2C_CLK_DIV1: u32 = 0;
pub const I2C_CLK_DIV2: u32 = 1;
pub const I2C_CLK_DIV4: u32 = 2;
pub const I2C_CLK_DIV8: u32 = 3;
pub const I2C_CLK_DIV16: u32 = 4;
pub const I2C_CLK_DIV32: u32 = 5;
pub const I2C_CLK_DIV64: u32 = 6;
pub const I2C_CLK_DIV128: u32 = 7;
pub const I2C_ADDR0: u32 = 0;
pub const I2C_ADDR1: u32 = 1;
pub const I2C_ACK: u32 = 0;
pub const I2C_NACK: u32 = 1024;
pub const I2C_SMBUS_MATCH_ALERT: u32 = 4;
pub const I2C_SMBUS_MATCH_DEFAULT: u32 = 8;
pub const I2C_SMBUS_MATCH_HOST: u32 = 16;
pub const I2C_SMBUS_MATCH_ALL: u32 = 28;
pub const I2C_DIG_FILTER_CLK_DIV1: u32 = 0;
pub const I2C_DIG_FILTER_CLK_DIV2: u32 = 1;
pub const I2C_DIG_FILTER_CLK_DIV3: u32 = 2;
pub const I2C_DIG_FILTER_CLK_DIV4: u32 = 3;
pub const I2C_FLAG_START: u32 = 1;
pub const I2C_FLAG_MATCH_ADDR0: u32 = 2;
pub const I2C_FLAG_MATCH_ADDR1: u32 = 4;
pub const I2C_FLAG_TX_CPLT: u32 = 8;
pub const I2C_FLAG_STOP: u32 = 16;
pub const I2C_FLAG_RX_FULL: u32 = 64;
pub const I2C_FLAG_TX_EMPTY: u32 = 128;
pub const I2C_FLAG_ARBITRATE_FAIL: u32 = 512;
pub const I2C_FLAG_ACKR: u32 = 1024;
pub const I2C_FLAG_NACKF: u32 = 4096;
pub const I2C_FLAG_TMOUTF: u32 = 16384;
pub const I2C_FLAG_MASTER: u32 = 65536;
pub const I2C_FLAG_BUSY: u32 = 131072;
pub const I2C_FLAG_TRA: u32 = 262144;
pub const I2C_FLAG_GENERAL_CALL: u32 = 1048576;
pub const I2C_FLAG_SMBUS_DEFAULT_MATCH: u32 = 2097152;
pub const I2C_FLAG_SMBUS_HOST_MATCH: u32 = 4194304;
pub const I2C_FLAG_SMBUS_ALERT_MATCH: u32 = 8388608;
pub const I2C_FLAG_ALL: u32 = 16209631;
pub const I2C_FLAG_CLR_START: u32 = 1;
pub const I2C_FLAG_CLR_MATCH_ADDR0: u32 = 2;
pub const I2C_FLAG_CLR_MATCH_ADDR1: u32 = 4;
pub const I2C_FLAG_CLR_TX_CPLT: u32 = 8;
pub const I2C_FLAG_CLR_STOP: u32 = 16;
pub const I2C_FLAG_CLR_RX_FULL: u32 = 64;
pub const I2C_FLAG_CLR_ARBITRATE_FAIL: u32 = 512;
pub const I2C_FLAG_CLR_NACK: u32 = 4096;
pub const I2C_FLAG_CLR_TMOUTF: u32 = 16384;
pub const I2C_FLAG_CLR_GENERAL_CALL: u32 = 1048576;
pub const I2C_FLAG_CLR_SMBUS_DEFAULT_MATCH: u32 = 2097152;
pub const I2C_FLAG_CLR_SMBUS_HOST_MATCH: u32 = 4194304;
pub const I2C_FLAG_CLR_SMBUS_ALERT_MATCH: u32 = 8388608;
pub const I2C_FLAG_CLR_ALL: u32 = 15749727;
pub const I2C_INT_START: u32 = 1;
pub const I2C_INT_MATCH_ADDR0: u32 = 2;
pub const I2C_INT_MATCH_ADDR1: u32 = 4;
pub const I2C_INT_TX_CPLT: u32 = 8;
pub const I2C_INT_STOP: u32 = 16;
pub const I2C_INT_RX_FULL: u32 = 64;
pub const I2C_INT_TX_EMPTY: u32 = 128;
pub const I2C_INT_ARBITRATE_FAIL: u32 = 512;
pub const I2C_INT_NACK: u32 = 4096;
pub const I2C_INT_TMOUTIE: u32 = 16384;
pub const I2C_INT_GENERAL_CALL: u32 = 1048576;
pub const I2C_INT_SMBUS_DEFAULT_MATCH: u32 = 2097152;
pub const I2C_INT_SMBUS_HOST_MATCH: u32 = 4194304;
pub const I2C_INT_SMBUS_ALERT_MATCH: u32 = 8388608;
pub const I2C_INT_ALL: u32 = 15749855;
pub const I2S_EXT_CLK_FREQ: u32 = 12288000;
pub const I2S_CLK_SRC_PLL: u32 = 262144;
pub const I2S_CLK_SRC_EXT: u32 = 8388608;
pub const I2S_MD_MASTER: u32 = 0;
pub const I2S_MD_SLAVE: u32 = 32;
pub const I2S_PROTOCOL_PHILLIPS: u32 = 0;
pub const I2S_PROTOCOL_MSB: u32 = 1;
pub const I2S_PROTOCOL_LSB: u32 = 2;
pub const I2S_PROTOCOL_PCM_SHORT: u32 = 3;
pub const I2S_PROTOCOL_PCM_LONG: u32 = 35;
pub const I2S_TRANS_MD_HALF_DUPLEX_RX: u32 = 0;
pub const I2S_TRANS_MD_HALF_DUPLEX_TX: u32 = 524288;
pub const I2S_TRANS_MD_FULL_DUPLEX: u32 = 4718592;
pub const I2S_AUDIO_FREQ_192K: u32 = 192000;
pub const I2S_AUDIO_FREQ_96K: u32 = 96000;
pub const I2S_AUDIO_FREQ_48K: u32 = 48000;
pub const I2S_AUDIO_FREQ_44K: u32 = 44100;
pub const I2S_AUDIO_FREQ_32K: u32 = 32000;
pub const I2S_AUDIO_FREQ_22K: u32 = 22050;
pub const I2S_AUDIO_FREQ_16K: u32 = 16000;
pub const I2S_AUDIO_FREQ_8K: u32 = 8000;
pub const I2S_AUDIO_FREQ_DEFAULT: u32 = 2;
pub const I2S_CH_LEN_16BIT: u32 = 0;
pub const I2S_CH_LEN_32BIT: u32 = 16;
pub const I2S_DATA_LEN_16BIT: u32 = 0;
pub const I2S_DATA_LEN_24BIT: u32 = 4;
pub const I2S_DATA_LEN_32BIT: u32 = 8;
pub const I2S_MCK_OUTPUT_DISABLE: u32 = 0;
pub const I2S_MCK_OUTPUT_ENABLE: u32 = 128;
pub const I2S_TRANS_LVL0: u32 = 0;
pub const I2S_TRANS_LVL1: u32 = 256;
pub const I2S_TRANS_LVL2: u32 = 512;
pub const I2S_RECEIVE_LVL0: u32 = 0;
pub const I2S_RECEIVE_LVL1: u32 = 4096;
pub const I2S_RECEIVE_LVL2: u32 = 8192;
pub const I2S_FUNC_TX: u32 = 1;
pub const I2S_FUNC_RX: u32 = 4;
pub const I2S_FUNC_ALL: u32 = 5;
pub const I2S_RST_TYPE_FIFO: u32 = 65536;
pub const I2S_RST_TYPE_ALL: u32 = 65536;
pub const I2S_INT_TX: u32 = 2;
pub const I2S_INT_RX: u32 = 8;
pub const I2S_INT_ERR: u32 = 16;
pub const I2S_INT_ALL: u32 = 26;
pub const I2S_FLAG_TX_ALARM: u32 = 1;
pub const I2S_FLAG_RX_ALARM: u32 = 2;
pub const I2S_FLAG_TX_EMPTY: u32 = 4;
pub const I2S_FLAG_TX_FULL: u32 = 8;
pub const I2S_FLAG_RX_EMPTY: u32 = 16;
pub const I2S_FLAG_RX_FULL: u32 = 32;
pub const I2S_FLAG_TX_ERR: u32 = 65536;
pub const I2S_FLAG_RX_ERR: u32 = 131072;
pub const I2S_FLAG_ALL: u32 = 196671;
pub const I2S_FLAG_CLR_ALL: u32 = 196608;
pub const ICG_SWDT_RST_START: u32 = 0;
pub const ICG_SWDT_RST_STOP: u32 = 1;
pub const ICG_SWDT_EXP_TYPE_INT: u32 = 0;
pub const ICG_SWDT_EXP_TYPE_RST: u32 = 2;
pub const ICG_SWDT_CNT_PERIOD256: u32 = 0;
pub const ICG_SWDT_CNT_PERIOD4096: u32 = 4;
pub const ICG_SWDT_CNT_PERIOD16384: u32 = 8;
pub const ICG_SWDT_CNT_PERIOD65536: u32 = 12;
pub const ICG_SWDT_CLK_DIV1: u32 = 0;
pub const ICG_SWDT_CLK_DIV16: u32 = 64;
pub const ICG_SWDT_CLK_DIV32: u32 = 80;
pub const ICG_SWDT_CLK_DIV64: u32 = 96;
pub const ICG_SWDT_CLK_DIV128: u32 = 112;
pub const ICG_SWDT_CLK_DIV256: u32 = 128;
pub const ICG_SWDT_CLK_DIV2048: u32 = 176;
pub const ICG_SWDT_RANGE_0TO25PCT: u32 = 256;
pub const ICG_SWDT_RANGE_25TO50PCT: u32 = 512;
pub const ICG_SWDT_RANGE_0TO50PCT: u32 = 768;
pub const ICG_SWDT_RANGE_50TO75PCT: u32 = 1024;
pub const ICG_SWDT_RANGE_0TO25PCT_50TO75PCT: u32 = 1280;
pub const ICG_SWDT_RANGE_25TO75PCT: u32 = 1536;
pub const ICG_SWDT_RANGE_0TO75PCT: u32 = 1792;
pub const ICG_SWDT_RANGE_75TO100PCT: u32 = 2048;
pub const ICG_SWDT_RANGE_0TO25PCT_75TO100PCT: u32 = 2304;
pub const ICG_SWDT_RANGE_25TO50PCT_75TO100PCT: u32 = 2560;
pub const ICG_SWDT_RANGE_0TO50PCT_75TO100PCT: u32 = 2816;
pub const ICG_SWDT_RANGE_50TO100PCT: u32 = 3072;
pub const ICG_SWDT_RANGE_0TO25PCT_50TO100PCT: u32 = 3328;
pub const ICG_SWDT_RANGE_25TO100PCT: u32 = 3584;
pub const ICG_SWDT_RANGE_0TO100PCT: u32 = 3840;
pub const ICG_SWDT_LPM_CNT_CONT: u32 = 0;
pub const ICG_SWDT_LPM_CNT_STOP: u32 = 4096;
pub const ICG_WDT_RST_START: u32 = 0;
pub const ICG_WDT_RST_STOP: u32 = 65536;
pub const ICG_WDT_EXP_TYPE_INT: u32 = 0;
pub const ICG_WDT_EXP_TYPE_RST: u32 = 131072;
pub const REDEF_ICG_WDTPERI_POS: u32 = 18;
pub const ICG_WDT_CNT_PERIOD256: u32 = 0;
pub const ICG_WDT_CNT_PERIOD4096: u32 = 262144;
pub const ICG_WDT_CNT_PERIOD16384: u32 = 524288;
pub const ICG_WDT_CNT_PERIOD65536: u32 = 786432;
pub const REDEF_ICG_WDTCKS_POS: u32 = 20;
pub const ICG_WDT_CLK_DIV4: u32 = 2097152;
pub const ICG_WDT_CLK_DIV64: u32 = 6291456;
pub const ICG_WDT_CLK_DIV128: u32 = 7340032;
pub const ICG_WDT_CLK_DIV256: u32 = 8388608;
pub const ICG_WDT_CLK_DIV512: u32 = 9437184;
pub const ICG_WDT_CLK_DIV1024: u32 = 10485760;
pub const ICG_WDT_CLK_DIV2048: u32 = 11534336;
pub const ICG_WDT_CLK_DIV8192: u32 = 13631488;
pub const REDEF_ICG_WDTWDPT_POS: u32 = 24;
pub const ICG_WDT_RANGE_0TO25PCT: u32 = 16777216;
pub const ICG_WDT_RANGE_25TO50PCT: u32 = 33554432;
pub const ICG_WDT_RANGE_0TO50PCT: u32 = 50331648;
pub const ICG_WDT_RANGE_50TO75PCT: u32 = 67108864;
pub const ICG_WDT_RANGE_0TO25PCT_50TO75PCT: u32 = 83886080;
pub const ICG_WDT_RANGE_25TO75PCT: u32 = 100663296;
pub const ICG_WDT_RANGE_0TO75PCT: u32 = 117440512;
pub const ICG_WDT_RANGE_75TO100PCT: u32 = 134217728;
pub const ICG_WDT_RANGE_0TO25PCT_75TO100PCT: u32 = 150994944;
pub const ICG_WDT_RANGE_25TO50PCT_75TO100PCT: u32 = 167772160;
pub const ICG_WDT_RANGE_0TO50PCT_75TO100PCT: u32 = 184549376;
pub const ICG_WDT_RANGE_50TO100PCT: u32 = 201326592;
pub const ICG_WDT_RANGE_0TO25PCT_50TO100PCT: u32 = 218103808;
pub const ICG_WDT_RANGE_25TO100PCT: u32 = 234881024;
pub const ICG_WDT_RANGE_0TO100PCT: u32 = 251658240;
pub const ICG_WDT_LPM_CNT_CONT: u32 = 0;
pub const ICG_WDT_LPM_CNT_STOP: u32 = 268435456;
pub const REDEF_ICG_NMIFCLK_POS: u32 = 26;
pub const ICG_NMI_PIN_FILTER_CLK_DIV1: u32 = 0;
pub const ICG_NMI_PIN_FILTER_CLK_DIV8: u32 = 67108864;
pub const ICG_NMI_PIN_FILTER_CLK_DIV32: u32 = 134217728;
pub const ICG_NMI_PIN_FILTER_CLK_DIV64: u32 = 201326592;
pub const ICG_NMI_PIN_FILTER_DISABLE: u32 = 0;
pub const ICG_NMI_PIN_FILTER_ENABLE: u32 = 1073741824;
pub const ICG_NMI_PIN_TRIG_EDGE_FALLING: u32 = 0;
pub const ICG_NMI_PIN_TRIG_EDGE_RISING: u32 = 268435456;
pub const ICG_NMI_PIN_INT_DISABLE: u32 = 0;
pub const ICG_NMI_PIN_INT_ENABLE: u32 = 536870912;
pub const ICG_NMI_PIN_RST_ENABLE: u32 = 0;
pub const ICG_NMI_PIN_RST_DISABLE: u32 = 2147483648;
pub const ICG_BOR_VOL_THRESHOLD_LVL0: u32 = 0;
pub const ICG_BOR_VOL_THRESHOLD_LVL1: u32 = 65536;
pub const ICG_BOR_VOL_THRESHOLD_LVL2: u32 = 131072;
pub const ICG_BOR_VOL_THRESHOLD_LVL3: u32 = 196608;
pub const ICG_BOR_RST_ENABLE: u32 = 0;
pub const ICG_BOR_RST_DISABLE: u32 = 262144;
pub const ICG_HRC_20M: u32 = 0;
pub const ICG_HRC_16M: u32 = 1;
pub const ICG_HRC_RST_OSCILLATION: u32 = 0;
pub const ICG_HRC_RST_STOP: u32 = 256;
pub const ICG_RB_SWDT_AUTS: u32 = 1;
pub const ICG_RB_SWDT_ITS: u32 = 2;
pub const ICG_RB_SWDT_PERI: u32 = 12;
pub const ICG_RB_SWDT_CKS: u32 = 176;
pub const ICG_RB_SWDT_WDPT: u32 = 3840;
pub const ICG_RB_SWDT_SLTPOFF: u32 = 4096;
pub const ICG_REG_SWDT_CONFIG: u32 = 8127;
pub const ICG_RB_WDT_AUTS: u32 = 65536;
pub const ICG_RB_WDT_ITS: u32 = 131072;
pub const ICG_RB_WDT_PERI: u32 = 786432;
pub const ICG_RB_WDT_CKS: u32 = 13631488;
pub const ICG_RB_WDT_WDPT: u32 = 251658240;
pub const ICG_RB_WDT_SLTPOFF: u32 = 268435456;
pub const ICG_REG_WDT_CONFIG: u32 = 534708224;
pub const ICG_RB_NMI_FCLK: u32 = 201326592;
pub const ICG_RB_NMI_FEN: u32 = 1073741824;
pub const ICG_RB_NMI_TRG: u32 = 268435456;
pub const ICG_RB_NMI_EN: u32 = 536870912;
pub const ICG_RB_NMI_ICGEN: u32 = 2147483648;
pub const ICG_REG_NMI_CONFIG: u32 = 4227858432;
pub const ICG_RB_BOR_LEV: u32 = 196608;
pub const ICG_RB_BOR_DIS: u32 = 262144;
pub const ICG_REG_BOR_CONFIG: u32 = 458752;
pub const ICG_RB_HRC_FREQSEL: u32 = 1;
pub const ICG_RB_HRC_STOP: u32 = 0;
pub const ICG_REG_HRC_CONFIG: u32 = 1;
pub const ICG_REG_CFG0_CONST: u32 = 4292870079;
pub const ICG_REG_CFG1_CONST: u32 = 4294967039;
pub const ICG_REG_RESV_CONST: u32 = 4294967295;
pub const DDL_IRQ_PRIO_00: u32 = 0;
pub const DDL_IRQ_PRIO_01: u32 = 1;
pub const DDL_IRQ_PRIO_02: u32 = 2;
pub const DDL_IRQ_PRIO_03: u32 = 3;
pub const DDL_IRQ_PRIO_04: u32 = 4;
pub const DDL_IRQ_PRIO_05: u32 = 5;
pub const DDL_IRQ_PRIO_06: u32 = 6;
pub const DDL_IRQ_PRIO_07: u32 = 7;
pub const DDL_IRQ_PRIO_08: u32 = 8;
pub const DDL_IRQ_PRIO_09: u32 = 9;
pub const DDL_IRQ_PRIO_10: u32 = 10;
pub const DDL_IRQ_PRIO_11: u32 = 11;
pub const DDL_IRQ_PRIO_12: u32 = 12;
pub const DDL_IRQ_PRIO_13: u32 = 13;
pub const DDL_IRQ_PRIO_14: u32 = 14;
pub const DDL_IRQ_PRIO_15: u32 = 15;
pub const DDL_IRQ_PRIO_DEFAULT: u32 = 15;
pub const NMI_SRC_PIN: u32 = 1;
pub const NMI_SRC_SWDT: u32 = 2;
pub const NMI_SRC_LVD1: u32 = 4;
pub const NMI_SRC_LVD2: u32 = 8;
pub const NMI_SRC_XTAL: u32 = 32;
pub const NMI_SRC_SRAM_PARITY: u32 = 256;
pub const NMI_SRC_SRAM_ECC: u32 = 512;
pub const NMI_SRC_BUS_ERR: u32 = 1024;
pub const NMI_SRC_WDT: u32 = 2048;
pub const NMI_SRC_ALL: u32 = 3887;
pub const NMI_TRIG_FALLING: u32 = 0;
pub const NMI_TRIG_RISING: u32 = 1;
pub const NMI_FILTER_OFF: u32 = 0;
pub const NMI_FILTER_ON: u32 = 128;
pub const NMI_FCLK_DIV1: u32 = 0;
pub const NMI_FCLK_DIV8: u32 = 16;
pub const NMI_FCLK_DIV32: u32 = 32;
pub const NMI_FCLK_DIV64: u32 = 48;
pub const EXTINT_CH00: u32 = 1;
pub const EXTINT_CH01: u32 = 2;
pub const EXTINT_CH02: u32 = 4;
pub const EXTINT_CH03: u32 = 8;
pub const EXTINT_CH04: u32 = 16;
pub const EXTINT_CH05: u32 = 32;
pub const EXTINT_CH06: u32 = 64;
pub const EXTINT_CH07: u32 = 128;
pub const EXTINT_CH08: u32 = 256;
pub const EXTINT_CH09: u32 = 512;
pub const EXTINT_CH10: u32 = 1024;
pub const EXTINT_CH11: u32 = 2048;
pub const EXTINT_CH12: u32 = 4096;
pub const EXTINT_CH13: u32 = 8192;
pub const EXTINT_CH14: u32 = 16384;
pub const EXTINT_CH15: u32 = 32768;
pub const EXTINT_CH_ALL: u32 = 65535;
pub const INTC_INT0: u32 = 1;
pub const INTC_INT1: u32 = 2;
pub const INTC_INT2: u32 = 4;
pub const INTC_INT3: u32 = 8;
pub const INTC_INT4: u32 = 16;
pub const INTC_INT5: u32 = 32;
pub const INTC_INT6: u32 = 64;
pub const INTC_INT7: u32 = 128;
pub const INTC_INT8: u32 = 256;
pub const INTC_INT9: u32 = 512;
pub const INTC_INT10: u32 = 1024;
pub const INTC_INT11: u32 = 2048;
pub const INTC_INT12: u32 = 4096;
pub const INTC_INT13: u32 = 8192;
pub const INTC_INT14: u32 = 16384;
pub const INTC_INT15: u32 = 32768;
pub const INTC_INT16: u32 = 65536;
pub const INTC_INT17: u32 = 131072;
pub const INTC_INT18: u32 = 262144;
pub const INTC_INT19: u32 = 524288;
pub const INTC_INT20: u32 = 1048576;
pub const INTC_INT21: u32 = 2097152;
pub const INTC_INT22: u32 = 4194304;
pub const INTC_INT23: u32 = 8388608;
pub const INTC_INT24: u32 = 16777216;
pub const INTC_INT25: u32 = 33554432;
pub const INTC_INT26: u32 = 67108864;
pub const INTC_INT27: u32 = 134217728;
pub const INTC_INT28: u32 = 268435456;
pub const INTC_INT29: u32 = 536870912;
pub const INTC_INT30: u32 = 1073741824;
pub const INTC_INT31: u32 = 2147483648;
pub const INTC_INT_ALL: u32 = 4294967295;
pub const INTC_EVT0: u32 = 1;
pub const INTC_EVT1: u32 = 2;
pub const INTC_EVT2: u32 = 4;
pub const INTC_EVT3: u32 = 8;
pub const INTC_EVT4: u32 = 16;
pub const INTC_EVT5: u32 = 32;
pub const INTC_EVT6: u32 = 64;
pub const INTC_EVT7: u32 = 128;
pub const INTC_EVT8: u32 = 256;
pub const INTC_EVT9: u32 = 512;
pub const INTC_EVT10: u32 = 1024;
pub const INTC_EVT11: u32 = 2048;
pub const INTC_EVT12: u32 = 4096;
pub const INTC_EVT13: u32 = 8192;
pub const INTC_EVT14: u32 = 16384;
pub const INTC_EVT15: u32 = 32768;
pub const INTC_EVT16: u32 = 65536;
pub const INTC_EVT17: u32 = 131072;
pub const INTC_EVT18: u32 = 262144;
pub const INTC_EVT19: u32 = 524288;
pub const INTC_EVT20: u32 = 1048576;
pub const INTC_EVT21: u32 = 2097152;
pub const INTC_EVT22: u32 = 4194304;
pub const INTC_EVT23: u32 = 8388608;
pub const INTC_EVT24: u32 = 16777216;
pub const INTC_EVT25: u32 = 33554432;
pub const INTC_EVT26: u32 = 67108864;
pub const INTC_EVT27: u32 = 134217728;
pub const INTC_EVT28: u32 = 268435456;
pub const INTC_EVT29: u32 = 536870912;
pub const INTC_EVT30: u32 = 1073741824;
pub const INTC_EVT31: u32 = 2147483648;
pub const INTC_EVT_ALL: u32 = 4294967295;
pub const SWINT_CH00: u32 = 1;
pub const SWINT_CH01: u32 = 2;
pub const SWINT_CH02: u32 = 4;
pub const SWINT_CH03: u32 = 8;
pub const SWINT_CH04: u32 = 16;
pub const SWINT_CH05: u32 = 32;
pub const SWINT_CH06: u32 = 64;
pub const SWINT_CH07: u32 = 128;
pub const SWINT_CH08: u32 = 256;
pub const SWINT_CH09: u32 = 512;
pub const SWINT_CH10: u32 = 1024;
pub const SWINT_CH11: u32 = 2048;
pub const SWINT_CH12: u32 = 4096;
pub const SWINT_CH13: u32 = 8192;
pub const SWINT_CH14: u32 = 16384;
pub const SWINT_CH15: u32 = 32768;
pub const SWINT_CH16: u32 = 65536;
pub const SWINT_CH17: u32 = 131072;
pub const SWINT_CH18: u32 = 262144;
pub const SWINT_CH19: u32 = 524288;
pub const SWINT_CH20: u32 = 1048576;
pub const SWINT_CH21: u32 = 2097152;
pub const SWINT_CH22: u32 = 4194304;
pub const SWINT_CH23: u32 = 8388608;
pub const SWINT_CH24: u32 = 16777216;
pub const SWINT_CH25: u32 = 33554432;
pub const SWINT_CH26: u32 = 67108864;
pub const SWINT_CH27: u32 = 134217728;
pub const SWINT_CH28: u32 = 268435456;
pub const SWINT_CH29: u32 = 536870912;
pub const SWINT_CH30: u32 = 1073741824;
pub const SWINT_CH31: u32 = 2147483648;
pub const SWINT_ALL: u32 = 4294967295;
pub const EXTINT_FILTER_OFF: u32 = 0;
pub const EXTINT_FILTER_ON: u32 = 128;
pub const EXTINT_FCLK_DIV1: u32 = 0;
pub const EXTINT_FCLK_DIV8: u32 = 16;
pub const EXTINT_FCLK_DIV32: u32 = 32;
pub const EXTINT_FCLK_DIV64: u32 = 48;
pub const EXTINT_TRIG_FALLING: u32 = 0;
pub const EXTINT_TRIG_RISING: u32 = 1;
pub const EXTINT_TRIG_BOTH: u32 = 2;
pub const EXTINT_TRIG_LOW: u32 = 3;
pub const INTC_STOP_WKUP_EXTINT_CH0: u32 = 1;
pub const INTC_STOP_WKUP_EXTINT_CH1: u32 = 2;
pub const INTC_STOP_WKUP_EXTINT_CH2: u32 = 4;
pub const INTC_STOP_WKUP_EXTINT_CH3: u32 = 8;
pub const INTC_STOP_WKUP_EXTINT_CH4: u32 = 16;
pub const INTC_STOP_WKUP_EXTINT_CH5: u32 = 32;
pub const INTC_STOP_WKUP_EXTINT_CH6: u32 = 64;
pub const INTC_STOP_WKUP_EXTINT_CH7: u32 = 128;
pub const INTC_STOP_WKUP_EXTINT_CH8: u32 = 256;
pub const INTC_STOP_WKUP_EXTINT_CH9: u32 = 512;
pub const INTC_STOP_WKUP_EXTINT_CH10: u32 = 1024;
pub const INTC_STOP_WKUP_EXTINT_CH11: u32 = 2048;
pub const INTC_STOP_WKUP_EXTINT_CH12: u32 = 4096;
pub const INTC_STOP_WKUP_EXTINT_CH13: u32 = 8192;
pub const INTC_STOP_WKUP_EXTINT_CH14: u32 = 16384;
pub const INTC_STOP_WKUP_EXTINT_CH15: u32 = 32768;
pub const INTC_STOP_WKUP_SWDT: u32 = 65536;
pub const INTC_STOP_WKUP_LVD1: u32 = 131072;
pub const INTC_STOP_WKUP_LVD2: u32 = 262144;
pub const INTC_STOP_WKUP_CMP: u32 = 524288;
pub const INTC_STOP_WKUP_WKTM: u32 = 1048576;
pub const INTC_STOP_WKUP_RTC_ALM: u32 = 2097152;
pub const INTC_STOP_WKUP_RTC_PRD: u32 = 4194304;
pub const INTC_STOP_WKUP_TMR0_CMP: u32 = 8388608;
pub const INTC_STOP_WKUP_USART1_RX: u32 = 33554432;
pub const INTC_WUPEN_ALL: u32 = 50331647;
pub const KEYSCAN_HIZ_CYCLE_4: u32 = 0;
pub const KEYSCAN_HIZ_CYCLE_8: u32 = 536870912;
pub const KEYSCAN_HIZ_CYCLE_16: u32 = 1073741824;
pub const KEYSCAN_HIZ_CYCLE_32: u32 = 1610612736;
pub const KEYSCAN_HIZ_CYCLE_64: u32 = 2147483648;
pub const KEYSCAN_HIZ_CYCLE_256: u32 = 2684354560;
pub const KEYSCAN_HIZ_CYCLE_512: u32 = 3221225472;
pub const KEYSCAN_HIZ_CYCLE_1024: u32 = 3758096384;
pub const KEYSCAN_LOW_CYCLE_4: u32 = 33554432;
pub const KEYSCAN_LOW_CYCLE_8: u32 = 50331648;
pub const KEYSCAN_LOW_CYCLE_16: u32 = 67108864;
pub const KEYSCAN_LOW_CYCLE_32: u32 = 83886080;
pub const KEYSCAN_LOW_CYCLE_64: u32 = 100663296;
pub const KEYSCAN_LOW_CYCLE_128: u32 = 117440512;
pub const KEYSCAN_LOW_CYCLE_256: u32 = 134217728;
pub const KEYSCAN_LOW_CYCLE_512: u32 = 150994944;
pub const KEYSCAN_LOW_CYCLE_1K: u32 = 167772160;
pub const KEYSCAN_LOW_CYCLE_2K: u32 = 184549376;
pub const KEYSCAN_LOW_CYCLE_4K: u32 = 201326592;
pub const KEYSCAN_LOW_CYCLE_8K: u32 = 218103808;
pub const KEYSCAN_LOW_CYCLE_16K: u32 = 234881024;
pub const KEYSCAN_LOW_CYCLE_32K: u32 = 251658240;
pub const KEYSCAN_LOW_CYCLE_64K: u32 = 268435456;
pub const KEYSCAN_LOW_CYCLE_128K: u32 = 285212672;
pub const KEYSCAN_LOW_CYCLE_256K: u32 = 301989888;
pub const KEYSCAN_LOW_CYCLE_512K: u32 = 318767104;
pub const KEYSCAN_LOW_CYCLE_1M: u32 = 335544320;
pub const KEYSCAN_LOW_CYCLE_2M: u32 = 352321536;
pub const KEYSCAN_LOW_CYCLE_4M: u32 = 369098752;
pub const KEYSCAN_LOW_CYCLE_8M: u32 = 385875968;
pub const KEYSCAN_LOW_CYCLE_16M: u32 = 402653184;
pub const KEYSCAN_CLK_HCLK: u32 = 0;
pub const KEYSCAN_CLK_LRC: u32 = 1048576;
pub const KEYSCAN_CLK_XTAL32: u32 = 2097152;
pub const KEYSCAN_OUT_0T1: u32 = 65536;
pub const KEYSCAN_OUT_0T2: u32 = 131072;
pub const KEYSCAN_OUT_0T3: u32 = 196608;
pub const KEYSCAN_OUT_0T4: u32 = 262144;
pub const KEYSCAN_OUT_0T5: u32 = 327680;
pub const KEYSCAN_OUT_0T6: u32 = 393216;
pub const KEYSCAN_OUT_0T7: u32 = 458752;
pub const KEYSCAN_IN_0: u32 = 1;
pub const KEYSCAN_IN_1: u32 = 2;
pub const KEYSCAN_IN_2: u32 = 4;
pub const KEYSCAN_IN_3: u32 = 8;
pub const KEYSCAN_IN_4: u32 = 16;
pub const KEYSCAN_IN_5: u32 = 32;
pub const KEYSCAN_IN_6: u32 = 64;
pub const KEYSCAN_IN_7: u32 = 128;
pub const KEYSCAN_IN_8: u32 = 256;
pub const KEYSCAN_IN_9: u32 = 512;
pub const KEYSCAN_IN_10: u32 = 1024;
pub const KEYSCAN_IN_11: u32 = 2048;
pub const KEYSCAN_IN_12: u32 = 4096;
pub const KEYSCAN_IN_13: u32 = 8192;
pub const KEYSCAN_IN_14: u32 = 16384;
pub const KEYSCAN_IN_15: u32 = 32768;
pub const KEYSCAN_IN_ALL: u32 = 65535;
pub const MPU_UNIT_DMA2: u32 = 1;
pub const MPU_UNIT_DMA1: u32 = 2;
pub const MPU_UNIT_USBFS_DMA: u32 = 4;
pub const MPU_UNIT_ALL: u32 = 7;
pub const MPU_REGION_NUM0: u32 = 0;
pub const MPU_REGION_NUM1: u32 = 1;
pub const MPU_REGION_NUM2: u32 = 2;
pub const MPU_REGION_NUM3: u32 = 3;
pub const MPU_REGION_NUM4: u32 = 4;
pub const MPU_REGION_NUM5: u32 = 5;
pub const MPU_REGION_NUM6: u32 = 6;
pub const MPU_REGION_NUM7: u32 = 7;
pub const MPU_REGION_NUM8: u32 = 8;
pub const MPU_REGION_NUM9: u32 = 9;
pub const MPU_REGION_NUM10: u32 = 10;
pub const MPU_REGION_NUM11: u32 = 11;
pub const MPU_REGION_NUM12: u32 = 12;
pub const MPU_REGION_NUM13: u32 = 13;
pub const MPU_REGION_NUM14: u32 = 14;
pub const MPU_REGION_NUM15: u32 = 15;
pub const MPU_BACKGROUND_WR_DISABLE: u32 = 2;
pub const MPU_BACKGROUND_WR_ENABLE: u32 = 0;
pub const MPU_BACKGROUND_RD_DISABLE: u32 = 1;
pub const MPU_BACKGROUND_RD_ENABLE: u32 = 0;
pub const MPU_UNIT_DISABLE: u32 = 0;
pub const MPU_EXP_TYPE_NONE: u32 = 0;
pub const MPU_EXP_TYPE_BUS_ERR: u32 = 4;
pub const MPU_EXP_TYPE_NMI: u32 = 8;
pub const MPU_EXP_TYPE_RST: u32 = 12;
pub const MPU_REGION_WR_DISABLE: u32 = 2;
pub const MPU_REGION_WR_ENABLE: u32 = 0;
pub const MPU_REGION_RD_DISABLE: u32 = 1;
pub const MPU_REGION_RD_ENABLE: u32 = 0;
pub const MPU_REGION_SIZE_32BYTE: u32 = 4;
pub const MPU_REGION_SIZE_64BYTE: u32 = 5;
pub const MPU_REGION_SIZE_128BYTE: u32 = 6;
pub const MPU_REGION_SIZE_256BYTE: u32 = 7;
pub const MPU_REGION_SIZE_512BYTE: u32 = 8;
pub const MPU_REGION_SIZE_1KBYTE: u32 = 9;
pub const MPU_REGION_SIZE_2KBYTE: u32 = 10;
pub const MPU_REGION_SIZE_4KBYTE: u32 = 11;
pub const MPU_REGION_SIZE_8KBYTE: u32 = 12;
pub const MPU_REGION_SIZE_16KBYTE: u32 = 13;
pub const MPU_REGION_SIZE_32KBYTE: u32 = 14;
pub const MPU_REGION_SIZE_64KBYTE: u32 = 15;
pub const MPU_REGION_SIZE_128KBYTE: u32 = 16;
pub const MPU_REGION_SIZE_256KBYTE: u32 = 17;
pub const MPU_REGION_SIZE_512KBYTE: u32 = 18;
pub const MPU_REGION_SIZE_1MBYTE: u32 = 19;
pub const MPU_REGION_SIZE_2MBYTE: u32 = 20;
pub const MPU_REGION_SIZE_4MBYTE: u32 = 21;
pub const MPU_REGION_SIZE_8MBYTE: u32 = 22;
pub const MPU_REGION_SIZE_16MBYTE: u32 = 23;
pub const MPU_REGION_SIZE_32MBYTE: u32 = 24;
pub const MPU_REGION_SIZE_64MBYTE: u32 = 25;
pub const MPU_REGION_SIZE_128MBYTE: u32 = 26;
pub const MPU_REGION_SIZE_256MBYTE: u32 = 27;
pub const MPU_REGION_SIZE_512MBYTE: u32 = 28;
pub const MPU_REGION_SIZE_1GBYTE: u32 = 29;
pub const MPU_REGION_SIZE_2GBYTE: u32 = 30;
pub const MPU_REGION_SIZE_4GBYTE: u32 = 31;
pub const MPU_FLAG_DMA1: u32 = 256;
pub const MPU_FLAG_DMA2: u32 = 1;
pub const MPU_FLAG_USBFS_DMA: u32 = 65536;
pub const MPU_FLAG_ALL: u32 = 65793;
pub const MPU_IP_AES: u32 = 1;
pub const MPU_IP_HASH: u32 = 4;
pub const MPU_IP_TRNG: u32 = 16;
pub const MPU_IP_CRC: u32 = 64;
pub const MPU_IP_EFM: u32 = 256;
pub const MPU_IP_WDT: u32 = 4096;
pub const MPU_IP_SWDT: u32 = 16384;
pub const MPU_IP_BKSRAM: u32 = 65536;
pub const MPU_IP_RTC: u32 = 262144;
pub const MPU_IP_MPU: u32 = 1048576;
pub const MPU_IP_SRAMC: u32 = 4194304;
pub const MPU_IP_INTC: u32 = 16777216;
pub const MPU_IP_RMU_CMU_PWC: u32 = 67108864;
pub const MPU_IP_FCG: u32 = 268435456;
pub const MPU_IP_ALL: u32 = 357912917;
pub const MPU_IP_EXP_TYPE_NONE: u32 = 0;
pub const MPU_IP_EXP_TYPE_BUS_ERR: u32 = 2147483648;
pub const MPU_REG_LOCK_KEY: u32 = 38564;
pub const MPU_REG_UNLOCK_KEY: u32 = 38565;
pub const OTS_CLK_XTAL: u32 = 0;
pub const OTS_CLK_HRC: u32 = 2;
pub const OTS_AUTO_OFF_DISABLE: u32 = 0;
pub const OTS_AUTO_OFF_ENABLE: u32 = 8;
pub const OTS_PARAM_TEMP_COND_TN40: u32 = 0;
pub const OTS_PARAM_TEMP_COND_T25: u32 = 1;
pub const OTS_PARAM_TEMP_COND_T125: u32 = 2;
pub const PWC_PD_MD1: u32 = 0;
pub const PWC_PD_MD2: u32 = 1;
pub const PWC_PD_MD3: u32 = 2;
pub const PWC_PD_MD4: u32 = 3;
pub const PWC_PD_IO_KEEP1: u32 = 0;
pub const PWC_PD_IO_KEEP2: u32 = 16;
pub const PWC_PD_IO_HIZ: u32 = 32;
pub const PWC_PD_VCAP_0P1UF: u32 = 0;
pub const PWC_PD_VCAP_0P047UF: u32 = 1;
pub const PWC_STOP_DRV_HIGH: u32 = 0;
pub const PWC_STOP_DRV_LOW: u32 = 192;
pub const PWC_STOP_CLK_KEEP: u32 = 0;
pub const PWC_STOP_CLK_MRC: u32 = 2;
pub const PWC_STOP_FLASH_WAIT_ON: u32 = 0;
pub const PWC_STOP_FLASH_WAIT_OFF: u32 = 1;
pub const PWC_STOP_WFI: u32 = 0;
pub const PWC_STOP_WFE_INT: u32 = 1;
pub const PWC_STOP_WFE_EVT: u32 = 2;
pub const PWC_SLEEP_WFI: u32 = 0;
pub const PWC_SLEEP_WFE_INT: u32 = 1;
pub const PWC_SLEEP_WFE_EVT: u32 = 2;
pub const PWC_RAM_HIGH_SPEED: u32 = 32835;
pub const PWC_RAM_ULOW_SPEED: u32 = 36962;
pub const PWC_RAM_PD_SRAM1: u32 = 1;
pub const PWC_RAM_PD_SRAM2: u32 = 2;
pub const PWC_RAM_PD_SRAM3: u32 = 4;
pub const PWC_RAM_PD_SRAMH: u32 = 8;
pub const PWC_RAM_PD_USBFS: u32 = 16;
pub const PWC_RAM_PD_SDIO0: u32 = 32;
pub const PWC_RAM_PD_SDIO1: u32 = 64;
pub const PWC_RAM_PD_CACHE: u32 = 256;
pub const PWC_RAM_PD_CAN: u32 = 128;
pub const PWC_RAM_PD_ALL: u32 = 511;
pub const PWC_LVD_CH1: u32 = 0;
pub const PWC_LVD_CH2: u32 = 1;
pub const PWC_LVD_ON: u32 = 32;
pub const PWC_LVD_OFF: u32 = 0;
pub const PWC_LVD_EXP_TYPE_NONE: u32 = 0;
pub const PWC_LVD_EXP_TYPE_INT: u32 = 257;
pub const PWC_LVD_EXP_TYPE_NMI: u32 = 1;
pub const PWC_LVD_EXP_TYPE_RST: u32 = 3;
pub const PWC_LVD_CMP_OFF: u32 = 0;
pub const PWC_LVD_CMP_ON: u32 = 4;
pub const PWC_LVD_FILTER_ON: u32 = 0;
pub const PWC_LVD_FILTER_OFF: u32 = 1;
pub const PWC_LVD_FILTER_LRC_DIV4: u32 = 0;
pub const PWC_LVD_FILTER_LRC_DIV2: u32 = 2;
pub const PWC_LVD_FILTER_LRC_DIV1: u32 = 4;
pub const PWC_LVD_FILTER_LRC_MUL2: u32 = 6;
pub const PWC_LVD_THRESHOLD_LVL0: u32 = 0;
pub const PWC_LVD_THRESHOLD_LVL1: u32 = 1;
pub const PWC_LVD_THRESHOLD_LVL2: u32 = 2;
pub const PWC_LVD_THRESHOLD_LVL3: u32 = 3;
pub const PWC_LVD_THRESHOLD_LVL4: u32 = 4;
pub const PWC_LVD_THRESHOLD_LVL5: u32 = 5;
pub const PWC_LVD_THRESHOLD_LVL6: u32 = 6;
pub const PWC_LVD_THRESHOLD_LVL7: u32 = 7;
pub const PWC_LVD_EXTVCC: u32 = 7;
pub const PWC_LVD1_FLAG_DETECT: u32 = 2;
pub const PWC_LVD2_FLAG_DETECT: u32 = 32;
pub const PWC_LVD1_FLAG_MON: u32 = 1;
pub const PWC_LVD2_FLAG_MON: u32 = 16;
pub const PWC_PD_WKUP0_POS: u32 = 0;
pub const PWC_PD_WKUP1_POS: u32 = 8;
pub const PWC_PD_WKUP2_POS: u32 = 16;
pub const PWC_PD_WKUP_WKUP00: u32 = 1;
pub const PWC_PD_WKUP_WKUP01: u32 = 2;
pub const PWC_PD_WKUP_WKUP02: u32 = 4;
pub const PWC_PD_WKUP_WKUP03: u32 = 8;
pub const PWC_PD_WKUP_WKUP10: u32 = 16;
pub const PWC_PD_WKUP_WKUP11: u32 = 32;
pub const PWC_PD_WKUP_WKUP12: u32 = 64;
pub const PWC_PD_WKUP_WKUP13: u32 = 128;
pub const PWC_PD_WKUP_WKUP20: u32 = 256;
pub const PWC_PD_WKUP_WKUP21: u32 = 512;
pub const PWC_PD_WKUP_WKUP22: u32 = 1024;
pub const PWC_PD_WKUP_WKUP23: u32 = 2048;
pub const PWC_PD_WKUP_WKUP30: u32 = 4096;
pub const PWC_PD_WKUP_WKUP31: u32 = 8192;
pub const PWC_PD_WKUP_WKUP32: u32 = 16384;
pub const PWC_PD_WKUP_WKUP33: u32 = 32768;
pub const PWC_PD_WKUP_LVD1: u32 = 65536;
pub const PWC_PD_WKUP_LVD2: u32 = 131072;
pub const PWC_PD_WKUP_NMI: u32 = 262144;
pub const PWC_PD_WKUP_RTCPRD: u32 = 1048576;
pub const PWC_PD_WKUP_RTCALM: u32 = 2097152;
pub const PWC_PD_WKUP_WKTM: u32 = 8388608;
pub const PWC_PD_WKUP_TRIG_LVD1: u32 = 16;
pub const PWC_PD_WKUP_TRIG_LVD2: u32 = 32;
pub const PWC_PD_WKUP_TRIG_WKUP0: u32 = 1;
pub const PWC_PD_WKUP_TRIG_WKUP1: u32 = 2;
pub const PWC_PD_WKUP_TRIG_WKUP2: u32 = 4;
pub const PWC_PD_WKUP_TRIG_WKUP3: u32 = 8;
pub const PWC_PD_WKUP_TRIG_NMI: u32 = 64;
pub const PWC_PD_WKUP_TRIG_ALL: u32 = 127;
pub const PWC_PD_WKUP_TRIG_FALLING: u32 = 0;
pub const PWC_PD_WKUP_TRIG_RISING: u32 = 1;
pub const PWC_PD_WKUP_FLAG0_POS: u32 = 0;
pub const PWC_PD_WKUP_FLAG1_POS: u32 = 8;
pub const PWC_PD_WKUP_FLAG_WKUP0: u32 = 1;
pub const PWC_PD_WKUP_FLAG_WKUP1: u32 = 2;
pub const PWC_PD_WKUP_FLAG_WKUP2: u32 = 4;
pub const PWC_PD_WKUP_FLAG_WKUP3: u32 = 8;
pub const PWC_PD_WKUP_FLAG_LVD1: u32 = 16;
pub const PWC_PD_WKUP_FLAG_LVD2: u32 = 32;
pub const PWC_PD_WKUP_FLAG_NMI: u32 = 64;
pub const PWC_PD_WKUP_FLAG_RTCPRD: u32 = 4096;
pub const PWC_PD_WKUP_FLAG_RTCALM: u32 = 8192;
pub const PWC_PD_WKUP_FLAG_WKTM: u32 = 32768;
pub const PWC_PD_WKUP_FLAG_ALL: u32 = 45183;
pub const PWC_WKT_OFF: u32 = 0;
pub const PWC_WKT_ON: u32 = 32768;
pub const PWC_WKT_CLK_SRC_64HZ: u32 = 0;
pub const PWC_WKT_CLK_SRC_XTAL32: u32 = 8192;
pub const PWC_WKT_CLK_SRC_LRC: u32 = 16384;
pub const PWC_LDO_HRC: u32 = 2;
pub const PWC_LDO_PLL: u32 = 1;
pub const PWC_LDO_MASK: u32 = 3;
pub const PWC_WRITE_ENABLE: u32 = 42240;
pub const PWC_UNLOCK_CODE0: u32 = 42241;
pub const PWC_UNLOCK_CODE1: u32 = 42242;
pub const PWC_UNLOCK_CODE2: u32 = 42248;
pub const PWC_FCG0_REG_UNLOCK_KEY: u32 = 2779054081;
pub const PWC_FCG0_REG_LOCK_KEY: u32 = 2779054080;
pub const QSPI_ROM_BASE: u32 = 2550136832;
pub const QSPI_ROM_END: u32 = 2617245695;
pub const QSPI_CLK_DIV2: u32 = 65536;
pub const QSPI_CLK_DIV3: u32 = 131072;
pub const QSPI_CLK_DIV4: u32 = 196608;
pub const QSPI_CLK_DIV5: u32 = 262144;
pub const QSPI_CLK_DIV6: u32 = 327680;
pub const QSPI_CLK_DIV7: u32 = 393216;
pub const QSPI_CLK_DIV8: u32 = 458752;
pub const QSPI_CLK_DIV9: u32 = 524288;
pub const QSPI_CLK_DIV10: u32 = 589824;
pub const QSPI_CLK_DIV11: u32 = 655360;
pub const QSPI_CLK_DIV12: u32 = 720896;
pub const QSPI_CLK_DIV13: u32 = 786432;
pub const QSPI_CLK_DIV14: u32 = 851968;
pub const QSPI_CLK_DIV15: u32 = 917504;
pub const QSPI_CLK_DIV16: u32 = 983040;
pub const QSPI_CLK_DIV17: u32 = 1048576;
pub const QSPI_CLK_DIV18: u32 = 1114112;
pub const QSPI_CLK_DIV19: u32 = 1179648;
pub const QSPI_CLK_DIV20: u32 = 1245184;
pub const QSPI_CLK_DIV21: u32 = 1310720;
pub const QSPI_CLK_DIV22: u32 = 1376256;
pub const QSPI_CLK_DIV23: u32 = 1441792;
pub const QSPI_CLK_DIV24: u32 = 1507328;
pub const QSPI_CLK_DIV25: u32 = 1572864;
pub const QSPI_CLK_DIV26: u32 = 1638400;
pub const QSPI_CLK_DIV27: u32 = 1703936;
pub const QSPI_CLK_DIV28: u32 = 1769472;
pub const QSPI_CLK_DIV29: u32 = 1835008;
pub const QSPI_CLK_DIV30: u32 = 1900544;
pub const QSPI_CLK_DIV31: u32 = 1966080;
pub const QSPI_CLK_DIV32: u32 = 2031616;
pub const QSPI_CLK_DIV33: u32 = 2097152;
pub const QSPI_CLK_DIV34: u32 = 2162688;
pub const QSPI_CLK_DIV35: u32 = 2228224;
pub const QSPI_CLK_DIV36: u32 = 2293760;
pub const QSPI_CLK_DIV37: u32 = 2359296;
pub const QSPI_CLK_DIV38: u32 = 2424832;
pub const QSPI_CLK_DIV39: u32 = 2490368;
pub const QSPI_CLK_DIV40: u32 = 2555904;
pub const QSPI_CLK_DIV41: u32 = 2621440;
pub const QSPI_CLK_DIV42: u32 = 2686976;
pub const QSPI_CLK_DIV43: u32 = 2752512;
pub const QSPI_CLK_DIV44: u32 = 2818048;
pub const QSPI_CLK_DIV45: u32 = 2883584;
pub const QSPI_CLK_DIV46: u32 = 2949120;
pub const QSPI_CLK_DIV47: u32 = 3014656;
pub const QSPI_CLK_DIV48: u32 = 3080192;
pub const QSPI_CLK_DIV49: u32 = 3145728;
pub const QSPI_CLK_DIV50: u32 = 3211264;
pub const QSPI_CLK_DIV51: u32 = 3276800;
pub const QSPI_CLK_DIV52: u32 = 3342336;
pub const QSPI_CLK_DIV53: u32 = 3407872;
pub const QSPI_CLK_DIV54: u32 = 3473408;
pub const QSPI_CLK_DIV55: u32 = 3538944;
pub const QSPI_CLK_DIV56: u32 = 3604480;
pub const QSPI_CLK_DIV57: u32 = 3670016;
pub const QSPI_CLK_DIV58: u32 = 3735552;
pub const QSPI_CLK_DIV59: u32 = 3801088;
pub const QSPI_CLK_DIV60: u32 = 3866624;
pub const QSPI_CLK_DIV61: u32 = 3932160;
pub const QSPI_CLK_DIV62: u32 = 3997696;
pub const QSPI_CLK_DIV63: u32 = 4063232;
pub const QSPI_CLK_DIV64: u32 = 4128768;
pub const QSPI_SPI_MD0: u32 = 0;
pub const QSPI_SPI_MD3: u32 = 128;
pub const QSPI_PREFETCH_MD_INVD: u32 = 0;
pub const QSPI_PREFETCH_MD_EDGE_STOP: u32 = 8;
pub const QSPI_PREFETCH_MD_IMMED_STOP: u32 = 24;
pub const QSPI_RD_MD_STD_RD: u32 = 0;
pub const QSPI_RD_MD_FAST_RD: u32 = 1;
pub const QSPI_RD_MD_DUAL_OUTPUT_FAST_RD: u32 = 2;
pub const QSPI_RD_MD_DUAL_IO_FAST_RD: u32 = 3;
pub const QSPI_RD_MD_QUAD_OUTPUT_FAST_RD: u32 = 4;
pub const QSPI_RD_MD_QUAD_IO_FAST_RD: u32 = 5;
pub const QSPI_RD_MD_CUSTOM_STANDARD_RD: u32 = 6;
pub const QSPI_RD_MD_CUSTOM_FAST_RD: u32 = 7;
pub const QSPI_DUMMY_CYCLE3: u32 = 0;
pub const QSPI_DUMMY_CYCLE4: u32 = 256;
pub const QSPI_DUMMY_CYCLE5: u32 = 512;
pub const QSPI_DUMMY_CYCLE6: u32 = 768;
pub const QSPI_DUMMY_CYCLE7: u32 = 1024;
pub const QSPI_DUMMY_CYCLE8: u32 = 1280;
pub const QSPI_DUMMY_CYCLE9: u32 = 1536;
pub const QSPI_DUMMY_CYCLE10: u32 = 1792;
pub const QSPI_DUMMY_CYCLE11: u32 = 2048;
pub const QSPI_DUMMY_CYCLE12: u32 = 2304;
pub const QSPI_DUMMY_CYCLE13: u32 = 2560;
pub const QSPI_DUMMY_CYCLE14: u32 = 2816;
pub const QSPI_DUMMY_CYCLE15: u32 = 3072;
pub const QSPI_DUMMY_CYCLE16: u32 = 3328;
pub const QSPI_DUMMY_CYCLE17: u32 = 3584;
pub const QSPI_DUMMY_CYCLE18: u32 = 3840;
pub const QSPI_ADDR_WIDTH_8BIT: u32 = 0;
pub const QSPI_ADDR_WIDTH_16BIT: u32 = 1;
pub const QSPI_ADDR_WIDTH_24BIT: u32 = 2;
pub const QSPI_ADDR_WIDTH_32BIT_INSTR_24BIT: u32 = 3;
pub const QSPI_ADDR_WIDTH_32BIT_INSTR_32BIT: u32 = 7;
pub const QSPI_QSSN_SETUP_ADVANCE_QSCK0P5: u32 = 0;
pub const QSPI_QSSN_SETUP_ADVANCE_QSCK1P5: u32 = 32;
pub const QSPI_QSSN_RELEASE_DELAY_QSCK0P5: u32 = 0;
pub const QSPI_QSSN_RELEASE_DELAY_QSCK1P5: u32 = 16;
pub const QSPI_QSSN_RELEASE_DELAY_QSCK32: u32 = 4096;
pub const QSPI_QSSN_RELEASE_DELAY_QSCK128: u32 = 8192;
pub const QSPI_QSSN_RELEASE_DELAY_INFINITE: u32 = 12288;
pub const QSPI_QSSN_INTERVAL_QSCK1: u32 = 0;
pub const QSPI_QSSN_INTERVAL_QSCK2: u32 = 1;
pub const QSPI_QSSN_INTERVAL_QSCK3: u32 = 2;
pub const QSPI_QSSN_INTERVAL_QSCK4: u32 = 3;
pub const QSPI_QSSN_INTERVAL_QSCK5: u32 = 4;
pub const QSPI_QSSN_INTERVAL_QSCK6: u32 = 5;
pub const QSPI_QSSN_INTERVAL_QSCK7: u32 = 6;
pub const QSPI_QSSN_INTERVAL_QSCK8: u32 = 7;
pub const QSPI_QSSN_INTERVAL_QSCK9: u32 = 8;
pub const QSPI_QSSN_INTERVAL_QSCK10: u32 = 9;
pub const QSPI_QSSN_INTERVAL_QSCK11: u32 = 10;
pub const QSPI_QSSN_INTERVAL_QSCK12: u32 = 11;
pub const QSPI_QSSN_INTERVAL_QSCK13: u32 = 12;
pub const QSPI_QSSN_INTERVAL_QSCK14: u32 = 13;
pub const QSPI_QSSN_INTERVAL_QSCK15: u32 = 14;
pub const QSPI_QSSN_INTERVAL_QSCK16: u32 = 15;
pub const QSPI_INSTR_PROTOCOL_1LINE: u32 = 0;
pub const QSPI_INSTR_PROTOCOL_2LINE: u32 = 256;
pub const QSPI_INSTR_PROTOCOL_4LINE: u32 = 512;
pub const QSPI_ADDR_PROTOCOL_1LINE: u32 = 0;
pub const QSPI_ADDR_PROTOCOL_2LINE: u32 = 1024;
pub const QSPI_ADDR_PROTOCOL_4LINE: u32 = 2048;
pub const QSPI_DATA_PROTOCOL_1LINE: u32 = 0;
pub const QSPI_DATA_PROTOCOL_2LINE: u32 = 4096;
pub const QSPI_DATA_PROTOCOL_4LINE: u32 = 8192;
pub const QSPI_WP_PIN_LOW: u32 = 0;
pub const QSPI_WP_PIN_HIGH: u32 = 64;
pub const QSPI_FLAG_DIRECT_COMM_BUSY: u32 = 1;
pub const QSPI_FLAG_XIP_MD: u32 = 64;
pub const QSPI_FLAG_ROM_ACCESS_ERR: u32 = 128;
pub const QSPI_FLAG_PREFETCH_BUF_FULL: u32 = 16384;
pub const QSPI_FLAG_PREFETCH_STOP: u32 = 32768;
pub const QSPI_FLAG_ALL: u32 = 49345;
pub const QSPI_FLAG_CLR_ALL: u32 = 128;
pub const RMU_FLAG_PWR_ON: u32 = 1;
pub const RMU_FLAG_PIN: u32 = 2;
pub const RMU_FLAG_BROWN_OUT: u32 = 4;
pub const RMU_FLAG_PVD1: u32 = 8;
pub const RMU_FLAG_PVD2: u32 = 16;
pub const RMU_FLAG_WDT: u32 = 32;
pub const RMU_FLAG_SWDT: u32 = 64;
pub const RMU_FLAG_PWR_DOWN: u32 = 128;
pub const RMU_FLAG_SW: u32 = 256;
pub const RMU_FLAG_MPU_ERR: u32 = 512;
pub const RMU_FLAG_RAM_PARITY_ERR: u32 = 1024;
pub const RMU_FLAG_RAM_ECC: u32 = 2048;
pub const RMU_FLAG_CLK_ERR: u32 = 4096;
pub const RMU_FLAG_XTAL_ERR: u32 = 8192;
pub const RMU_FLAG_MX: u32 = 16384;
pub const RMU_FLAG_ALL: u32 = 32767;
pub const RTC_DATA_FMT_DEC: u32 = 0;
pub const RTC_DATA_FMT_BCD: u32 = 1;
pub const RTC_CLK_SRC_XTAL32: u32 = 0;
pub const RTC_CLK_SRC_LRC: u32 = 144;
pub const RTC_HOUR_FMT_12H: u32 = 0;
pub const RTC_HOUR_FMT_24H: u32 = 8;
pub const RTC_INT_PERIOD_INVD: u32 = 0;
pub const RTC_INT_PERIOD_PER_HALF_SEC: u32 = 1;
pub const RTC_INT_PERIOD_PER_SEC: u32 = 2;
pub const RTC_INT_PERIOD_PER_MINUTE: u32 = 3;
pub const RTC_INT_PERIOD_PER_HOUR: u32 = 4;
pub const RTC_INT_PERIOD_PER_DAY: u32 = 5;
pub const RTC_INT_PERIOD_PER_MONTH: u32 = 6;
pub const RTC_CLK_COMPEN_DISABLE: u32 = 0;
pub const RTC_CLK_COMPEN_ENABLE: u32 = 128;
pub const RTC_CLK_COMPEN_MD_DISTRIBUTED: u32 = 0;
pub const RTC_CLK_COMPEN_MD_UNIFORM: u32 = 64;
pub const RTC_HOUR_24H: u32 = 0;
pub const RTC_HOUR_12H_AM: u32 = 0;
pub const RTC_HOUR_12H_PM: u32 = 32;
pub const RTC_MONTH_JANUARY: u32 = 1;
pub const RTC_MONTH_FEBRUARY: u32 = 2;
pub const RTC_MONTH_MARCH: u32 = 3;
pub const RTC_MONTH_APRIL: u32 = 4;
pub const RTC_MONTH_MAY: u32 = 5;
pub const RTC_MONTH_JUNE: u32 = 6;
pub const RTC_MONTH_JULY: u32 = 7;
pub const RTC_MONTH_AUGUST: u32 = 8;
pub const RTC_MONTH_SEPTEMBER: u32 = 9;
pub const RTC_MONTH_OCTOBER: u32 = 10;
pub const RTC_MONTH_NOVEMBER: u32 = 11;
pub const RTC_MONTH_DECEMBER: u32 = 12;
pub const RTC_WEEKDAY_SUNDAY: u32 = 0;
pub const RTC_WEEKDAY_MONDAY: u32 = 1;
pub const RTC_WEEKDAY_TUESDAY: u32 = 2;
pub const RTC_WEEKDAY_WEDNESDAY: u32 = 3;
pub const RTC_WEEKDAY_THURSDAY: u32 = 4;
pub const RTC_WEEKDAY_FRIDAY: u32 = 5;
pub const RTC_WEEKDAY_SATURDAY: u32 = 6;
pub const RTC_ALARM_WEEKDAY_SUNDAY: u32 = 1;
pub const RTC_ALARM_WEEKDAY_MONDAY: u32 = 2;
pub const RTC_ALARM_WEEKDAY_TUESDAY: u32 = 4;
pub const RTC_ALARM_WEEKDAY_WEDNESDAY: u32 = 8;
pub const RTC_ALARM_WEEKDAY_THURSDAY: u32 = 16;
pub const RTC_ALARM_WEEKDAY_FRIDAY: u32 = 32;
pub const RTC_ALARM_WEEKDAY_SATURDAY: u32 = 64;
pub const RTC_ALARM_WEEKDAY_EVERYDAY: u32 = 127;
pub const RTC_FLAG_RD_WR: u32 = 2;
pub const RTC_FLAG_ALARM: u32 = 8;
pub const RTC_FLAG_ALL: u32 = 10;
pub const RTC_FLAG_CLR_ALL: u32 = 8;
pub const RTC_INT_PERIOD: u32 = 32;
pub const RTC_INT_ALARM: u32 = 64;
pub const RTC_INT_ALL: u32 = 96;
pub const SDIOC_MD_SD: u32 = 0;
pub const SDIOC_MD_MMC: u32 = 1;
pub const SDIOC_CARD_DETECT_CD_PIN_LVL: u32 = 0;
pub const SDIOC_CARD_DETECT_TEST_SIGNAL: u32 = 128;
pub const SDIOC_CARD_DETECT_TEST_LVL_LOW: u32 = 0;
pub const SDIOC_CARD_DETECT_TEST_LVL_HIGH: u32 = 64;
pub const SDIOC_SPEED_MD_NORMAL: u32 = 0;
pub const SDIOC_SPEED_MD_HIGH: u32 = 4;
pub const SDIOC_BUS_WIDTH_1BIT: u32 = 0;
pub const SDIOC_BUS_WIDTH_4BIT: u32 = 2;
pub const SDIOC_BUS_WIDTH_8BIT: u32 = 32;
pub const SDIOC_CLK_DIV1: u32 = 0;
pub const SDIOC_CLK_DIV2: u32 = 256;
pub const SDIOC_CLK_DIV4: u32 = 512;
pub const SDIOC_CLK_DIV8: u32 = 1024;
pub const SDIOC_CLK_DIV16: u32 = 2048;
pub const SDIOC_CLK_DIV32: u32 = 4096;
pub const SDIOC_CLK_DIV64: u32 = 8192;
pub const SDIOC_CLK_DIV128: u32 = 16384;
pub const SDIOC_CLK_DIV256: u32 = 32768;
pub const SDIOC_CMD_TYPE_NORMAL: u32 = 0;
pub const SDIOC_CMD_TYPE_SUSPEND: u32 = 64;
pub const SDIOC_CMD_TYPE_RESUME: u32 = 128;
pub const SDIOC_CMD_TYPE_ABORT: u32 = 192;
pub const SDIOC_DATA_LINE_DISABLE: u32 = 0;
pub const SDIOC_DATA_LINE_ENABLE: u32 = 32;
pub const SDIOC_TRANS_DIR_TO_CARD: u32 = 0;
pub const SDIOC_TRANS_DIR_TO_HOST: u32 = 16;
pub const SDIOC_AUTO_SEND_CMD12_DISABLE: u32 = 0;
pub const SDIOC_AUTO_SEND_CMD12_ENABLE: u32 = 4;
pub const SDIOC_TRANS_MD_SINGLE: u32 = 0;
pub const SDIOC_TRANS_MD_INFINITE: u32 = 32;
pub const SDIOC_TRANS_MD_MULTI: u32 = 34;
pub const SDIOC_TRANS_MD_STOP_MULTI: u32 = 32802;
pub const SDIOC_DATA_TIMEOUT_CLK_2E13: u32 = 0;
pub const SDIOC_DATA_TIMEOUT_CLK_2E14: u32 = 1;
pub const SDIOC_DATA_TIMEOUT_CLK_2E15: u32 = 2;
pub const SDIOC_DATA_TIMEOUT_CLK_2E16: u32 = 3;
pub const SDIOC_DATA_TIMEOUT_CLK_2E17: u32 = 4;
pub const SDIOC_DATA_TIMEOUT_CLK_2E18: u32 = 5;
pub const SDIOC_DATA_TIMEOUT_CLK_2E19: u32 = 6;
pub const SDIOC_DATA_TIMEOUT_CLK_2E20: u32 = 7;
pub const SDIOC_DATA_TIMEOUT_CLK_2E21: u32 = 8;
pub const SDIOC_DATA_TIMEOUT_CLK_2E22: u32 = 9;
pub const SDIOC_DATA_TIMEOUT_CLK_2E23: u32 = 10;
pub const SDIOC_DATA_TIMEOUT_CLK_2E24: u32 = 11;
pub const SDIOC_DATA_TIMEOUT_CLK_2E25: u32 = 12;
pub const SDIOC_DATA_TIMEOUT_CLK_2E26: u32 = 13;
pub const SDIOC_DATA_TIMEOUT_CLK_2E27: u32 = 14;
pub const SDIOC_RESP_REG_BIT0_31: u32 = 0;
pub const SDIOC_RESP_REG_BIT32_63: u32 = 4;
pub const SDIOC_RESP_REG_BIT64_95: u32 = 8;
pub const SDIOC_RESP_REG_BIT96_127: u32 = 12;
pub const SDIOC_SW_RST_DATA_LINE: u32 = 4;
pub const SDIOC_SW_RST_CMD_LINE: u32 = 2;
pub const SDIOC_SW_RST_ALL: u32 = 1;
pub const SDIOC_OUTPUT_CLK_FREQ_400K: u32 = 400000;
pub const SDIOC_OUTPUT_CLK_FREQ_25M: u32 = 25000000;
pub const SDIOC_OUTPUT_CLK_FREQ_26M: u32 = 26000000;
pub const SDIOC_OUTPUT_CLK_FREQ_50M: u32 = 50000000;
pub const SDIOC_OUTPUT_CLK_FREQ_52M: u32 = 52000000;
pub const SDIOC_HOST_FLAG_CMDL: u32 = 16777216;
pub const SDIOC_HOST_FLAG_DATL: u32 = 15728640;
pub const SDIOC_HOST_FLAG_DATL_D0: u32 = 1048576;
pub const SDIOC_HOST_FLAG_DATL_D1: u32 = 2097152;
pub const SDIOC_HOST_FLAG_DATL_D2: u32 = 4194304;
pub const SDIOC_HOST_FLAG_DATL_D3: u32 = 8388608;
pub const SDIOC_HOST_FLAG_WPL: u32 = 524288;
pub const SDIOC_HOST_FLAG_CDL: u32 = 262144;
pub const SDIOC_HOST_FLAG_CSS: u32 = 131072;
pub const SDIOC_HOST_FLAG_CIN: u32 = 65536;
pub const SDIOC_HOST_FLAG_BRE: u32 = 2048;
pub const SDIOC_HOST_FLAG_BWE: u32 = 1024;
pub const SDIOC_HOST_FLAG_RTA: u32 = 512;
pub const SDIOC_HOST_FLAG_WTA: u32 = 256;
pub const SDIOC_HOST_FLAG_DA: u32 = 4;
pub const SDIOC_HOST_FLAG_CID: u32 = 2;
pub const SDIOC_HOST_FLAG_CIC: u32 = 1;
pub const SDIOC_HOST_FLAG_ALL: u32 = 33492743;
pub const SDIOC_INT_FLAG_EI: u32 = 32768;
pub const SDIOC_INT_FLAG_CINT: u32 = 256;
pub const SDIOC_INT_FLAG_CRM: u32 = 128;
pub const SDIOC_INT_FLAG_CIST: u32 = 64;
pub const SDIOC_INT_FLAG_BRR: u32 = 32;
pub const SDIOC_INT_FLAG_BWR: u32 = 16;
pub const SDIOC_INT_FLAG_BGE: u32 = 4;
pub const SDIOC_INT_FLAG_TC: u32 = 2;
pub const SDIOC_INT_FLAG_CC: u32 = 1;
pub const SDIOC_NORMAL_INT_FLAG_ALL: u32 = 33271;
pub const SDIOC_INT_CINTSEN: u32 = 256;
pub const SDIOC_INT_CRMSEN: u32 = 128;
pub const SDIOC_INT_CISTSEN: u32 = 64;
pub const SDIOC_INT_BRRSEN: u32 = 32;
pub const SDIOC_INT_BWRSEN: u32 = 16;
pub const SDIOC_INT_BGESEN: u32 = 4;
pub const SDIOC_INT_TCSEN: u32 = 2;
pub const SDIOC_INT_CCSEN: u32 = 1;
pub const SDIOC_NORMAL_INT_ALL: u32 = 503;
pub const SDIOC_AUTO_CMD_ERR_FLAG_CMDE: u32 = 128;
pub const SDIOC_AUTO_CMD_ERR_FLAG_IE: u32 = 16;
pub const SDIOC_AUTO_CMD_ERR_FLAG_EBE: u32 = 8;
pub const SDIOC_AUTO_CMD_ERR_FLAG_CE: u32 = 4;
pub const SDIOC_AUTO_CMD_ERR_FLAG_TOE: u32 = 2;
pub const SDIOC_AUTO_CMD_ERR_FLAG_NE: u32 = 1;
pub const SDIOC_AUTO_CMD_ERR_FLAG_ALL: u32 = 159;
pub const SDIOC_FORCE_AUTO_CMD_ERR_FCMDE: u32 = 128;
pub const SDIOC_FORCE_AUTO_CMD_ERR_FIE: u32 = 16;
pub const SDIOC_FORCE_AUTO_CMD_ERR_FEBE: u32 = 8;
pub const SDIOC_FORCE_AUTO_CMD_ERR_FCE: u32 = 4;
pub const SDIOC_FORCE_AUTO_CMD_ERR_FTOE: u32 = 2;
pub const SDIOC_FORCE_AUTO_CMD_ERR_FNE: u32 = 1;
pub const SDIOC_FORCE_AUTO_CMD_ERR_ALL: u32 = 159;
pub const SDIOC_FORCE_ERR_INT_FACE: u32 = 256;
pub const SDIOC_FORCE_ERR_INT_FDEBE: u32 = 64;
pub const SDIOC_FORCE_ERR_INT_FDCE: u32 = 32;
pub const SDIOC_FORCE_ERR_INT_FDTOE: u32 = 16;
pub const SDIOC_FORCE_ERR_INT_FCIE: u32 = 8;
pub const SDIOC_FORCE_ERR_INT_FCEBE: u32 = 4;
pub const SDIOC_FORCE_ERR_INT_FCCE: u32 = 2;
pub const SDIOC_FORCE_ERR_INT_FCTOE: u32 = 1;
pub const SDIOC_FORCE_ERR_INT_ALL: u32 = 383;
pub const SDIOC_RESP_TYPE_NO: u32 = 0;
pub const SDIOC_RESP_TYPE_R2: u32 = 1;
pub const SDIOC_RESP_TYPE_R3_R4: u32 = 2;
pub const SDIOC_RESP_TYPE_R1_R5_R6_R7: u32 = 26;
pub const SDIOC_RESP_TYPE_R1B_R5B: u32 = 27;
pub const SDIOC_CMD0_GO_IDLE_STATE: u32 = 0;
pub const SDIOC_CMD1_SEND_OP_COND: u32 = 1;
pub const SDIOC_CMD2_ALL_SEND_CID: u32 = 2;
pub const SDIOC_CMD3_SEND_RELATIVE_ADDR: u32 = 3;
pub const SDIOC_CMD4_SET_DSR: u32 = 4;
pub const SDIOC_CMD5_IO_SEND_OP_COND: u32 = 5;
pub const SDIOC_CMD6_SWITCH_FUNC: u32 = 6;
pub const SDIOC_CMD7_SELECT_DESELECT_CARD: u32 = 7;
pub const SDIOC_CMD8_SEND_IF_COND: u32 = 8;
pub const SDIOC_CMD9_SEND_CSD: u32 = 9;
pub const SDIOC_CMD10_SEND_CID: u32 = 10;
pub const SDIOC_CMD11_READ_DAT_UNTIL_STOP: u32 = 11;
pub const SDIOC_CMD12_STOP_TRANSMISSION: u32 = 12;
pub const SDIOC_CMD13_SEND_STATUS: u32 = 13;
pub const SDIOC_CMD14_HS_BUSTEST_READ: u32 = 14;
pub const SDIOC_CMD15_GO_INACTIVE_STATE: u32 = 15;
pub const SDIOC_CMD16_SET_BLOCKLEN: u32 = 16;
pub const SDIOC_CMD17_READ_SINGLE_BLOCK: u32 = 17;
pub const SDIOC_CMD18_READ_MULTI_BLOCK: u32 = 18;
pub const SDIOC_CMD19_HS_BUSTEST_WRITE: u32 = 19;
pub const SDIOC_CMD20_WRITE_DAT_UNTIL_STOP: u32 = 20;
pub const SDIOC_CMD23_SET_BLOCK_COUNT: u32 = 23;
pub const SDIOC_CMD24_WRITE_SINGLE_BLOCK: u32 = 24;
pub const SDIOC_CMD25_WRITE_MULTI_BLOCK: u32 = 25;
pub const SDIOC_CMD26_PROGRAM_CID: u32 = 26;
pub const SDIOC_CMD27_PROGRAM_CSD: u32 = 27;
pub const SDIOC_CMD28_SET_WRITE_PROT: u32 = 28;
pub const SDIOC_CMD29_CLR_WRITE_PROT: u32 = 29;
pub const SDIOC_CMD30_SEND_WRITE_PROT: u32 = 30;
pub const SDIOC_CMD32_ERASE_WR_BLK_START: u32 = 32;
pub const SDIOC_CMD33_ERASE_WR_BLK_END: u32 = 33;
pub const SDIOC_CMD35_ERASE_GROUP_START: u32 = 35;
pub const SDIOC_CMD36_ERASE_GROUP_END: u32 = 36;
pub const SDIOC_CMD38_ERASE: u32 = 38;
pub const SDIOC_CMD39_FAST_IO: u32 = 39;
pub const SDIOC_CMD40_GO_IRQ_STATE: u32 = 40;
pub const SDIOC_CMD42_LOCK_UNLOCK: u32 = 42;
pub const SDIOC_CMD52_IO_RW_DIRECT: u32 = 52;
pub const SDIOC_CMD53_IO_RW_EXTENDED: u32 = 53;
pub const SDIOC_CMD55_APP_CMD: u32 = 55;
pub const SDIOC_CMD56_GEN_CMD: u32 = 56;
pub const SDIOC_CMD64_NO_CMD: u32 = 64;
pub const SDIOC_ACMD6_SET_BUS_WIDTH: u32 = 6;
pub const SDIOC_ACMD13_SD_STATUS: u32 = 13;
pub const SDIOC_ACMD22_SEND_NUM_WR_BLOCKS: u32 = 22;
pub const SDIOC_ACMD23_SET_WR_BLK_ERASE_COUNT: u32 = 23;
pub const SDIOC_ACMD41_SD_APP_OP_COND: u32 = 41;
pub const SDIOC_ACMD42_SET_CLR_CARD_DETECT: u32 = 42;
pub const SDIOC_ACMD51_SEND_SCR: u32 = 51;
pub const SDIOC_ACMD43_GET_MKB: u32 = 43;
pub const SDIOC_ACMD44_GET_MID: u32 = 44;
pub const SDIOC_ACMD45_SET_CER_RN1: u32 = 45;
pub const SDIOC_ACMD46_GET_CER_RN2: u32 = 46;
pub const SDIOC_ACMD47_SET_CER_RES2: u32 = 47;
pub const SDIOC_ACMD48_GET_CER_RES1: u32 = 48;
pub const SDIOC_ACMD18_SECURE_READ_MULTI_BLOCK: u32 = 18;
pub const SDIOC_ACMD25_SECURE_WRITE_MULTI_BLOCK: u32 = 25;
pub const SDIOC_ACMD38_SECURE_ERASE: u32 = 38;
pub const SDIOC_ACMD49_CHANGE_SECURE_AREA: u32 = 49;
pub const SDIOC_ACMD48_SECURE_WRITE_MKB: u32 = 48;
pub const SDMMC_ERR_NONE: u32 = 0;
pub const SDMMC_ERR_ADDR_OUT_OF_RANGE: u32 = 2147483648;
pub const SDMMC_ERR_ADDR_MISALIGNED: u32 = 1073741824;
pub const SDMMC_ERR_BLOCK_LEN_ERR: u32 = 536870912;
pub const SDMMC_ERR_ERASE_SEQ_ERR: u32 = 268435456;
pub const SDMMC_ERR_BAD_ERASE_PARAM: u32 = 134217728;
pub const SDMMC_ERR_WR_PROT_VIOLATION: u32 = 67108864;
pub const SDMMC_ERR_LOCK_UNLOCK_FAILED: u32 = 16777216;
pub const SDMMC_ERR_COM_CRC_FAILED: u32 = 8388608;
pub const SDMMC_ERR_ILLEGAL_CMD: u32 = 4194304;
pub const SDMMC_ERR_CARD_ECC_FAILED: u32 = 2097152;
pub const SDMMC_ERR_CC_ERR: u32 = 1048576;
pub const SDMMC_ERR_GENERAL_UNKNOWN_ERR: u32 = 524288;
pub const SDMMC_ERR_STREAM_RD_UNDERRUN: u32 = 262144;
pub const SDMMC_ERR_STREAM_WR_OVERRUN: u32 = 131072;
pub const SDMMC_ERR_CID_CSD_OVERWRITE: u32 = 65536;
pub const SDMMC_ERR_WP_ERASE_SKIP: u32 = 32768;
pub const SDMMC_ERR_CARD_ECC_DISABLED: u32 = 16384;
pub const SDMMC_ERR_ERASE_RST: u32 = 8192;
pub const SDMMC_ERR_CMD_AUTO_SEND: u32 = 4096;
pub const SDMMC_ERR_CMD_INDEX: u32 = 2048;
pub const SDMMC_ERR_CMD_STOP_BIT: u32 = 1024;
pub const SDMMC_ERR_CMD_CRC_FAIL: u32 = 512;
pub const SDMMC_ERR_CMD_TIMEOUT: u32 = 256;
pub const SDMMC_ERR_SWITCH_ERR: u32 = 128;
pub const SDMMC_ERR_DATA_STOP_BIT: u32 = 64;
pub const SDMMC_ERR_DATA_CRC_FAIL: u32 = 32;
pub const SDMMC_ERR_DATA_TIMEOUT: u32 = 16;
pub const SDMMC_ERR_AKE_SEQ_ERR: u32 = 8;
pub const SDMMC_ERR_INVD_VOLT: u32 = 4;
pub const SDMMC_ERR_REQ_NOT_APPLICABLE: u32 = 2;
pub const SDMMC_ERR_UNSUPPORT_FEATURE: u32 = 1;
pub const SDMMC_ERR_BITS_MASK: u32 = 4261404744;
pub const SDMMC_STATUS_CARD_IS_LOCKED_POS: u32 = 24;
pub const SDMMC_STATUS_CARD_IS_LOCKED: u32 = 33554432;
pub const SDMMC_STATUS_CURR_STATE_POS: u32 = 9;
pub const SDMMC_STATUS_CURR_STATE: u32 = 7680;
pub const SDMMC_STATUS_RDY_FOR_DATA_POS: u32 = 8;
pub const SDMMC_STATUS_RDY_FOR_DATA: u32 = 256;
pub const SDMMC_STATUS_APP_CMD_POS: u32 = 5;
pub const SDMMC_STATUS_APP_CMD: u32 = 32;
pub const SDMMC_SCR_PHY_SPEC_VER_1P0: u32 = 0;
pub const SDMMC_SCR_PHY_SPEC_VER_1P1: u32 = 16777216;
pub const SDMMC_SCR_PHY_SPEC_VER_2P0: u32 = 33554432;
pub const SDMMC_SCR_BUS_WIDTH_4BIT: u32 = 262144;
pub const SDMMC_SCR_BUS_WIDTH_1BIT: u32 = 65536;
pub const SDMMC_OCR_HIGH_CAPACITY: u32 = 1073741824;
pub const SDMMC_OCR_STD_CAPACITY: u32 = 0;
pub const SDMMC_CSD_SUPPORT_CLASS5_ERASE: u32 = 32;
pub const SDMMC_DATA_TIMEOUT: u32 = 65535;
pub const SDMMC_MAX_VOLT_TRIAL: u32 = 65535;
pub const SDIO_CMD52_ARG_RD: u32 = 0;
pub const SDIO_CMD52_ARG_WR: u32 = 2147483648;
pub const SDIO_CMD52_ARG_RAW_FLAG_0: u32 = 0;
pub const SDIO_CMD52_ARG_RAW_FLAG_1: u32 = 134217728;
pub const SDIO_CMD53_ARG_RD: u32 = 0;
pub const SDIO_CMD53_ARG_WR: u32 = 2147483648;
pub const SDIO_CMD53_ARG_TRANS_MD_BYTE: u32 = 0;
pub const SDIO_CMD53_ARG_TRANS_MD_BLOCK: u32 = 134217728;
pub const SDIO_CMD53_ARG_OP_CODE_ADDR_FIX: u32 = 0;
pub const SDIO_CMD53_ARG_OP_CODE_ADDR_INC: u32 = 67108864;
pub const SPI_4_WIRE: u32 = 0;
pub const SPI_3_WIRE: u32 = 1;
pub const SPI_FULL_DUPLEX: u32 = 0;
pub const SPI_SEND_ONLY: u32 = 2;
pub const SPI_SLAVE: u32 = 0;
pub const SPI_MASTER: u32 = 8;
pub const SPI_LOOPBACK_INVD: u32 = 0;
pub const SPI_LOOPBACK_MOSI_INVT: u32 = 16;
pub const SPI_LOOPBACK_MOSI: u32 = 32;
pub const SPI_INT_ERR: u32 = 256;
pub const SPI_INT_TX_BUF_EMPTY: u32 = 512;
pub const SPI_INT_RX_BUF_FULL: u32 = 1024;
pub const SPI_INT_IDLE: u32 = 2048;
pub const SPI_INT_ALL: u32 = 3840;
pub const SPI_MD_FAULT_DETECT_DISABLE: u32 = 0;
pub const SPI_MD_FAULT_DETECT_ENABLE: u32 = 4096;
pub const SPI_PARITY_INVD: u32 = 0;
pub const SPI_PARITY_EVEN: u32 = 32768;
pub const SPI_PARITY_ODD: u32 = 49152;
pub const SPI_PIN_SS0: u32 = 256;
pub const SPI_PIN_SS1: u32 = 512;
pub const SPI_PIN_SS2: u32 = 1024;
pub const SPI_PIN_SS3: u32 = 2048;
pub const SPI_SS_VALID_LVL_HIGH: u32 = 1;
pub const SPI_SS_VALID_LVL_LOW: u32 = 0;
pub const SPI_RD_TARGET_RD_BUF: u32 = 0;
pub const SPI_RD_TARGET_WR_BUF: u32 = 64;
pub const SPI_1_FRAME: u32 = 0;
pub const SPI_2_FRAME: u32 = 1;
pub const SPI_3_FRAME: u32 = 2;
pub const SPI_4_FRAME: u32 = 3;
pub const SPI_INTERVAL_TIME_1SCK: u32 = 0;
pub const SPI_INTERVAL_TIME_2SCK: u32 = 268435456;
pub const SPI_INTERVAL_TIME_3SCK: u32 = 536870912;
pub const SPI_INTERVAL_TIME_4SCK: u32 = 805306368;
pub const SPI_INTERVAL_TIME_5SCK: u32 = 1073741824;
pub const SPI_INTERVAL_TIME_6SCK: u32 = 1342177280;
pub const SPI_INTERVAL_TIME_7SCK: u32 = 1610612736;
pub const SPI_INTERVAL_TIME_8SCK: u32 = 1879048192;
pub const SPI_RELEASE_TIME_1SCK: u32 = 0;
pub const SPI_RELEASE_TIME_2SCK: u32 = 16777216;
pub const SPI_RELEASE_TIME_3SCK: u32 = 33554432;
pub const SPI_RELEASE_TIME_4SCK: u32 = 50331648;
pub const SPI_RELEASE_TIME_5SCK: u32 = 67108864;
pub const SPI_RELEASE_TIME_6SCK: u32 = 83886080;
pub const SPI_RELEASE_TIME_7SCK: u32 = 100663296;
pub const SPI_RELEASE_TIME_8SCK: u32 = 117440512;
pub const SPI_SETUP_TIME_1SCK: u32 = 0;
pub const SPI_SETUP_TIME_2SCK: u32 = 1048576;
pub const SPI_SETUP_TIME_3SCK: u32 = 2097152;
pub const SPI_SETUP_TIME_4SCK: u32 = 3145728;
pub const SPI_SETUP_TIME_5SCK: u32 = 4194304;
pub const SPI_SETUP_TIME_6SCK: u32 = 5242880;
pub const SPI_SETUP_TIME_7SCK: u32 = 6291456;
pub const SPI_SETUP_TIME_8SCK: u32 = 7340032;
pub const SPI_COM_SUSP_FUNC_OFF: u32 = 0;
pub const SPI_COM_SUSP_FUNC_ON: u32 = 128;
pub const SPI_MD_0: u32 = 0;
pub const SPI_MD_1: u32 = 1;
pub const SPI_MD_2: u32 = 2;
pub const SPI_MD_3: u32 = 3;
pub const SPI_SCK_POLARITY_LOW: u32 = 0;
pub const SPI_SCK_POLARITY_HIGH: u32 = 2;
pub const SPI_SCK_PHASE_ODD_EDGE_SAMPLE: u32 = 0;
pub const SPI_SCK_PHASE_EVEN_EDGE_SAMPLE: u32 = 1;
pub const SPI_BR_CLK_DIV2: u32 = 0;
pub const SPI_BR_CLK_DIV4: u32 = 4;
pub const SPI_BR_CLK_DIV8: u32 = 8;
pub const SPI_BR_CLK_DIV16: u32 = 12;
pub const SPI_BR_CLK_DIV32: u32 = 16;
pub const SPI_BR_CLK_DIV64: u32 = 20;
pub const SPI_BR_CLK_DIV128: u32 = 24;
pub const SPI_BR_CLK_DIV256: u32 = 28;
pub const SPI_DATA_SIZE_4BIT: u32 = 0;
pub const SPI_DATA_SIZE_5BIT: u32 = 256;
pub const SPI_DATA_SIZE_6BIT: u32 = 512;
pub const SPI_DATA_SIZE_7BIT: u32 = 768;
pub const SPI_DATA_SIZE_8BIT: u32 = 1024;
pub const SPI_DATA_SIZE_9BIT: u32 = 1280;
pub const SPI_DATA_SIZE_10BIT: u32 = 1536;
pub const SPI_DATA_SIZE_11BIT: u32 = 1792;
pub const SPI_DATA_SIZE_12BIT: u32 = 2048;
pub const SPI_DATA_SIZE_13BIT: u32 = 2304;
pub const SPI_DATA_SIZE_14BIT: u32 = 2560;
pub const SPI_DATA_SIZE_15BIT: u32 = 2816;
pub const SPI_DATA_SIZE_16BIT: u32 = 3072;
pub const SPI_DATA_SIZE_20BIT: u32 = 3328;
pub const SPI_DATA_SIZE_24BIT: u32 = 3584;
pub const SPI_DATA_SIZE_32BIT: u32 = 3840;
pub const SPI_FIRST_MSB: u32 = 0;
pub const SPI_FIRST_LSB: u32 = 4096;
pub const SPI_FLAG_OVERRUN: u32 = 1;
pub const SPI_FLAG_IDLE: u32 = 2;
pub const SPI_FLAG_MD_FAULT: u32 = 4;
pub const SPI_FLAG_PARITY_ERR: u32 = 8;
pub const SPI_FLAG_UNDERRUN: u32 = 16;
pub const SPI_FLAG_TX_BUF_EMPTY: u32 = 32;
pub const SPI_FLAG_RX_BUF_FULL: u32 = 128;
pub const SPI_FLAG_CLR_ALL: u32 = 29;
pub const SPI_FLAG_ALL: u32 = 191;
pub const SRAM_SRAMH: u32 = 4;
pub const SRAM_SRAM12: u32 = 1;
pub const SRAM_SRAM3: u32 = 2;
pub const SRAM_SRAMR: u32 = 8;
pub const SRAM_SRAM_ALL: u32 = 15;
pub const SRAM_ECC_SRAM3: u32 = 1;
pub const SRAM_ECC_SRAM_ALL: u32 = 1;
pub const SRAM_WAIT_CYCLE0: u32 = 0;
pub const SRAM_WAIT_CYCLE1: u32 = 1;
pub const SRAM_WAIT_CYCLE2: u32 = 2;
pub const SRAM_WAIT_CYCLE3: u32 = 3;
pub const SRAM_WAIT_CYCLE4: u32 = 4;
pub const SRAM_WAIT_CYCLE5: u32 = 5;
pub const SRAM_WAIT_CYCLE6: u32 = 6;
pub const SRAM_WAIT_CYCLE7: u32 = 7;
pub const SRAM_EXP_TYPE_NMI: u32 = 0;
pub const SRAM_EXP_TYPE_RST: u32 = 1;
pub const SRAM_CHECK_SRAM3: u32 = 65536;
pub const SRAM_CHECK_SRAMH_1_2_B: u32 = 1;
pub const SRAM_CHECK_SRAM_ALL: u32 = 65537;
pub const SRAM_SRAM3_ECC_INVD: u32 = 0;
pub const SRAM_SRAM3_ECC_MD1: u32 = 16777216;
pub const SRAM_SRAM3_ECC_MD2: u32 = 33554432;
pub const SRAM_SRAM3_ECC_MD3: u32 = 50331648;
pub const SRAM_ECC_MD_INVD: u32 = 0;
pub const SRAM_FLAG_SRAM3_1ERR: u32 = 1;
pub const SRAM_FLAG_SRAM3_2ERR: u32 = 2;
pub const SRAM_FLAG_SRAM12_PYERR: u32 = 4;
pub const SRAM_FLAG_SRAMH_PYERR: u32 = 8;
pub const SRAM_FLAG_SRAMR_PYERR: u32 = 16;
pub const SRAM_FLAG_ALL: u32 = 31;
pub const SRAM_REG_LOCK_KEY: u32 = 118;
pub const SRAM_REG_UNLOCK_KEY: u32 = 119;
pub const SWDT_FLAG_UDF: u32 = 65536;
pub const SWDT_FLAG_REFRESH: u32 = 131072;
pub const SWDT_FLAG_ALL: u32 = 196608;
pub const TMR0_CH_A: u32 = 0;
pub const TMR0_CH_B: u32 = 1;
pub const TMR0_CLK_SRC_INTERN_CLK: u32 = 0;
pub const TMR0_CLK_SRC_SPEC_EVT: u32 = 512;
pub const TMR0_CLK_SRC_LRC: u32 = 256;
pub const TMR0_CLK_SRC_XTAL32: u32 = 1280;
pub const TMR0_CLK_DIV1: u32 = 0;
pub const TMR0_CLK_DIV2: u32 = 16;
pub const TMR0_CLK_DIV4: u32 = 32;
pub const TMR0_CLK_DIV8: u32 = 48;
pub const TMR0_CLK_DIV16: u32 = 64;
pub const TMR0_CLK_DIV32: u32 = 80;
pub const TMR0_CLK_DIV64: u32 = 96;
pub const TMR0_CLK_DIV128: u32 = 112;
pub const TMR0_CLK_DIV256: u32 = 128;
pub const TMR0_CLK_DIV512: u32 = 144;
pub const TMR0_CLK_DIV1024: u32 = 160;
pub const TMR0_FUNC_CMP: u32 = 0;
pub const TMR0_FUNC_CAPT: u32 = 32770;
pub const TMR0_INT_CMP_A: u32 = 4;
pub const TMR0_INT_CMP_B: u32 = 262144;
pub const TMR0_INT_ALL: u32 = 262148;
pub const TMR0_FLAG_CMP_A: u32 = 1;
pub const TMR0_FLAG_CMP_B: u32 = 65536;
pub const TMR0_FLAG_ALL: u32 = 65537;
pub const TMR4_CLK_SRC_INTERNCLK: u32 = 0;
pub const TMR4_CLK_SRC_EXTCLK: u32 = 32768;
pub const TMR4_CLK_DIV1: u32 = 0;
pub const TMR4_CLK_DIV2: u32 = 1;
pub const TMR4_CLK_DIV4: u32 = 2;
pub const TMR4_CLK_DIV8: u32 = 3;
pub const TMR4_CLK_DIV16: u32 = 4;
pub const TMR4_CLK_DIV32: u32 = 5;
pub const TMR4_CLK_DIV64: u32 = 6;
pub const TMR4_CLK_DIV128: u32 = 7;
pub const TMR4_CLK_DIV256: u32 = 8;
pub const TMR4_CLK_DIV512: u32 = 9;
pub const TMR4_CLK_DIV1024: u32 = 10;
pub const TMR4_MD_SAWTOOTH: u32 = 0;
pub const TMR4_MD_TRIANGLE: u32 = 32;
pub const TMR4_FLAG_RELOAD_TMR_U: u32 = 1;
pub const TMR4_FLAG_RELOAD_TMR_V: u32 = 16;
pub const TMR4_FLAG_RELOAD_TMR_W: u32 = 256;
pub const TMR4_FLAG_OC_CMP_UH: u32 = 65536;
pub const TMR4_FLAG_OC_CMP_UL: u32 = 131072;
pub const TMR4_FLAG_OC_CMP_VH: u32 = 262144;
pub const TMR4_FLAG_OC_CMP_VL: u32 = 524288;
pub const TMR4_FLAG_OC_CMP_WH: u32 = 1048576;
pub const TMR4_FLAG_OC_CMP_WL: u32 = 2097152;
pub const TMR4_INT_RELOAD_TMR_U: u32 = 1;
pub const TMR4_INT_RELOAD_TMR_V: u32 = 2;
pub const TMR4_INT_RELOAD_TMR_W: u32 = 4;
pub const TMR4_INT_OC_CMP_UH: u32 = 65536;
pub const TMR4_INT_OC_CMP_UL: u32 = 131072;
pub const TMR4_INT_OC_CMP_VH: u32 = 262144;
pub const TMR4_INT_OC_CMP_VL: u32 = 524288;
pub const TMR4_INT_OC_CMP_WH: u32 = 1048576;
pub const TMR4_INT_OC_CMP_WL: u32 = 2097152;
pub const TMR4_INT_CNT_MASK0: u32 = 0;
pub const TMR4_INT_CNT_MASK1: u32 = 1;
pub const TMR4_INT_CNT_MASK2: u32 = 2;
pub const TMR4_INT_CNT_MASK3: u32 = 3;
pub const TMR4_INT_CNT_MASK4: u32 = 4;
pub const TMR4_INT_CNT_MASK5: u32 = 5;
pub const TMR4_INT_CNT_MASK6: u32 = 6;
pub const TMR4_INT_CNT_MASK7: u32 = 7;
pub const TMR4_INT_CNT_MASK8: u32 = 8;
pub const TMR4_INT_CNT_MASK9: u32 = 9;
pub const TMR4_INT_CNT_MASK10: u32 = 10;
pub const TMR4_INT_CNT_MASK11: u32 = 11;
pub const TMR4_INT_CNT_MASK12: u32 = 12;
pub const TMR4_INT_CNT_MASK13: u32 = 13;
pub const TMR4_INT_CNT_MASK14: u32 = 14;
pub const TMR4_INT_CNT_MASK15: u32 = 15;
pub const TMR4_OC_CH_UH: u32 = 0;
pub const TMR4_OC_CH_UL: u32 = 1;
pub const TMR4_OC_CH_VH: u32 = 2;
pub const TMR4_OC_CH_VL: u32 = 3;
pub const TMR4_OC_CH_WH: u32 = 4;
pub const TMR4_OC_CH_WL: u32 = 5;
pub const TMR4_OC_INVD_LOW: u32 = 0;
pub const TMR4_OC_INVD_HIGH: u32 = 4;
pub const TMR4_OC_PORT_LOW: u32 = 0;
pub const TMR4_OC_PORT_HIGH: u32 = 4;
pub const TMR4_OC_BUF_NONE: u32 = 0;
pub const TMR4_OC_BUF_CMP_VALUE: u32 = 1;
pub const TMR4_OC_BUF_CMP_MD: u32 = 2;
pub const TMR4_OC_BUF_COND_IMMED: u32 = 0;
pub const TMR4_OC_BUF_COND_VALLEY: u32 = 1;
pub const TMR4_OC_BUF_COND_PEAK: u32 = 2;
pub const TMR4_OC_BUF_COND_PEAK_VALLEY: u32 = 3;
pub const TMR4_OC_OCF_HOLD: u32 = 0;
pub const TMR4_OC_OCF_SET: u32 = 1;
pub const TMR4_OC_HOLD: u32 = 0;
pub const TMR4_OC_HIGH: u32 = 1;
pub const TMR4_OC_LOW: u32 = 2;
pub const TMR4_OC_INVT: u32 = 3;
pub const TMR4_PWM_CH_U: u32 = 0;
pub const TMR4_PWM_CH_V: u32 = 1;
pub const TMR4_PWM_CH_W: u32 = 2;
pub const TMR4_PWM_PIN_OUH: u32 = 0;
pub const TMR4_PWM_PIN_OUL: u32 = 1;
pub const TMR4_PWM_PIN_OVH: u32 = 2;
pub const TMR4_PWM_PIN_OVL: u32 = 3;
pub const TMR4_PWM_PIN_OWH: u32 = 4;
pub const TMR4_PWM_PIN_OWL: u32 = 5;
pub const TMR4_PWM_CLK_DIV1: u32 = 0;
pub const TMR4_PWM_CLK_DIV2: u32 = 1;
pub const TMR4_PWM_CLK_DIV4: u32 = 2;
pub const TMR4_PWM_CLK_DIV8: u32 = 3;
pub const TMR4_PWM_CLK_DIV16: u32 = 4;
pub const TMR4_PWM_CLK_DIV32: u32 = 5;
pub const TMR4_PWM_CLK_DIV64: u32 = 6;
pub const TMR4_PWM_CLK_DIV128: u32 = 7;
pub const TMR4_PWM_MD_THROUGH: u32 = 0;
pub const TMR4_PWM_MD_DEAD_TMR: u32 = 16;
pub const TMR4_PWM_MD_DEAD_TMR_FILTER: u32 = 32;
pub const TMR4_PWM_OXH_HOLD_OXL_HOLD: u32 = 0;
pub const TMR4_PWM_OXH_INVT_OXL_INVT: u32 = 64;
pub const TMR4_PWM_OXH_INVT_OXL_HOLD: u32 = 128;
pub const TMR4_PWM_OXH_HOLD_OXL_INVT: u32 = 192;
pub const TMR4_PWM_PDAR_IDX: u32 = 0;
pub const TMR4_PWM_PDBR_IDX: u32 = 1;
pub const TMR4_PWM_ABNORMAL_PIN_NORMAL: u32 = 0;
pub const TMR4_PWM_ABNORMAL_PIN_HIZ: u32 = 1;
pub const TMR4_PWM_ABNORMAL_PIN_LOW: u32 = 2;
pub const TMR4_PWM_ABNORMAL_PIN_HIGH: u32 = 3;
pub const TMR4_PWM_ABNORMAL_PIN_HOLD: u32 = 4;
pub const TMR4_EVT_CH_UH: u32 = 0;
pub const TMR4_EVT_CH_UL: u32 = 1;
pub const TMR4_EVT_CH_VH: u32 = 2;
pub const TMR4_EVT_CH_VL: u32 = 3;
pub const TMR4_EVT_CH_WH: u32 = 4;
pub const TMR4_EVT_CH_WL: u32 = 5;
pub const TMR4_EVT_MATCH_CNT_UP: u32 = 16384;
pub const TMR4_EVT_MATCH_CNT_DOWN: u32 = 4096;
pub const TMR4_EVT_MATCH_CNT_PEAK: u32 = 8192;
pub const TMR4_EVT_MATCH_CNT_VALLEY: u32 = 32768;
pub const TMR4_EVT_MATCH_CNT_ALL: u32 = 61440;
pub const TMR4_EVT_MASK_PEAK: u32 = 128;
pub const TMR4_EVT_MASK_VALLEY: u32 = 64;
pub const TMR4_EVT_MASK_TYPE_ALL: u32 = 192;
pub const TMR4_EVT_BUF_COND_IMMED: u32 = 0;
pub const TMR4_EVT_BUF_COND_VALLEY: u32 = 1;
pub const TMR4_EVT_BUF_COND_PEAK: u32 = 2;
pub const TMR4_EVT_BUF_COND_PEAK_VALLEY: u32 = 3;
pub const TMR4_EVT_MD_CMP: u32 = 0;
pub const TMR4_EVT_MD_DELAY: u32 = 256;
pub const TMR4_EVT_DELAY_OCCRXH: u32 = 0;
pub const TMR4_EVT_DELAY_OCCRXL: u32 = 512;
pub const TMR4_EVT_MASK0: u32 = 0;
pub const TMR4_EVT_MASK1: u32 = 1;
pub const TMR4_EVT_MASK2: u32 = 2;
pub const TMR4_EVT_MASK3: u32 = 3;
pub const TMR4_EVT_MASK4: u32 = 4;
pub const TMR4_EVT_MASK5: u32 = 5;
pub const TMR4_EVT_MASK6: u32 = 6;
pub const TMR4_EVT_MASK7: u32 = 7;
pub const TMR4_EVT_MASK8: u32 = 8;
pub const TMR4_EVT_MASK9: u32 = 9;
pub const TMR4_EVT_MASK10: u32 = 10;
pub const TMR4_EVT_MASK11: u32 = 11;
pub const TMR4_EVT_MASK12: u32 = 12;
pub const TMR4_EVT_MASK13: u32 = 13;
pub const TMR4_EVT_MASK14: u32 = 14;
pub const TMR4_EVT_MASK15: u32 = 15;
pub const TMR4_EVT_OUTPUT_EVT0: u32 = 0;
pub const TMR4_EVT_OUTPUT_EVT1: u32 = 4;
pub const TMR4_EVT_OUTPUT_EVT2: u32 = 8;
pub const TMR4_EVT_OUTPUT_EVT3: u32 = 12;
pub const TMR4_EVT_OUTPUT_EVT4: u32 = 16;
pub const TMR4_EVT_OUTPUT_EVT5: u32 = 20;
pub const TMR4_EVT_OUTPUT_NONE: u32 = 0;
pub const TMR4_EVT_OUTPUT_EVT0_SIGNAL: u32 = 1;
pub const TMR4_EVT_OUTPUT_EVT1_SIGNAL: u32 = 2;
pub const TMR4_EVT_OUTPUT_EVT2_SIGNAL: u32 = 3;
pub const TMR4_EVT_OUTPUT_EVT3_SIGNAL: u32 = 4;
pub const TMR4_EVT_OUTPUT_EVT4_SIGNAL: u32 = 5;
pub const TMR4_EVT_OUTPUT_EVT5_SIGNAL: u32 = 6;
pub const TMR6_CNT_SRC_SW: u32 = 0;
pub const TMR6_CNT_SRC_HW: u32 = 1;
pub const TMR6_FLAG_MATCH_A: u32 = 1;
pub const TMR6_FLAG_MATCH_B: u32 = 2;
pub const TMR6_FLAG_MATCH_C: u32 = 4;
pub const TMR6_FLAG_MATCH_D: u32 = 8;
pub const TMR6_FLAG_MATCH_E: u32 = 16;
pub const TMR6_FLAG_MATCH_F: u32 = 32;
pub const TMR6_FLAG_OVF: u32 = 64;
pub const TMR6_FLAG_UDF: u32 = 128;
pub const TMR6_FLAG_DEAD_TIME_ERR: u32 = 256;
pub const TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A: u32 = 512;
pub const TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A: u32 = 1024;
pub const TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B: u32 = 2048;
pub const TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B: u32 = 4096;
pub const TMR6_FLAG_CNT_DIR: u32 = 2147483648;
pub const TMR6_FLAG_CLR_ALL: u32 = 7935;
pub const TMR6_FLAG_ALL: u32 = 2147491839;
pub const TMR6_INT_MATCH_A: u32 = 1;
pub const TMR6_INT_MATCH_B: u32 = 2;
pub const TMR6_INT_MATCH_C: u32 = 4;
pub const TMR6_INT_MATCH_D: u32 = 8;
pub const TMR6_INT_MATCH_E: u32 = 16;
pub const TMR6_INT_MATCH_F: u32 = 32;
pub const TMR6_INT_OVF: u32 = 64;
pub const TMR6_INT_UDF: u32 = 128;
pub const TMR6_INT_DEAD_TIME_ERR: u32 = 256;
pub const TMR6_INT_UP_CNT_SPECIAL_MATCH_A: u32 = 65536;
pub const TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A: u32 = 131072;
pub const TMR6_INT_UP_CNT_SPECIAL_MATCH_B: u32 = 262144;
pub const TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B: u32 = 524288;
pub const TMR6_INT_ALL: u32 = 983551;
pub const TMR6_PERIOD_REG_A: u32 = 0;
pub const TMR6_PERIOD_REG_B: u32 = 1;
pub const TMR6_PERIOD_REG_C: u32 = 2;
pub const TMR6_CMP_REG_A: u32 = 0;
pub const TMR6_CMP_REG_B: u32 = 1;
pub const TMR6_CMP_REG_C: u32 = 2;
pub const TMR6_CMP_REG_D: u32 = 3;
pub const TMR6_CMP_REG_E: u32 = 4;
pub const TMR6_CMP_REG_F: u32 = 5;
pub const TMR6_CH_A: u32 = 0;
pub const TMR6_CH_B: u32 = 1;
pub const TMR6_BUF_SINGLE: u32 = 0;
pub const TMR6_BUF_DUAL: u32 = 2;
pub const TMR6_BUF_TRANS_INVD: u32 = 0;
pub const TMR6_BUF_TRANS_OVF: u32 = 4;
pub const TMR6_BUF_TRANS_UDF: u32 = 8;
pub const TMR6_BUF_TRANS_OVF_UDF: u32 = 12;
pub const TMR6_VALID_PERIOD_INVD: u32 = 0;
pub const TMR6_VALID_PERIOD_CNT_COND_VALLEY: u32 = 65536;
pub const TMR6_VALID_PERIOD_CNT_COND_PEAK: u32 = 131072;
pub const TMR6_VALID_PERIOD_CNT_COND_VALLEY_PEAK: u32 = 196608;
pub const TMR6_VALID_PERIOD_CNT_INVD: u32 = 0;
pub const TMR6_VALID_PERIOD_CNT1: u32 = 262144;
pub const TMR6_VALID_PERIOD_CNT2: u32 = 524288;
pub const TMR6_VALID_PERIOD_CNT3: u32 = 786432;
pub const TMR6_VALID_PERIOD_CNT4: u32 = 1048576;
pub const TMR6_VALID_PERIOD_CNT5: u32 = 1310720;
pub const TMR6_VALID_PERIOD_CNT6: u32 = 1572864;
pub const TMR6_VALID_PERIOD_CNT7: u32 = 1835008;
pub const TMR6_DEADTIME_REG_UP_A: u32 = 0;
pub const TMR6_DEADTIME_REG_DOWN_A: u32 = 1;
pub const TMR6_DEADTIME_REG_UP_B: u32 = 2;
pub const TMR6_DEADTIME_REG_DOWN_B: u32 = 3;
pub const TMR6_IO_PWMA: u32 = 0;
pub const TMR6_IO_PWMB: u32 = 1;
pub const TMR6_INPUT_TRIGA: u32 = 2;
pub const TMR6_INPUT_TRIGB: u32 = 3;
pub const TMR6_FILTER_CLK_DIV1: u32 = 0;
pub const TMR6_FILTER_CLK_DIV4: u32 = 1;
pub const TMR6_FILTER_CLK_DIV16: u32 = 2;
pub const TMR6_FILTER_CLK_DIV64: u32 = 3;
pub const TMR6_PIN_CMP_OUTPUT: u32 = 0;
pub const TMR6_PIN_CAPT_INPUT: u32 = 1;
pub const TMR6_STAT_START: u32 = 0;
pub const TMR6_STAT_STOP: u32 = 1;
pub const TMR6_STAT_MATCH_CMP: u32 = 2;
pub const TMR6_STAT_MATCH_PERIOD: u32 = 3;
pub const TMR6_PWM_LOW: u32 = 0;
pub const TMR6_PWM_HIGH: u32 = 1;
pub const TMR6_PWM_HOLD: u32 = 2;
pub const TMR6_PWM_INVT: u32 = 3;
pub const TMR6_PWM_START_STOP_HOLD: u32 = 8;
pub const TMR6_PWM_START_STOP_CHANGE: u32 = 0;
pub const TMR6_EMB_PIN_NORMAL: u32 = 0;
pub const TMR6_EMB_PIN_HIZ: u32 = 2048;
pub const TMR6_EMB_PIN_LOW: u32 = 4096;
pub const TMR6_EMB_PIN_HIGH: u32 = 6144;
pub const TMR6_DEADTIME_CNT_UP_BUF_OFF: u32 = 0;
pub const TMR6_DEADTIME_CNT_UP_BUF_ON: u32 = 16;
pub const TMR6_DEADTIME_CNT_DOWN_BUF_OFF: u32 = 0;
pub const TMR6_DEADTIME_CNT_DOWN_BUF_ON: u32 = 32;
pub const TMR6_DEADTIME_EQUAL_OFF: u32 = 0;
pub const TMR6_DEADTIME_EQUAL_ON: u32 = 256;
pub const TMR6_SW_SYNC_U1: u32 = 1;
pub const TMR6_SW_SYNC_U2: u32 = 2;
pub const TMR6_SW_SYNC_U3: u32 = 4;
pub const TMR6_SW_SYNC_ALL: u32 = 7;
pub const TMR6_START_COND_EVT0: u32 = 1;
pub const TMR6_START_COND_EVT1: u32 = 2;
pub const TMR6_START_COND_PWMA_RISING: u32 = 16;
pub const TMR6_START_COND_PWMA_FALLING: u32 = 32;
pub const TMR6_START_COND_PWMB_RISING: u32 = 64;
pub const TMR6_START_COND_PWMB_FALLING: u32 = 128;
pub const TMR6_START_COND_TRIGA_RISING: u32 = 256;
pub const TMR6_START_COND_TRIGA_FALLING: u32 = 512;
pub const TMR6_START_COND_TRIGB_RISING: u32 = 1024;
pub const TMR6_START_COND_TRIGB_FALLING: u32 = 2048;
pub const TMR6_START_COND_ALL: u32 = 4083;
pub const TMR6_STOP_COND_EVT0: u32 = 1;
pub const TMR6_STOP_COND_EVT1: u32 = 2;
pub const TMR6_STOP_COND_PWMA_RISING: u32 = 16;
pub const TMR6_STOP_COND_PWMA_FALLING: u32 = 32;
pub const TMR6_STOP_COND_PWMB_RISING: u32 = 64;
pub const TMR6_STOP_COND_PWMB_FALLING: u32 = 128;
pub const TMR6_STOP_COND_TRIGA_RISING: u32 = 256;
pub const TMR6_STOP_COND_TRIGA_FALLING: u32 = 512;
pub const TMR6_STOP_COND_TRIGB_RISING: u32 = 1024;
pub const TMR6_STOP_COND_TRIGB_FALLING: u32 = 2048;
pub const TMR6_STOP_COND_ALL: u32 = 4083;
pub const TMR6_CLR_COND_EVT0: u32 = 1;
pub const TMR6_CLR_COND_EVT1: u32 = 2;
pub const TMR6_CLR_COND_PWMA_RISING: u32 = 16;
pub const TMR6_CLR_COND_PWMA_FALLING: u32 = 32;
pub const TMR6_CLR_COND_PWMB_RISING: u32 = 64;
pub const TMR6_CLR_COND_PWMB_FALLING: u32 = 128;
pub const TMR6_CLR_COND_TRIGA_RISING: u32 = 256;
pub const TMR6_CLR_COND_TRIGA_FALLING: u32 = 512;
pub const TMR6_CLR_COND_TRIGB_RISING: u32 = 1024;
pub const TMR6_CLR_COND_TRIGB_FALLING: u32 = 2048;
pub const TMR6_CLR_COND_ALL: u32 = 4083;
pub const TMR6_CAPT_COND_EVT0: u32 = 1;
pub const TMR6_CAPT_COND_EVT1: u32 = 2;
pub const TMR6_CAPT_COND_PWMA_RISING: u32 = 16;
pub const TMR6_CAPT_COND_PWMA_FALLING: u32 = 32;
pub const TMR6_CAPT_COND_PWMB_RISING: u32 = 64;
pub const TMR6_CAPT_COND_PWMB_FALLING: u32 = 128;
pub const TMR6_CAPT_COND_TRIGA_RISING: u32 = 256;
pub const TMR6_CAPT_COND_TRIGA_FALLING: u32 = 512;
pub const TMR6_CAPT_COND_TRIGB_RISING: u32 = 1024;
pub const TMR6_CAPT_COND_TRIGB_FALLING: u32 = 2048;
pub const TMR6_CAPT_COND_ALL: u32 = 4083;
pub const TMR6_CNT_UP_COND_INVD: u32 = 0;
pub const TMR6_CNT_UP_COND_PWMA_LOW_PWMB_RISING: u32 = 1;
pub const TMR6_CNT_UP_COND_PWMA_LOW_PWMB_FALLING: u32 = 2;
pub const TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING: u32 = 4;
pub const TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_FALLING: u32 = 8;
pub const TMR6_CNT_UP_COND_PWMB_LOW_PWMA_RISING: u32 = 16;
pub const TMR6_CNT_UP_COND_PWMB_LOW_PWMA_FALLING: u32 = 32;
pub const TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_RISING: u32 = 64;
pub const TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_FALLING: u32 = 128;
pub const TMR6_CNT_UP_COND_TRIGA_RISING: u32 = 256;
pub const TMR6_CNT_UP_COND_TRIGA_FALLING: u32 = 512;
pub const TMR6_CNT_UP_COND_TRIGB_RISING: u32 = 1024;
pub const TMR6_CNT_UP_COND_TRIGB_FALLING: u32 = 2048;
pub const TMR6_CNT_UP_COND_EVT0: u32 = 65536;
pub const TMR6_CNT_UP_COND_EVT1: u32 = 131072;
pub const TMR6_CNT_UP_COND_ALL: u32 = 200703;
pub const TMR6_CNT_DOWN_COND_INVD: u32 = 0;
pub const TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_RISING: u32 = 1;
pub const TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_FALLING: u32 = 2;
pub const TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_RISING: u32 = 4;
pub const TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_FALLING: u32 = 8;
pub const TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_RISING: u32 = 16;
pub const TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_FALLING: u32 = 32;
pub const TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING: u32 = 64;
pub const TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_FALLING: u32 = 128;
pub const TMR6_CNT_DOWN_COND_TRIGA_RISING: u32 = 256;
pub const TMR6_CNT_DOWN_COND_TRIGA_FALLING: u32 = 512;
pub const TMR6_CNT_DOWN_COND_TRIGB_RISING: u32 = 1024;
pub const TMR6_CNT_DOWN_COND_TRIGB_FALLING: u32 = 2048;
pub const TMR6_CNT_DOWN_COND_EVT0: u32 = 65536;
pub const TMR6_CNT_DOWN_COND_EVT1: u32 = 131072;
pub const TMR6_CNT_DOWN_COND_ALL: u32 = 200703;
pub const TMR6_CNT_UP: u32 = 256;
pub const TMR6_CNT_DOWN: u32 = 0;
pub const TMR6_STAT_CNT_UP: u32 = 2147483648;
pub const TMR6_STAT_CNT_DOWN: u32 = 0;
pub const TMR6_MD_SAWTOOTH: u32 = 0;
pub const TMR6_MD_TRIANGLE_A: u32 = 8;
pub const TMR6_MD_TRIANGLE_B: u32 = 10;
pub const TMR6_CLK_DIV1: u32 = 0;
pub const TMR6_CLK_DIV2: u32 = 16;
pub const TMR6_CLK_DIV4: u32 = 32;
pub const TMR6_CLK_DIV8: u32 = 48;
pub const TMR6_CLK_DIV16: u32 = 64;
pub const TMR6_CLK_DIV64: u32 = 80;
pub const TMR6_CLK_DIV256: u32 = 96;
pub const TMR6_CLK_DIV1024: u32 = 112;
pub const TMR6_ZMASK_FUNC_INVD: u32 = 0;
pub const TMR6_ZMASK_CYCLE_4: u32 = 262144;
pub const TMR6_ZMASK_CYCLE_8: u32 = 524288;
pub const TMR6_ZMASK_CYCLE_16: u32 = 786432;
pub const TMR6_POS_CLR_ZMASK_FUNC_OFF: u32 = 0;
pub const TMR6_POS_CLR_ZMASK_FUNC_ON: u32 = 131072;
pub const TMR6_REVO_CNT_ZMASK_FUNC_OFF: u32 = 0;
pub const TMR6_REVO_CNT_ZMASK_FUNC_ON: u32 = 65536;
pub const TMRA_CNT_SRC_SW: u32 = 0;
pub const TMRA_CNT_SRC_HW: u32 = 1;
pub const TMRA_CH1: u32 = 0;
pub const TMRA_CH2: u32 = 1;
pub const TMRA_CH3: u32 = 2;
pub const TMRA_CH4: u32 = 3;
pub const TMRA_CH5: u32 = 4;
pub const TMRA_CH6: u32 = 5;
pub const TMRA_CH7: u32 = 6;
pub const TMRA_CH8: u32 = 7;
pub const TMRA_DIR_DOWN: u32 = 0;
pub const TMRA_DIR_UP: u32 = 2;
pub const TMRA_MD_SAWTOOTH: u32 = 0;
pub const TMRA_MD_TRIANGLE: u32 = 4;
pub const TMRA_FUNC_CMP: u32 = 0;
pub const TMRA_FUNC_CAPT: u32 = 1;
pub const TMRA_CLK_DIV1: u32 = 0;
pub const TMRA_CLK_DIV2: u32 = 16;
pub const TMRA_CLK_DIV4: u32 = 32;
pub const TMRA_CLK_DIV8: u32 = 48;
pub const TMRA_CLK_DIV16: u32 = 64;
pub const TMRA_CLK_DIV32: u32 = 80;
pub const TMRA_CLK_DIV64: u32 = 96;
pub const TMRA_CLK_DIV128: u32 = 112;
pub const TMRA_CLK_DIV256: u32 = 128;
pub const TMRA_CLK_DIV512: u32 = 144;
pub const TMRA_CLK_DIV1024: u32 = 160;
pub const TMRA_PIN_TRIG: u32 = 0;
pub const TMRA_PIN_CLKA: u32 = 1;
pub const TMRA_PIN_CLKB: u32 = 2;
pub const TMRA_PIN_PWM1: u32 = 3;
pub const TMRA_PIN_PWM2: u32 = 4;
pub const TMRA_PIN_PWM3: u32 = 5;
pub const TMRA_PIN_PWM4: u32 = 6;
pub const TMRA_PIN_PWM5: u32 = 7;
pub const TMRA_PIN_PWM6: u32 = 8;
pub const TMRA_PIN_PWM7: u32 = 9;
pub const TMRA_PIN_PWM8: u32 = 10;
pub const TMRA_CNT_UP_COND_INVD: u32 = 0;
pub const TMRA_CNT_UP_COND_CLKA_LOW_CLKB_RISING: u32 = 1;
pub const TMRA_CNT_UP_COND_CLKA_LOW_CLKB_FALLING: u32 = 2;
pub const TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING: u32 = 4;
pub const TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_FALLING: u32 = 8;
pub const TMRA_CNT_UP_COND_CLKB_LOW_CLKA_RISING: u32 = 16;
pub const TMRA_CNT_UP_COND_CLKB_LOW_CLKA_FALLING: u32 = 32;
pub const TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_RISING: u32 = 64;
pub const TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_FALLING: u32 = 128;
pub const TMRA_CNT_UP_COND_TRIG_RISING: u32 = 256;
pub const TMRA_CNT_UP_COND_TRIG_FALLING: u32 = 512;
pub const TMRA_CNT_UP_COND_EVT: u32 = 1024;
pub const TMRA_CNT_UP_COND_SYM_OVF: u32 = 2048;
pub const TMRA_CNT_UP_COND_SYM_UDF: u32 = 4096;
pub const TMRA_CNT_UP_COND_ALL: u32 = 8191;
pub const TMRA_CNT_DOWN_COND_INVD: u32 = 0;
pub const TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_RISING: u32 = 1;
pub const TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_FALLING: u32 = 2;
pub const TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_RISING: u32 = 4;
pub const TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_FALLING: u32 = 8;
pub const TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_RISING: u32 = 16;
pub const TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_FALLING: u32 = 32;
pub const TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING: u32 = 64;
pub const TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_FALLING: u32 = 128;
pub const TMRA_CNT_DOWN_COND_TRIG_RISING: u32 = 256;
pub const TMRA_CNT_DOWN_COND_TRIG_FALLING: u32 = 512;
pub const TMRA_CNT_DOWN_COND_EVT: u32 = 1024;
pub const TMRA_CNT_DOWN_COND_SYM_OVF: u32 = 2048;
pub const TMRA_CNT_DOWN_COND_SYM_UDF: u32 = 4096;
pub const TMRA_CNT_DOWN_COND_ALL: u32 = 8191;
pub const TMRA_INT_OVF: u32 = 16;
pub const TMRA_INT_UDF: u32 = 32;
pub const TMRA_INT_CMP_CH1: u32 = 65536;
pub const TMRA_INT_CMP_CH2: u32 = 131072;
pub const TMRA_INT_CMP_CH3: u32 = 262144;
pub const TMRA_INT_CMP_CH4: u32 = 524288;
pub const TMRA_INT_CMP_CH5: u32 = 1048576;
pub const TMRA_INT_CMP_CH6: u32 = 2097152;
pub const TMRA_INT_CMP_CH7: u32 = 4194304;
pub const TMRA_INT_CMP_CH8: u32 = 8388608;
pub const TMRA_INT_ALL: u32 = 16711728;
pub const TMRA_EVT_CMP_CH1: u32 = 1;
pub const TMRA_EVT_CMP_CH2: u32 = 2;
pub const TMRA_EVT_CMP_CH3: u32 = 4;
pub const TMRA_EVT_CMP_CH4: u32 = 8;
pub const TMRA_EVT_CMP_CH5: u32 = 16;
pub const TMRA_EVT_CMP_CH6: u32 = 32;
pub const TMRA_EVT_CMP_CH7: u32 = 64;
pub const TMRA_EVT_CMP_CH8: u32 = 128;
pub const TMRA_EVT_ALL: u32 = 255;
pub const TMRA_FLAG_OVF: u32 = 64;
pub const TMRA_FLAG_UDF: u32 = 128;
pub const TMRA_FLAG_CMP_CH1: u32 = 65536;
pub const TMRA_FLAG_CMP_CH2: u32 = 131072;
pub const TMRA_FLAG_CMP_CH3: u32 = 262144;
pub const TMRA_FLAG_CMP_CH4: u32 = 524288;
pub const TMRA_FLAG_CMP_CH5: u32 = 1048576;
pub const TMRA_FLAG_CMP_CH6: u32 = 2097152;
pub const TMRA_FLAG_CMP_CH7: u32 = 4194304;
pub const TMRA_FLAG_CMP_CH8: u32 = 8388608;
pub const TMRA_FLAG_ALL: u32 = 16711872;
pub const TMRA_CAPT_COND_INVD: u32 = 0;
pub const TMRA_CAPT_COND_PWM_RISING: u32 = 16;
pub const TMRA_CAPT_COND_PWM_FALLING: u32 = 32;
pub const TMRA_CAPT_COND_EVT: u32 = 64;
pub const TMRA_CAPT_COND_TRIG_RISING: u32 = 256;
pub const TMRA_CAPT_COND_TRIG_FALLING: u32 = 512;
pub const TMRA_CAPT_COND_ALL: u32 = 880;
pub const TMRA_BUF_TRANS_COND_OVF_UDF_CLR: u32 = 0;
pub const TMRA_BUF_TRANS_COND_PEAK: u32 = 2;
pub const TMRA_BUF_TRANS_COND_VALLEY: u32 = 4;
pub const TMRA_BUF_TRANS_COND_PEAK_VALLEY: u32 = 6;
pub const TMRA_FILTER_CLK_DIV1: u32 = 0;
pub const TMRA_FILTER_CLK_DIV4: u32 = 1;
pub const TMRA_FILTER_CLK_DIV16: u32 = 2;
pub const TMRA_FILTER_CLK_DIV64: u32 = 3;
pub const TMRA_CNT_STAT_START: u32 = 0;
pub const TMRA_CNT_STAT_STOP: u32 = 1;
pub const TMRA_CNT_STAT_MATCH_CMP: u32 = 2;
pub const TMRA_CNT_STAT_MATCH_PERIOD: u32 = 3;
pub const TMRA_PWM_LOW: u32 = 0;
pub const TMRA_PWM_HIGH: u32 = 1;
pub const TMRA_PWM_HOLD: u32 = 2;
pub const TMRA_PWM_INVT: u32 = 3;
pub const TMRA_PWM_FORCE_INVD: u32 = 0;
pub const TMRA_PWM_FORCE_LOW: u32 = 512;
pub const TMRA_PWM_FORCE_HIGH: u32 = 768;
pub const TMRA_START_COND_INVD: u32 = 0;
pub const TMRA_START_COND_TRIG_RISING: u32 = 1;
pub const TMRA_START_COND_TRIG_FALLING: u32 = 2;
pub const TMRA_START_COND_EVT: u32 = 4;
pub const TMRA_START_COND_ALL: u32 = 7;
pub const TMRA_STOP_COND_INVD: u32 = 0;
pub const TMRA_STOP_COND_TRIG_RISING: u32 = 16;
pub const TMRA_STOP_COND_TRIG_FALLING: u32 = 32;
pub const TMRA_STOP_COND_EVT: u32 = 64;
pub const TMRA_STOP_COND_ALL: u32 = 112;
pub const TMRA_CLR_COND_INVD: u32 = 0;
pub const TMRA_CLR_COND_TRIG_RISING: u32 = 256;
pub const TMRA_CLR_COND_TRIG_FALLING: u32 = 512;
pub const TMRA_CLR_COND_EVT: u32 = 1024;
pub const TMRA_CLR_COND_SYM_TRIG_RISING: u32 = 4096;
pub const TMRA_CLR_COND_SYM_TRIG_FALLING: u32 = 8192;
pub const TMRA_CLR_COND_PWM3_RISING: u32 = 16384;
pub const TMRA_CLR_COND_PWM3_FALLING: u32 = 32768;
pub const TMRA_CLR_COND_ALL: u32 = 63232;
pub const TRNG_RELOAD_INIT_VAL_ENABLE: u32 = 1;
pub const TRNG_RELOAD_INIT_VAL_DISABLE: u32 = 0;
pub const TRNG_SHIFT_CNT32: u32 = 12;
pub const TRNG_SHIFT_CNT64: u32 = 16;
pub const TRNG_SHIFT_CNT128: u32 = 20;
pub const TRNG_SHIFT_CNT256: u32 = 24;
pub const USART_FLAG_RX_FULL: u32 = 32;
pub const USART_FLAG_OVERRUN: u32 = 8;
pub const USART_FLAG_TX_CPLT: u32 = 64;
pub const USART_FLAG_TX_EMPTY: u32 = 128;
pub const USART_FLAG_FRAME_ERR: u32 = 2;
pub const USART_FLAG_PARITY_ERR: u32 = 1;
pub const USART_FLAG_MX_PROCESSOR: u32 = 65536;
pub const USART_FLAG_RX_TIMEOUT: u32 = 256;
pub const USART_FLAG_ALL: u32 = 66027;
pub const USART_TRANS_DATA: u32 = 0;
pub const USART_TRANS_ID: u32 = 512;
pub const USART_TX: u32 = 8;
pub const USART_RX: u32 = 4;
pub const USART_INT_RX: u32 = 32;
pub const USART_INT_TX_CPLT: u32 = 64;
pub const USART_INT_TX_EMPTY: u32 = 128;
pub const USART_RX_TIMEOUT: u32 = 1;
pub const USART_INT_RX_TIMEOUT: u32 = 2;
pub const USART_FUNC_ALL: u32 = 239;
pub const USART_PARITY_NONE: u32 = 0;
pub const USART_PARITY_EVEN: u32 = 1024;
pub const USART_PARITY_ODD: u32 = 1536;
pub const USART_DATA_WIDTH_8BIT: u32 = 0;
pub const USART_DATA_WIDTH_9BIT: u32 = 4096;
pub const USART_OVER_SAMPLE_16BIT: u32 = 0;
pub const USART_OVER_SAMPLE_8BIT: u32 = 32768;
pub const USART_FIRST_BIT_LSB: u32 = 0;
pub const USART_FIRST_BIT_MSB: u32 = 268435456;
pub const USART_START_BIT_LOW: u32 = 0;
pub const USART_START_BIT_FALLING: u32 = 2147483648;
pub const USART_CLK_SRC_INTERNCLK: u32 = 0;
pub const USART_CLK_SRC_EXTCLK: u32 = 4096;
pub const USART_CK_OUTPUT_DISABLE: u32 = 0;
pub const USART_CK_OUTPUT_ENABLE: u32 = 2048;
pub const USART_STOPBIT_1BIT: u32 = 0;
pub const USART_STOPBIT_2BIT: u32 = 8192;
pub const USART_HW_FLOWCTRL_CTS: u32 = 512;
pub const USART_HW_FLOWCTRL_RTS: u32 = 256;
pub const USART_CLK_DIV1: u32 = 0;
pub const USART_CLK_DIV4: u32 = 1;
pub const USART_CLK_DIV16: u32 = 2;
pub const USART_CLK_DIV64: u32 = 3;
pub const USART_MAX_TIMEOUT: u32 = 4294967295;
pub const USART_SC_ETU_CLK32: u32 = 0;
pub const USART_SC_ETU_CLK64: u32 = 2097152;
pub const USART_SC_ETU_CLK128: u32 = 6291456;
pub const USART_SC_ETU_CLK256: u32 = 10485760;
pub const USART_SC_ETU_CLK372: u32 = 12582912;
pub const WDT_CNT_PERIOD256: u32 = 0;
pub const WDT_CNT_PERIOD4096: u32 = 1;
pub const WDT_CNT_PERIOD16384: u32 = 2;
pub const WDT_CNT_PERIOD65536: u32 = 3;
pub const WDT_CLK_DIV4: u32 = 32;
pub const WDT_CLK_DIV64: u32 = 96;
pub const WDT_CLK_DIV128: u32 = 112;
pub const WDT_CLK_DIV256: u32 = 128;
pub const WDT_CLK_DIV512: u32 = 144;
pub const WDT_CLK_DIV1024: u32 = 160;
pub const WDT_CLK_DIV2048: u32 = 176;
pub const WDT_CLK_DIV8192: u32 = 208;
pub const WDT_RANGE_0TO25PCT: u32 = 256;
pub const WDT_RANGE_25TO50PCT: u32 = 512;
pub const WDT_RANGE_0TO50PCT: u32 = 768;
pub const WDT_RANGE_50TO75PCT: u32 = 1024;
pub const WDT_RANGE_0TO25PCT_50TO75PCT: u32 = 1280;
pub const WDT_RANGE_25TO75PCT: u32 = 1536;
pub const WDT_RANGE_0TO75PCT: u32 = 1792;
pub const WDT_RANGE_75TO100PCT: u32 = 2048;
pub const WDT_RANGE_0TO25PCT_75TO100PCT: u32 = 2304;
pub const WDT_RANGE_25TO50PCT_75TO100PCT: u32 = 2560;
pub const WDT_RANGE_0TO50PCT_75TO100PCT: u32 = 2816;
pub const WDT_RANGE_50TO100PCT: u32 = 3072;
pub const WDT_RANGE_0TO25PCT_50TO100PCT: u32 = 3328;
pub const WDT_RANGE_25TO100PCT: u32 = 3584;
pub const WDT_RANGE_0TO100PCT: u32 = 3840;
pub const WDT_LPM_CNT_CONT: u32 = 0;
pub const WDT_LPM_CNT_STOP: u32 = 65536;
pub const WDT_EXP_TYPE_INT: u32 = 0;
pub const WDT_EXP_TYPE_RST: u32 = 2147483648;
pub const WDT_FLAG_UDF: u32 = 65536;
pub const WDT_FLAG_REFRESH: u32 = 131072;
pub const WDT_FLAG_ALL: u32 = 196608;
pub const IRQn_Type_NMI_IRQn: IRQn_Type = -14;
pub const IRQn_Type_HardFault_IRQn: IRQn_Type = -13;
pub const IRQn_Type_MemManageFault_IRQn: IRQn_Type = -12;
pub const IRQn_Type_BusFault_IRQn: IRQn_Type = -11;
pub const IRQn_Type_UsageFault_IRQn: IRQn_Type = -10;
pub const IRQn_Type_SVC_IRQn: IRQn_Type = -5;
pub const IRQn_Type_DebugMonitor_IRQn: IRQn_Type = -4;
pub const IRQn_Type_PendSV_IRQn: IRQn_Type = -2;
pub const IRQn_Type_SysTick_IRQn: IRQn_Type = -1;
pub const IRQn_Type_INT000_IRQn: IRQn_Type = 0;
pub const IRQn_Type_INT001_IRQn: IRQn_Type = 1;
pub const IRQn_Type_INT002_IRQn: IRQn_Type = 2;
pub const IRQn_Type_INT003_IRQn: IRQn_Type = 3;
pub const IRQn_Type_INT004_IRQn: IRQn_Type = 4;
pub const IRQn_Type_INT005_IRQn: IRQn_Type = 5;
pub const IRQn_Type_INT006_IRQn: IRQn_Type = 6;
pub const IRQn_Type_INT007_IRQn: IRQn_Type = 7;
pub const IRQn_Type_INT008_IRQn: IRQn_Type = 8;
pub const IRQn_Type_INT009_IRQn: IRQn_Type = 9;
pub const IRQn_Type_INT010_IRQn: IRQn_Type = 10;
pub const IRQn_Type_INT011_IRQn: IRQn_Type = 11;
pub const IRQn_Type_INT012_IRQn: IRQn_Type = 12;
pub const IRQn_Type_INT013_IRQn: IRQn_Type = 13;
pub const IRQn_Type_INT014_IRQn: IRQn_Type = 14;
pub const IRQn_Type_INT015_IRQn: IRQn_Type = 15;
pub const IRQn_Type_INT016_IRQn: IRQn_Type = 16;
pub const IRQn_Type_INT017_IRQn: IRQn_Type = 17;
pub const IRQn_Type_INT018_IRQn: IRQn_Type = 18;
pub const IRQn_Type_INT019_IRQn: IRQn_Type = 19;
pub const IRQn_Type_INT020_IRQn: IRQn_Type = 20;
pub const IRQn_Type_INT021_IRQn: IRQn_Type = 21;
pub const IRQn_Type_INT022_IRQn: IRQn_Type = 22;
pub const IRQn_Type_INT023_IRQn: IRQn_Type = 23;
pub const IRQn_Type_INT024_IRQn: IRQn_Type = 24;
pub const IRQn_Type_INT025_IRQn: IRQn_Type = 25;
pub const IRQn_Type_INT026_IRQn: IRQn_Type = 26;
pub const IRQn_Type_INT027_IRQn: IRQn_Type = 27;
pub const IRQn_Type_INT028_IRQn: IRQn_Type = 28;
pub const IRQn_Type_INT029_IRQn: IRQn_Type = 29;
pub const IRQn_Type_INT030_IRQn: IRQn_Type = 30;
pub const IRQn_Type_INT031_IRQn: IRQn_Type = 31;
pub const IRQn_Type_INT032_IRQn: IRQn_Type = 32;
pub const IRQn_Type_INT033_IRQn: IRQn_Type = 33;
pub const IRQn_Type_INT034_IRQn: IRQn_Type = 34;
pub const IRQn_Type_INT035_IRQn: IRQn_Type = 35;
pub const IRQn_Type_INT036_IRQn: IRQn_Type = 36;
pub const IRQn_Type_INT037_IRQn: IRQn_Type = 37;
pub const IRQn_Type_INT038_IRQn: IRQn_Type = 38;
pub const IRQn_Type_INT039_IRQn: IRQn_Type = 39;
pub const IRQn_Type_INT040_IRQn: IRQn_Type = 40;
pub const IRQn_Type_INT041_IRQn: IRQn_Type = 41;
pub const IRQn_Type_INT042_IRQn: IRQn_Type = 42;
pub const IRQn_Type_INT043_IRQn: IRQn_Type = 43;
pub const IRQn_Type_INT044_IRQn: IRQn_Type = 44;
pub const IRQn_Type_INT045_IRQn: IRQn_Type = 45;
pub const IRQn_Type_INT046_IRQn: IRQn_Type = 46;
pub const IRQn_Type_INT047_IRQn: IRQn_Type = 47;
pub const IRQn_Type_INT048_IRQn: IRQn_Type = 48;
pub const IRQn_Type_INT049_IRQn: IRQn_Type = 49;
pub const IRQn_Type_INT050_IRQn: IRQn_Type = 50;
pub const IRQn_Type_INT051_IRQn: IRQn_Type = 51;
pub const IRQn_Type_INT052_IRQn: IRQn_Type = 52;
pub const IRQn_Type_INT053_IRQn: IRQn_Type = 53;
pub const IRQn_Type_INT054_IRQn: IRQn_Type = 54;
pub const IRQn_Type_INT055_IRQn: IRQn_Type = 55;
pub const IRQn_Type_INT056_IRQn: IRQn_Type = 56;
pub const IRQn_Type_INT057_IRQn: IRQn_Type = 57;
pub const IRQn_Type_INT058_IRQn: IRQn_Type = 58;
pub const IRQn_Type_INT059_IRQn: IRQn_Type = 59;
pub const IRQn_Type_INT060_IRQn: IRQn_Type = 60;
pub const IRQn_Type_INT061_IRQn: IRQn_Type = 61;
pub const IRQn_Type_INT062_IRQn: IRQn_Type = 62;
pub const IRQn_Type_INT063_IRQn: IRQn_Type = 63;
pub const IRQn_Type_INT064_IRQn: IRQn_Type = 64;
pub const IRQn_Type_INT065_IRQn: IRQn_Type = 65;
pub const IRQn_Type_INT066_IRQn: IRQn_Type = 66;
pub const IRQn_Type_INT067_IRQn: IRQn_Type = 67;
pub const IRQn_Type_INT068_IRQn: IRQn_Type = 68;
pub const IRQn_Type_INT069_IRQn: IRQn_Type = 69;
pub const IRQn_Type_INT070_IRQn: IRQn_Type = 70;
pub const IRQn_Type_INT071_IRQn: IRQn_Type = 71;
pub const IRQn_Type_INT072_IRQn: IRQn_Type = 72;
pub const IRQn_Type_INT073_IRQn: IRQn_Type = 73;
pub const IRQn_Type_INT074_IRQn: IRQn_Type = 74;
pub const IRQn_Type_INT075_IRQn: IRQn_Type = 75;
pub const IRQn_Type_INT076_IRQn: IRQn_Type = 76;
pub const IRQn_Type_INT077_IRQn: IRQn_Type = 77;
pub const IRQn_Type_INT078_IRQn: IRQn_Type = 78;
pub const IRQn_Type_INT079_IRQn: IRQn_Type = 79;
pub const IRQn_Type_INT080_IRQn: IRQn_Type = 80;
pub const IRQn_Type_INT081_IRQn: IRQn_Type = 81;
pub const IRQn_Type_INT082_IRQn: IRQn_Type = 82;
pub const IRQn_Type_INT083_IRQn: IRQn_Type = 83;
pub const IRQn_Type_INT084_IRQn: IRQn_Type = 84;
pub const IRQn_Type_INT085_IRQn: IRQn_Type = 85;
pub const IRQn_Type_INT086_IRQn: IRQn_Type = 86;
pub const IRQn_Type_INT087_IRQn: IRQn_Type = 87;
pub const IRQn_Type_INT088_IRQn: IRQn_Type = 88;
pub const IRQn_Type_INT089_IRQn: IRQn_Type = 89;
pub const IRQn_Type_INT090_IRQn: IRQn_Type = 90;
pub const IRQn_Type_INT091_IRQn: IRQn_Type = 91;
pub const IRQn_Type_INT092_IRQn: IRQn_Type = 92;
pub const IRQn_Type_INT093_IRQn: IRQn_Type = 93;
pub const IRQn_Type_INT094_IRQn: IRQn_Type = 94;
pub const IRQn_Type_INT095_IRQn: IRQn_Type = 95;
pub const IRQn_Type_INT096_IRQn: IRQn_Type = 96;
pub const IRQn_Type_INT097_IRQn: IRQn_Type = 97;
pub const IRQn_Type_INT098_IRQn: IRQn_Type = 98;
pub const IRQn_Type_INT099_IRQn: IRQn_Type = 99;
pub const IRQn_Type_INT100_IRQn: IRQn_Type = 100;
pub const IRQn_Type_INT101_IRQn: IRQn_Type = 101;
pub const IRQn_Type_INT102_IRQn: IRQn_Type = 102;
pub const IRQn_Type_INT103_IRQn: IRQn_Type = 103;
pub const IRQn_Type_INT104_IRQn: IRQn_Type = 104;
pub const IRQn_Type_INT105_IRQn: IRQn_Type = 105;
pub const IRQn_Type_INT106_IRQn: IRQn_Type = 106;
pub const IRQn_Type_INT107_IRQn: IRQn_Type = 107;
pub const IRQn_Type_INT108_IRQn: IRQn_Type = 108;
pub const IRQn_Type_INT109_IRQn: IRQn_Type = 109;
pub const IRQn_Type_INT110_IRQn: IRQn_Type = 110;
pub const IRQn_Type_INT111_IRQn: IRQn_Type = 111;
pub const IRQn_Type_INT112_IRQn: IRQn_Type = 112;
pub const IRQn_Type_INT113_IRQn: IRQn_Type = 113;
pub const IRQn_Type_INT114_IRQn: IRQn_Type = 114;
pub const IRQn_Type_INT115_IRQn: IRQn_Type = 115;
pub const IRQn_Type_INT116_IRQn: IRQn_Type = 116;
pub const IRQn_Type_INT117_IRQn: IRQn_Type = 117;
pub const IRQn_Type_INT118_IRQn: IRQn_Type = 118;
pub const IRQn_Type_INT119_IRQn: IRQn_Type = 119;
pub const IRQn_Type_INT120_IRQn: IRQn_Type = 120;
pub const IRQn_Type_INT121_IRQn: IRQn_Type = 121;
pub const IRQn_Type_INT122_IRQn: IRQn_Type = 122;
pub const IRQn_Type_INT123_IRQn: IRQn_Type = 123;
pub const IRQn_Type_INT124_IRQn: IRQn_Type = 124;
pub const IRQn_Type_INT125_IRQn: IRQn_Type = 125;
pub const IRQn_Type_INT126_IRQn: IRQn_Type = 126;
pub const IRQn_Type_INT127_IRQn: IRQn_Type = 127;
pub const IRQn_Type_INT128_IRQn: IRQn_Type = 128;
pub const IRQn_Type_INT129_IRQn: IRQn_Type = 129;
pub const IRQn_Type_INT130_IRQn: IRQn_Type = 130;
pub const IRQn_Type_INT131_IRQn: IRQn_Type = 131;
pub const IRQn_Type_INT132_IRQn: IRQn_Type = 132;
pub const IRQn_Type_INT133_IRQn: IRQn_Type = 133;
pub const IRQn_Type_INT134_IRQn: IRQn_Type = 134;
pub const IRQn_Type_INT135_IRQn: IRQn_Type = 135;
pub const IRQn_Type_INT136_IRQn: IRQn_Type = 136;
pub const IRQn_Type_INT137_IRQn: IRQn_Type = 137;
pub const IRQn_Type_INT138_IRQn: IRQn_Type = 138;
pub const IRQn_Type_INT139_IRQn: IRQn_Type = 139;
pub const IRQn_Type_INT140_IRQn: IRQn_Type = 140;
pub const IRQn_Type_INT141_IRQn: IRQn_Type = 141;
pub const IRQn_Type_INT142_IRQn: IRQn_Type = 142;
pub const IRQn_Type_INT143_IRQn: IRQn_Type = 143;
#[doc = " Interrupt Number Definition"]
pub type IRQn_Type = ::core::ffi::c_int;
pub const en_event_src_t_EVT_SRC_SWI_IRQ0: en_event_src_t = 0;
pub const en_event_src_t_EVT_SRC_SWI_IRQ1: en_event_src_t = 1;
pub const en_event_src_t_EVT_SRC_SWI_IRQ2: en_event_src_t = 2;
pub const en_event_src_t_EVT_SRC_SWI_IRQ3: en_event_src_t = 3;
pub const en_event_src_t_EVT_SRC_SWI_IRQ4: en_event_src_t = 4;
pub const en_event_src_t_EVT_SRC_SWI_IRQ5: en_event_src_t = 5;
pub const en_event_src_t_EVT_SRC_SWI_IRQ6: en_event_src_t = 6;
pub const en_event_src_t_EVT_SRC_SWI_IRQ7: en_event_src_t = 7;
pub const en_event_src_t_EVT_SRC_SWI_IRQ8: en_event_src_t = 8;
pub const en_event_src_t_EVT_SRC_SWI_IRQ9: en_event_src_t = 9;
pub const en_event_src_t_EVT_SRC_SWI_IRQ10: en_event_src_t = 10;
pub const en_event_src_t_EVT_SRC_SWI_IRQ11: en_event_src_t = 11;
pub const en_event_src_t_EVT_SRC_SWI_IRQ12: en_event_src_t = 12;
pub const en_event_src_t_EVT_SRC_SWI_IRQ13: en_event_src_t = 13;
pub const en_event_src_t_EVT_SRC_SWI_IRQ14: en_event_src_t = 14;
pub const en_event_src_t_EVT_SRC_SWI_IRQ15: en_event_src_t = 15;
pub const en_event_src_t_EVT_SRC_SWI_IRQ16: en_event_src_t = 16;
pub const en_event_src_t_EVT_SRC_SWI_IRQ17: en_event_src_t = 17;
pub const en_event_src_t_EVT_SRC_SWI_IRQ18: en_event_src_t = 18;
pub const en_event_src_t_EVT_SRC_SWI_IRQ19: en_event_src_t = 19;
pub const en_event_src_t_EVT_SRC_SWI_IRQ20: en_event_src_t = 20;
pub const en_event_src_t_EVT_SRC_SWI_IRQ21: en_event_src_t = 21;
pub const en_event_src_t_EVT_SRC_SWI_IRQ22: en_event_src_t = 22;
pub const en_event_src_t_EVT_SRC_SWI_IRQ23: en_event_src_t = 23;
pub const en_event_src_t_EVT_SRC_SWI_IRQ24: en_event_src_t = 24;
pub const en_event_src_t_EVT_SRC_SWI_IRQ25: en_event_src_t = 25;
pub const en_event_src_t_EVT_SRC_SWI_IRQ26: en_event_src_t = 26;
pub const en_event_src_t_EVT_SRC_SWI_IRQ27: en_event_src_t = 27;
pub const en_event_src_t_EVT_SRC_SWI_IRQ28: en_event_src_t = 28;
pub const en_event_src_t_EVT_SRC_SWI_IRQ29: en_event_src_t = 29;
pub const en_event_src_t_EVT_SRC_SWI_IRQ30: en_event_src_t = 30;
pub const en_event_src_t_EVT_SRC_SWI_IRQ31: en_event_src_t = 31;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ0: en_event_src_t = 0;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ1: en_event_src_t = 1;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ2: en_event_src_t = 2;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ3: en_event_src_t = 3;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ4: en_event_src_t = 4;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ5: en_event_src_t = 5;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ6: en_event_src_t = 6;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ7: en_event_src_t = 7;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ8: en_event_src_t = 8;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ9: en_event_src_t = 9;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ10: en_event_src_t = 10;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ11: en_event_src_t = 11;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ12: en_event_src_t = 12;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ13: en_event_src_t = 13;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ14: en_event_src_t = 14;
pub const en_event_src_t_EVT_SRC_PORT_EIRQ15: en_event_src_t = 15;
pub const en_event_src_t_EVT_SRC_DMA1_TC0: en_event_src_t = 32;
pub const en_event_src_t_EVT_SRC_DMA1_TC1: en_event_src_t = 33;
pub const en_event_src_t_EVT_SRC_DMA1_TC2: en_event_src_t = 34;
pub const en_event_src_t_EVT_SRC_DMA1_TC3: en_event_src_t = 35;
pub const en_event_src_t_EVT_SRC_DMA2_TC0: en_event_src_t = 36;
pub const en_event_src_t_EVT_SRC_DMA2_TC1: en_event_src_t = 37;
pub const en_event_src_t_EVT_SRC_DMA2_TC2: en_event_src_t = 38;
pub const en_event_src_t_EVT_SRC_DMA2_TC3: en_event_src_t = 39;
pub const en_event_src_t_EVT_SRC_DMA1_BTC0: en_event_src_t = 40;
pub const en_event_src_t_EVT_SRC_DMA1_BTC1: en_event_src_t = 41;
pub const en_event_src_t_EVT_SRC_DMA1_BTC2: en_event_src_t = 42;
pub const en_event_src_t_EVT_SRC_DMA1_BTC3: en_event_src_t = 43;
pub const en_event_src_t_EVT_SRC_DMA2_BTC0: en_event_src_t = 44;
pub const en_event_src_t_EVT_SRC_DMA2_BTC1: en_event_src_t = 45;
pub const en_event_src_t_EVT_SRC_DMA2_BTC2: en_event_src_t = 46;
pub const en_event_src_t_EVT_SRC_DMA2_BTC3: en_event_src_t = 47;
pub const en_event_src_t_EVT_SRC_EFM_OPTEND: en_event_src_t = 52;
pub const en_event_src_t_EVT_SRC_USBFS_SOF: en_event_src_t = 53;
pub const en_event_src_t_EVT_SRC_DCU1: en_event_src_t = 55;
pub const en_event_src_t_EVT_SRC_DCU2: en_event_src_t = 56;
pub const en_event_src_t_EVT_SRC_DCU3: en_event_src_t = 57;
pub const en_event_src_t_EVT_SRC_DCU4: en_event_src_t = 58;
pub const en_event_src_t_EVT_SRC_TMR0_1_CMP_A: en_event_src_t = 64;
pub const en_event_src_t_EVT_SRC_TMR0_1_CMP_B: en_event_src_t = 65;
pub const en_event_src_t_EVT_SRC_TMR0_2_CMP_A: en_event_src_t = 66;
pub const en_event_src_t_EVT_SRC_TMR0_2_CMP_B: en_event_src_t = 67;
pub const en_event_src_t_EVT_SRC_RTC_ALM: en_event_src_t = 81;
pub const en_event_src_t_EVT_SRC_RTC_PRD: en_event_src_t = 82;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_A: en_event_src_t = 96;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_B: en_event_src_t = 97;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_C: en_event_src_t = 98;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_D: en_event_src_t = 99;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_E: en_event_src_t = 100;
pub const en_event_src_t_EVT_SRC_TMR6_1_GCMP_F: en_event_src_t = 101;
pub const en_event_src_t_EVT_SRC_TMR6_1_OVF: en_event_src_t = 102;
pub const en_event_src_t_EVT_SRC_TMR6_1_UDF: en_event_src_t = 103;
pub const en_event_src_t_EVT_SRC_TMR6_1_SCMP_A: en_event_src_t = 107;
pub const en_event_src_t_EVT_SRC_TMR6_1_SCMP_B: en_event_src_t = 108;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_A: en_event_src_t = 112;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_B: en_event_src_t = 113;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_C: en_event_src_t = 114;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_D: en_event_src_t = 115;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_E: en_event_src_t = 116;
pub const en_event_src_t_EVT_SRC_TMR6_2_GCMP_F: en_event_src_t = 117;
pub const en_event_src_t_EVT_SRC_TMR6_2_OVF: en_event_src_t = 118;
pub const en_event_src_t_EVT_SRC_TMR6_2_UDF: en_event_src_t = 119;
pub const en_event_src_t_EVT_SRC_TMR6_2_SCMP_A: en_event_src_t = 123;
pub const en_event_src_t_EVT_SRC_TMR6_2_SCMP_B: en_event_src_t = 124;
pub const en_event_src_t_EVT_SRC_TMR6_3_GCMP_A: en_event_src_t = 128;
pub const en_event_src_t_EVT_SRC_TMR6_3_GCMP_B: en_event_src_t = 129;
pub const en_event_src_t_EVT_SRC_TMR6_3_GCMP_C: en_event_src_t = 130;
pub const en_event_src_t_EVT_SRC_TMR6_3_GCMP_D: en_event_src_t = 131;
pub const en_event_src_t_EVT_SRC_TMR6_3_GCMP_E: en_event_src_t = 132;
pub const en_event_src_t_EVT_SRC_TMR6_3_GCMP_F: en_event_src_t = 133;
pub const en_event_src_t_EVT_SRC_TMR6_3_OVF: en_event_src_t = 134;
pub const en_event_src_t_EVT_SRC_TMR6_3_UDF: en_event_src_t = 135;
pub const en_event_src_t_EVT_SRC_TMR6_3_SCMP_A: en_event_src_t = 139;
pub const en_event_src_t_EVT_SRC_TMR6_3_SCMP_B: en_event_src_t = 140;
pub const en_event_src_t_EVT_SRC_TMRA_1_OVF: en_event_src_t = 256;
pub const en_event_src_t_EVT_SRC_TMRA_1_UDF: en_event_src_t = 257;
pub const en_event_src_t_EVT_SRC_TMRA_1_CMP: en_event_src_t = 258;
pub const en_event_src_t_EVT_SRC_TMRA_2_OVF: en_event_src_t = 259;
pub const en_event_src_t_EVT_SRC_TMRA_2_UDF: en_event_src_t = 260;
pub const en_event_src_t_EVT_SRC_TMRA_2_CMP: en_event_src_t = 261;
pub const en_event_src_t_EVT_SRC_TMRA_3_OVF: en_event_src_t = 262;
pub const en_event_src_t_EVT_SRC_TMRA_3_UDF: en_event_src_t = 263;
pub const en_event_src_t_EVT_SRC_TMRA_3_CMP: en_event_src_t = 264;
pub const en_event_src_t_EVT_SRC_TMRA_4_OVF: en_event_src_t = 265;
pub const en_event_src_t_EVT_SRC_TMRA_4_UDF: en_event_src_t = 266;
pub const en_event_src_t_EVT_SRC_TMRA_4_CMP: en_event_src_t = 267;
pub const en_event_src_t_EVT_SRC_TMRA_5_OVF: en_event_src_t = 268;
pub const en_event_src_t_EVT_SRC_TMRA_5_UDF: en_event_src_t = 269;
pub const en_event_src_t_EVT_SRC_TMRA_5_CMP: en_event_src_t = 270;
pub const en_event_src_t_EVT_SRC_TMRA_6_OVF: en_event_src_t = 272;
pub const en_event_src_t_EVT_SRC_TMRA_6_UDF: en_event_src_t = 273;
pub const en_event_src_t_EVT_SRC_TMRA_6_CMP: en_event_src_t = 274;
pub const en_event_src_t_EVT_SRC_USART1_EI: en_event_src_t = 278;
pub const en_event_src_t_EVT_SRC_USART1_RI: en_event_src_t = 279;
pub const en_event_src_t_EVT_SRC_USART1_TI: en_event_src_t = 280;
pub const en_event_src_t_EVT_SRC_USART1_TCI: en_event_src_t = 281;
pub const en_event_src_t_EVT_SRC_USART1_RTO: en_event_src_t = 282;
pub const en_event_src_t_EVT_SRC_USART2_EI: en_event_src_t = 283;
pub const en_event_src_t_EVT_SRC_USART2_RI: en_event_src_t = 284;
pub const en_event_src_t_EVT_SRC_USART2_TI: en_event_src_t = 285;
pub const en_event_src_t_EVT_SRC_USART2_TCI: en_event_src_t = 286;
pub const en_event_src_t_EVT_SRC_USART2_RTO: en_event_src_t = 287;
pub const en_event_src_t_EVT_SRC_USART3_EI: en_event_src_t = 288;
pub const en_event_src_t_EVT_SRC_USART3_RI: en_event_src_t = 289;
pub const en_event_src_t_EVT_SRC_USART3_TI: en_event_src_t = 290;
pub const en_event_src_t_EVT_SRC_USART3_TCI: en_event_src_t = 291;
pub const en_event_src_t_EVT_SRC_USART3_RTO: en_event_src_t = 292;
pub const en_event_src_t_EVT_SRC_USART4_EI: en_event_src_t = 293;
pub const en_event_src_t_EVT_SRC_USART4_RI: en_event_src_t = 294;
pub const en_event_src_t_EVT_SRC_USART4_TI: en_event_src_t = 295;
pub const en_event_src_t_EVT_SRC_USART4_TCI: en_event_src_t = 296;
pub const en_event_src_t_EVT_SRC_USART4_RTO: en_event_src_t = 297;
pub const en_event_src_t_EVT_SRC_SPI1_SPRI: en_event_src_t = 299;
pub const en_event_src_t_EVT_SRC_SPI1_SPTI: en_event_src_t = 300;
pub const en_event_src_t_EVT_SRC_SPI1_SPII: en_event_src_t = 301;
pub const en_event_src_t_EVT_SRC_SPI1_SPEI: en_event_src_t = 302;
pub const en_event_src_t_EVT_SRC_SPI1_SPTEND: en_event_src_t = 303;
pub const en_event_src_t_EVT_SRC_SPI2_SPRI: en_event_src_t = 304;
pub const en_event_src_t_EVT_SRC_SPI2_SPTI: en_event_src_t = 305;
pub const en_event_src_t_EVT_SRC_SPI2_SPII: en_event_src_t = 306;
pub const en_event_src_t_EVT_SRC_SPI2_SPEI: en_event_src_t = 307;
pub const en_event_src_t_EVT_SRC_SPI2_SPTEND: en_event_src_t = 308;
pub const en_event_src_t_EVT_SRC_SPI3_SPRI: en_event_src_t = 309;
pub const en_event_src_t_EVT_SRC_SPI3_SPTI: en_event_src_t = 310;
pub const en_event_src_t_EVT_SRC_SPI3_SPII: en_event_src_t = 311;
pub const en_event_src_t_EVT_SRC_SPI3_SPEI: en_event_src_t = 312;
pub const en_event_src_t_EVT_SRC_SPI3_SPTEND: en_event_src_t = 313;
pub const en_event_src_t_EVT_SRC_SPI4_SPRI: en_event_src_t = 314;
pub const en_event_src_t_EVT_SRC_SPI4_SPTI: en_event_src_t = 315;
pub const en_event_src_t_EVT_SRC_SPI4_SPII: en_event_src_t = 316;
pub const en_event_src_t_EVT_SRC_SPI4_SPEI: en_event_src_t = 317;
pub const en_event_src_t_EVT_SRC_SPI4_SPTEND: en_event_src_t = 318;
pub const en_event_src_t_EVT_SRC_AOS_STRG: en_event_src_t = 319;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP0: en_event_src_t = 368;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP1: en_event_src_t = 369;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP2: en_event_src_t = 370;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP3: en_event_src_t = 371;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP4: en_event_src_t = 372;
pub const en_event_src_t_EVT_SRC_TMR4_1_SCMP5: en_event_src_t = 373;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP0: en_event_src_t = 374;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP1: en_event_src_t = 375;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP2: en_event_src_t = 376;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP3: en_event_src_t = 377;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP4: en_event_src_t = 378;
pub const en_event_src_t_EVT_SRC_TMR4_2_SCMP5: en_event_src_t = 379;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP0: en_event_src_t = 384;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP1: en_event_src_t = 385;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP2: en_event_src_t = 386;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP3: en_event_src_t = 387;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP4: en_event_src_t = 388;
pub const en_event_src_t_EVT_SRC_TMR4_3_SCMP5: en_event_src_t = 389;
pub const en_event_src_t_EVT_SRC_EVENT_PORT1: en_event_src_t = 394;
pub const en_event_src_t_EVT_SRC_EVENT_PORT2: en_event_src_t = 395;
pub const en_event_src_t_EVT_SRC_EVENT_PORT3: en_event_src_t = 396;
pub const en_event_src_t_EVT_SRC_EVENT_PORT4: en_event_src_t = 397;
pub const en_event_src_t_EVT_SRC_I2S1_TXIRQOUT: en_event_src_t = 400;
pub const en_event_src_t_EVT_SRC_I2S1_RXIRQOUT: en_event_src_t = 401;
pub const en_event_src_t_EVT_SRC_I2S2_TXIRQOUT: en_event_src_t = 403;
pub const en_event_src_t_EVT_SRC_I2S2_RXIRQOUT: en_event_src_t = 404;
pub const en_event_src_t_EVT_SRC_I2S3_TXIRQOUT: en_event_src_t = 406;
pub const en_event_src_t_EVT_SRC_I2S3_RXIRQOUT: en_event_src_t = 407;
pub const en_event_src_t_EVT_SRC_I2S4_TXIRQOUT: en_event_src_t = 409;
pub const en_event_src_t_EVT_SRC_I2S4_RXIRQOUT: en_event_src_t = 410;
pub const en_event_src_t_EVT_SRC_CMP1: en_event_src_t = 416;
pub const en_event_src_t_EVT_SRC_CMP2: en_event_src_t = 417;
pub const en_event_src_t_EVT_SRC_CMP3: en_event_src_t = 418;
pub const en_event_src_t_EVT_SRC_I2C1_RXI: en_event_src_t = 420;
pub const en_event_src_t_EVT_SRC_I2C1_TXI: en_event_src_t = 421;
pub const en_event_src_t_EVT_SRC_I2C1_TEI: en_event_src_t = 422;
pub const en_event_src_t_EVT_SRC_I2C1_EEI: en_event_src_t = 423;
pub const en_event_src_t_EVT_SRC_I2C2_RXI: en_event_src_t = 424;
pub const en_event_src_t_EVT_SRC_I2C2_TXI: en_event_src_t = 425;
pub const en_event_src_t_EVT_SRC_I2C2_TEI: en_event_src_t = 426;
pub const en_event_src_t_EVT_SRC_I2C2_EEI: en_event_src_t = 427;
pub const en_event_src_t_EVT_SRC_I2C3_RXI: en_event_src_t = 428;
pub const en_event_src_t_EVT_SRC_I2C3_TXI: en_event_src_t = 429;
pub const en_event_src_t_EVT_SRC_I2C3_TEI: en_event_src_t = 430;
pub const en_event_src_t_EVT_SRC_I2C3_EEI: en_event_src_t = 431;
pub const en_event_src_t_EVT_SRC_LVD1: en_event_src_t = 433;
pub const en_event_src_t_EVT_SRC_LVD2: en_event_src_t = 434;
pub const en_event_src_t_EVT_SRC_OTS: en_event_src_t = 435;
pub const en_event_src_t_EVT_SRC_WDT_REFUDF: en_event_src_t = 439;
pub const en_event_src_t_EVT_SRC_ADC1_EOCA: en_event_src_t = 448;
pub const en_event_src_t_EVT_SRC_ADC1_EOCB: en_event_src_t = 449;
pub const en_event_src_t_EVT_SRC_ADC1_CHCMP: en_event_src_t = 450;
pub const en_event_src_t_EVT_SRC_ADC1_SEQCMP: en_event_src_t = 451;
pub const en_event_src_t_EVT_SRC_ADC2_EOCA: en_event_src_t = 452;
pub const en_event_src_t_EVT_SRC_ADC2_EOCB: en_event_src_t = 453;
pub const en_event_src_t_EVT_SRC_ADC2_CHCMP: en_event_src_t = 454;
pub const en_event_src_t_EVT_SRC_ADC2_SEQCMP: en_event_src_t = 455;
pub const en_event_src_t_EVT_SRC_TRNG_END: en_event_src_t = 456;
pub const en_event_src_t_EVT_SRC_SDIOC1_DMAR: en_event_src_t = 480;
pub const en_event_src_t_EVT_SRC_SDIOC1_DMAW: en_event_src_t = 481;
pub const en_event_src_t_EVT_SRC_SDIOC2_DMAR: en_event_src_t = 483;
pub const en_event_src_t_EVT_SRC_SDIOC2_DMAW: en_event_src_t = 484;
pub const en_event_src_t_EVT_SRC_MAX: en_event_src_t = 511;
#[doc = " \\brief Event number enumeration"]
pub type en_event_src_t = ::core::ffi::c_uint;
pub const en_int_src_t_INT_SRC_SWI_IRQ0: en_int_src_t = 0;
pub const en_int_src_t_INT_SRC_SWI_IRQ1: en_int_src_t = 1;
pub const en_int_src_t_INT_SRC_SWI_IRQ2: en_int_src_t = 2;
pub const en_int_src_t_INT_SRC_SWI_IRQ3: en_int_src_t = 3;
pub const en_int_src_t_INT_SRC_SWI_IRQ4: en_int_src_t = 4;
pub const en_int_src_t_INT_SRC_SWI_IRQ5: en_int_src_t = 5;
pub const en_int_src_t_INT_SRC_SWI_IRQ6: en_int_src_t = 6;
pub const en_int_src_t_INT_SRC_SWI_IRQ7: en_int_src_t = 7;
pub const en_int_src_t_INT_SRC_SWI_IRQ8: en_int_src_t = 8;
pub const en_int_src_t_INT_SRC_SWI_IRQ9: en_int_src_t = 9;
pub const en_int_src_t_INT_SRC_SWI_IRQ10: en_int_src_t = 10;
pub const en_int_src_t_INT_SRC_SWI_IRQ11: en_int_src_t = 11;
pub const en_int_src_t_INT_SRC_SWI_IRQ12: en_int_src_t = 12;
pub const en_int_src_t_INT_SRC_SWI_IRQ13: en_int_src_t = 13;
pub const en_int_src_t_INT_SRC_SWI_IRQ14: en_int_src_t = 14;
pub const en_int_src_t_INT_SRC_SWI_IRQ15: en_int_src_t = 15;
pub const en_int_src_t_INT_SRC_SWI_IRQ16: en_int_src_t = 16;
pub const en_int_src_t_INT_SRC_SWI_IRQ17: en_int_src_t = 17;
pub const en_int_src_t_INT_SRC_SWI_IRQ18: en_int_src_t = 18;
pub const en_int_src_t_INT_SRC_SWI_IRQ19: en_int_src_t = 19;
pub const en_int_src_t_INT_SRC_SWI_IRQ20: en_int_src_t = 20;
pub const en_int_src_t_INT_SRC_SWI_IRQ21: en_int_src_t = 21;
pub const en_int_src_t_INT_SRC_SWI_IRQ22: en_int_src_t = 22;
pub const en_int_src_t_INT_SRC_SWI_IRQ23: en_int_src_t = 23;
pub const en_int_src_t_INT_SRC_SWI_IRQ24: en_int_src_t = 24;
pub const en_int_src_t_INT_SRC_SWI_IRQ25: en_int_src_t = 25;
pub const en_int_src_t_INT_SRC_SWI_IRQ26: en_int_src_t = 26;
pub const en_int_src_t_INT_SRC_SWI_IRQ27: en_int_src_t = 27;
pub const en_int_src_t_INT_SRC_SWI_IRQ28: en_int_src_t = 28;
pub const en_int_src_t_INT_SRC_SWI_IRQ29: en_int_src_t = 29;
pub const en_int_src_t_INT_SRC_SWI_IRQ30: en_int_src_t = 30;
pub const en_int_src_t_INT_SRC_SWI_IRQ31: en_int_src_t = 31;
pub const en_int_src_t_INT_SRC_PORT_EIRQ0: en_int_src_t = 0;
pub const en_int_src_t_INT_SRC_PORT_EIRQ1: en_int_src_t = 1;
pub const en_int_src_t_INT_SRC_PORT_EIRQ2: en_int_src_t = 2;
pub const en_int_src_t_INT_SRC_PORT_EIRQ3: en_int_src_t = 3;
pub const en_int_src_t_INT_SRC_PORT_EIRQ4: en_int_src_t = 4;
pub const en_int_src_t_INT_SRC_PORT_EIRQ5: en_int_src_t = 5;
pub const en_int_src_t_INT_SRC_PORT_EIRQ6: en_int_src_t = 6;
pub const en_int_src_t_INT_SRC_PORT_EIRQ7: en_int_src_t = 7;
pub const en_int_src_t_INT_SRC_PORT_EIRQ8: en_int_src_t = 8;
pub const en_int_src_t_INT_SRC_PORT_EIRQ9: en_int_src_t = 9;
pub const en_int_src_t_INT_SRC_PORT_EIRQ10: en_int_src_t = 10;
pub const en_int_src_t_INT_SRC_PORT_EIRQ11: en_int_src_t = 11;
pub const en_int_src_t_INT_SRC_PORT_EIRQ12: en_int_src_t = 12;
pub const en_int_src_t_INT_SRC_PORT_EIRQ13: en_int_src_t = 13;
pub const en_int_src_t_INT_SRC_PORT_EIRQ14: en_int_src_t = 14;
pub const en_int_src_t_INT_SRC_PORT_EIRQ15: en_int_src_t = 15;
pub const en_int_src_t_INT_SRC_DMA1_TC0: en_int_src_t = 32;
pub const en_int_src_t_INT_SRC_DMA1_TC1: en_int_src_t = 33;
pub const en_int_src_t_INT_SRC_DMA1_TC2: en_int_src_t = 34;
pub const en_int_src_t_INT_SRC_DMA1_TC3: en_int_src_t = 35;
pub const en_int_src_t_INT_SRC_DMA2_TC0: en_int_src_t = 36;
pub const en_int_src_t_INT_SRC_DMA2_TC1: en_int_src_t = 37;
pub const en_int_src_t_INT_SRC_DMA2_TC2: en_int_src_t = 38;
pub const en_int_src_t_INT_SRC_DMA2_TC3: en_int_src_t = 39;
pub const en_int_src_t_INT_SRC_DMA1_BTC0: en_int_src_t = 40;
pub const en_int_src_t_INT_SRC_DMA1_BTC1: en_int_src_t = 41;
pub const en_int_src_t_INT_SRC_DMA1_BTC2: en_int_src_t = 42;
pub const en_int_src_t_INT_SRC_DMA1_BTC3: en_int_src_t = 43;
pub const en_int_src_t_INT_SRC_DMA2_BTC0: en_int_src_t = 44;
pub const en_int_src_t_INT_SRC_DMA2_BTC1: en_int_src_t = 45;
pub const en_int_src_t_INT_SRC_DMA2_BTC2: en_int_src_t = 46;
pub const en_int_src_t_INT_SRC_DMA2_BTC3: en_int_src_t = 47;
pub const en_int_src_t_INT_SRC_DMA1_ERR: en_int_src_t = 48;
pub const en_int_src_t_INT_SRC_DMA2_ERR: en_int_src_t = 49;
pub const en_int_src_t_INT_SRC_EFM_PEERR: en_int_src_t = 50;
pub const en_int_src_t_INT_SRC_EFM_COLERR: en_int_src_t = 51;
pub const en_int_src_t_INT_SRC_EFM_OPTEND: en_int_src_t = 52;
pub const en_int_src_t_INT_SRC_QSPI_INTR: en_int_src_t = 54;
pub const en_int_src_t_INT_SRC_DCU1: en_int_src_t = 55;
pub const en_int_src_t_INT_SRC_DCU2: en_int_src_t = 56;
pub const en_int_src_t_INT_SRC_DCU3: en_int_src_t = 57;
pub const en_int_src_t_INT_SRC_DCU4: en_int_src_t = 58;
pub const en_int_src_t_INT_SRC_TMR0_1_CMP_A: en_int_src_t = 64;
pub const en_int_src_t_INT_SRC_TMR0_1_CMP_B: en_int_src_t = 65;
pub const en_int_src_t_INT_SRC_TMR0_2_CMP_A: en_int_src_t = 66;
pub const en_int_src_t_INT_SRC_TMR0_2_CMP_B: en_int_src_t = 67;
pub const en_int_src_t_INT_SRC_RTC_ALM: en_int_src_t = 81;
pub const en_int_src_t_INT_SRC_RTC_PRD: en_int_src_t = 82;
pub const en_int_src_t_INT_SRC_XTAL32_STOP: en_int_src_t = 84;
pub const en_int_src_t_INT_SRC_XTAL_STOP: en_int_src_t = 85;
pub const en_int_src_t_INT_SRC_WKTM_PRD: en_int_src_t = 86;
pub const en_int_src_t_INT_SRC_SWDT_REFUDF: en_int_src_t = 87;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_A: en_int_src_t = 96;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_B: en_int_src_t = 97;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_C: en_int_src_t = 98;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_D: en_int_src_t = 99;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_E: en_int_src_t = 100;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_F: en_int_src_t = 101;
pub const en_int_src_t_INT_SRC_TMR6_1_OVF: en_int_src_t = 102;
pub const en_int_src_t_INT_SRC_TMR6_1_UDF: en_int_src_t = 103;
pub const en_int_src_t_INT_SRC_TMR6_1_DTE: en_int_src_t = 104;
pub const en_int_src_t_INT_SRC_TMR6_1_SCMP_A: en_int_src_t = 107;
pub const en_int_src_t_INT_SRC_TMR6_1_SCMP_B: en_int_src_t = 108;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_A: en_int_src_t = 112;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_B: en_int_src_t = 113;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_C: en_int_src_t = 114;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_D: en_int_src_t = 115;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_E: en_int_src_t = 116;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_F: en_int_src_t = 117;
pub const en_int_src_t_INT_SRC_TMR6_2_OVF: en_int_src_t = 118;
pub const en_int_src_t_INT_SRC_TMR6_2_UDF: en_int_src_t = 119;
pub const en_int_src_t_INT_SRC_TMR6_2_DTE: en_int_src_t = 120;
pub const en_int_src_t_INT_SRC_TMR6_2_SCMP_A: en_int_src_t = 123;
pub const en_int_src_t_INT_SRC_TMR6_2_SCMP_B: en_int_src_t = 124;
pub const en_int_src_t_INT_SRC_TMR6_3_GCMP_A: en_int_src_t = 128;
pub const en_int_src_t_INT_SRC_TMR6_3_GCMP_B: en_int_src_t = 129;
pub const en_int_src_t_INT_SRC_TMR6_3_GCMP_C: en_int_src_t = 130;
pub const en_int_src_t_INT_SRC_TMR6_3_GCMP_D: en_int_src_t = 131;
pub const en_int_src_t_INT_SRC_TMR6_3_GCMP_E: en_int_src_t = 132;
pub const en_int_src_t_INT_SRC_TMR6_3_GCMP_F: en_int_src_t = 133;
pub const en_int_src_t_INT_SRC_TMR6_3_OVF: en_int_src_t = 134;
pub const en_int_src_t_INT_SRC_TMR6_3_UDF: en_int_src_t = 135;
pub const en_int_src_t_INT_SRC_TMR6_3_DTE: en_int_src_t = 136;
pub const en_int_src_t_INT_SRC_TMR6_3_SCMP_A: en_int_src_t = 139;
pub const en_int_src_t_INT_SRC_TMR6_3_SCMP_B: en_int_src_t = 140;
pub const en_int_src_t_INT_SRC_TMRA_1_OVF: en_int_src_t = 256;
pub const en_int_src_t_INT_SRC_TMRA_1_UDF: en_int_src_t = 257;
pub const en_int_src_t_INT_SRC_TMRA_1_CMP: en_int_src_t = 258;
pub const en_int_src_t_INT_SRC_TMRA_2_OVF: en_int_src_t = 259;
pub const en_int_src_t_INT_SRC_TMRA_2_UDF: en_int_src_t = 260;
pub const en_int_src_t_INT_SRC_TMRA_2_CMP: en_int_src_t = 261;
pub const en_int_src_t_INT_SRC_TMRA_3_OVF: en_int_src_t = 262;
pub const en_int_src_t_INT_SRC_TMRA_3_UDF: en_int_src_t = 263;
pub const en_int_src_t_INT_SRC_TMRA_3_CMP: en_int_src_t = 264;
pub const en_int_src_t_INT_SRC_TMRA_4_OVF: en_int_src_t = 265;
pub const en_int_src_t_INT_SRC_TMRA_4_UDF: en_int_src_t = 266;
pub const en_int_src_t_INT_SRC_TMRA_4_CMP: en_int_src_t = 267;
pub const en_int_src_t_INT_SRC_TMRA_5_OVF: en_int_src_t = 268;
pub const en_int_src_t_INT_SRC_TMRA_5_UDF: en_int_src_t = 269;
pub const en_int_src_t_INT_SRC_TMRA_5_CMP: en_int_src_t = 270;
pub const en_int_src_t_INT_SRC_TMRA_6_OVF: en_int_src_t = 272;
pub const en_int_src_t_INT_SRC_TMRA_6_UDF: en_int_src_t = 273;
pub const en_int_src_t_INT_SRC_TMRA_6_CMP: en_int_src_t = 274;
pub const en_int_src_t_INT_SRC_USBFS_GLB: en_int_src_t = 275;
pub const en_int_src_t_INT_SRC_USART1_EI: en_int_src_t = 278;
pub const en_int_src_t_INT_SRC_USART1_RI: en_int_src_t = 279;
pub const en_int_src_t_INT_SRC_USART1_TI: en_int_src_t = 280;
pub const en_int_src_t_INT_SRC_USART1_TCI: en_int_src_t = 281;
pub const en_int_src_t_INT_SRC_USART1_RTO: en_int_src_t = 282;
pub const en_int_src_t_INT_SRC_USART1_WUPI: en_int_src_t = 432;
pub const en_int_src_t_INT_SRC_USART2_EI: en_int_src_t = 283;
pub const en_int_src_t_INT_SRC_USART2_RI: en_int_src_t = 284;
pub const en_int_src_t_INT_SRC_USART2_TI: en_int_src_t = 285;
pub const en_int_src_t_INT_SRC_USART2_TCI: en_int_src_t = 286;
pub const en_int_src_t_INT_SRC_USART2_RTO: en_int_src_t = 287;
pub const en_int_src_t_INT_SRC_USART3_EI: en_int_src_t = 288;
pub const en_int_src_t_INT_SRC_USART3_RI: en_int_src_t = 289;
pub const en_int_src_t_INT_SRC_USART3_TI: en_int_src_t = 290;
pub const en_int_src_t_INT_SRC_USART3_TCI: en_int_src_t = 291;
pub const en_int_src_t_INT_SRC_USART3_RTO: en_int_src_t = 292;
pub const en_int_src_t_INT_SRC_USART4_EI: en_int_src_t = 293;
pub const en_int_src_t_INT_SRC_USART4_RI: en_int_src_t = 294;
pub const en_int_src_t_INT_SRC_USART4_TI: en_int_src_t = 295;
pub const en_int_src_t_INT_SRC_USART4_TCI: en_int_src_t = 296;
pub const en_int_src_t_INT_SRC_USART4_RTO: en_int_src_t = 297;
pub const en_int_src_t_INT_SRC_SPI1_SPRI: en_int_src_t = 299;
pub const en_int_src_t_INT_SRC_SPI1_SPTI: en_int_src_t = 300;
pub const en_int_src_t_INT_SRC_SPI1_SPII: en_int_src_t = 301;
pub const en_int_src_t_INT_SRC_SPI1_SPEI: en_int_src_t = 302;
pub const en_int_src_t_INT_SRC_SPI2_SPRI: en_int_src_t = 304;
pub const en_int_src_t_INT_SRC_SPI2_SPTI: en_int_src_t = 305;
pub const en_int_src_t_INT_SRC_SPI2_SPII: en_int_src_t = 306;
pub const en_int_src_t_INT_SRC_SPI2_SPEI: en_int_src_t = 307;
pub const en_int_src_t_INT_SRC_SPI3_SPRI: en_int_src_t = 309;
pub const en_int_src_t_INT_SRC_SPI3_SPTI: en_int_src_t = 310;
pub const en_int_src_t_INT_SRC_SPI3_SPII: en_int_src_t = 311;
pub const en_int_src_t_INT_SRC_SPI3_SPEI: en_int_src_t = 312;
pub const en_int_src_t_INT_SRC_SPI4_SPRI: en_int_src_t = 314;
pub const en_int_src_t_INT_SRC_SPI4_SPTI: en_int_src_t = 315;
pub const en_int_src_t_INT_SRC_SPI4_SPII: en_int_src_t = 316;
pub const en_int_src_t_INT_SRC_SPI4_SPEI: en_int_src_t = 317;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_UH: en_int_src_t = 320;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_UL: en_int_src_t = 321;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_VH: en_int_src_t = 322;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_VL: en_int_src_t = 323;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_WH: en_int_src_t = 324;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_WL: en_int_src_t = 325;
pub const en_int_src_t_INT_SRC_TMR4_1_OVF: en_int_src_t = 326;
pub const en_int_src_t_INT_SRC_TMR4_1_UDF: en_int_src_t = 327;
pub const en_int_src_t_INT_SRC_TMR4_1_RELOAD_U: en_int_src_t = 328;
pub const en_int_src_t_INT_SRC_TMR4_1_RELOAD_V: en_int_src_t = 329;
pub const en_int_src_t_INT_SRC_TMR4_1_RELOAD_W: en_int_src_t = 330;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_UH: en_int_src_t = 336;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_UL: en_int_src_t = 337;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_VH: en_int_src_t = 338;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_VL: en_int_src_t = 339;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_WH: en_int_src_t = 340;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_WL: en_int_src_t = 341;
pub const en_int_src_t_INT_SRC_TMR4_2_OVF: en_int_src_t = 342;
pub const en_int_src_t_INT_SRC_TMR4_2_UDF: en_int_src_t = 343;
pub const en_int_src_t_INT_SRC_TMR4_2_RELOAD_U: en_int_src_t = 344;
pub const en_int_src_t_INT_SRC_TMR4_2_RELOAD_V: en_int_src_t = 345;
pub const en_int_src_t_INT_SRC_TMR4_2_RELOAD_W: en_int_src_t = 346;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_UH: en_int_src_t = 352;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_UL: en_int_src_t = 353;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_VH: en_int_src_t = 354;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_VL: en_int_src_t = 355;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_WH: en_int_src_t = 356;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_WL: en_int_src_t = 357;
pub const en_int_src_t_INT_SRC_TMR4_3_OVF: en_int_src_t = 358;
pub const en_int_src_t_INT_SRC_TMR4_3_UDF: en_int_src_t = 359;
pub const en_int_src_t_INT_SRC_TMR4_3_RELOAD_U: en_int_src_t = 360;
pub const en_int_src_t_INT_SRC_TMR4_3_RELOAD_V: en_int_src_t = 361;
pub const en_int_src_t_INT_SRC_TMR4_3_RELOAD_W: en_int_src_t = 362;
pub const en_int_src_t_INT_SRC_EMB_GR0: en_int_src_t = 390;
pub const en_int_src_t_INT_SRC_EMB_GR1: en_int_src_t = 391;
pub const en_int_src_t_INT_SRC_EMB_GR2: en_int_src_t = 392;
pub const en_int_src_t_INT_SRC_EMB_GR3: en_int_src_t = 393;
pub const en_int_src_t_INT_SRC_EVENT_PORT1: en_int_src_t = 394;
pub const en_int_src_t_INT_SRC_EVENT_PORT2: en_int_src_t = 395;
pub const en_int_src_t_INT_SRC_EVENT_PORT3: en_int_src_t = 396;
pub const en_int_src_t_INT_SRC_EVENT_PORT4: en_int_src_t = 397;
pub const en_int_src_t_INT_SRC_I2S1_TXIRQOUT: en_int_src_t = 400;
pub const en_int_src_t_INT_SRC_I2S1_RXIRQOUT: en_int_src_t = 401;
pub const en_int_src_t_INT_SRC_I2S1_ERRIRQOUT: en_int_src_t = 402;
pub const en_int_src_t_INT_SRC_I2S2_TXIRQOUT: en_int_src_t = 403;
pub const en_int_src_t_INT_SRC_I2S2_RXIRQOUT: en_int_src_t = 404;
pub const en_int_src_t_INT_SRC_I2S2_ERRIRQOUT: en_int_src_t = 405;
pub const en_int_src_t_INT_SRC_I2S3_TXIRQOUT: en_int_src_t = 406;
pub const en_int_src_t_INT_SRC_I2S3_RXIRQOUT: en_int_src_t = 407;
pub const en_int_src_t_INT_SRC_I2S3_ERRIRQOUT: en_int_src_t = 408;
pub const en_int_src_t_INT_SRC_I2S4_TXIRQOUT: en_int_src_t = 409;
pub const en_int_src_t_INT_SRC_I2S4_RXIRQOUT: en_int_src_t = 410;
pub const en_int_src_t_INT_SRC_I2S4_ERRIRQOUT: en_int_src_t = 411;
pub const en_int_src_t_INT_SRC_CMP1: en_int_src_t = 416;
pub const en_int_src_t_INT_SRC_CMP2: en_int_src_t = 417;
pub const en_int_src_t_INT_SRC_CMP3: en_int_src_t = 418;
pub const en_int_src_t_INT_SRC_I2C1_RXI: en_int_src_t = 420;
pub const en_int_src_t_INT_SRC_I2C1_TXI: en_int_src_t = 421;
pub const en_int_src_t_INT_SRC_I2C1_TEI: en_int_src_t = 422;
pub const en_int_src_t_INT_SRC_I2C1_EEI: en_int_src_t = 423;
pub const en_int_src_t_INT_SRC_I2C2_RXI: en_int_src_t = 424;
pub const en_int_src_t_INT_SRC_I2C2_TXI: en_int_src_t = 425;
pub const en_int_src_t_INT_SRC_I2C2_TEI: en_int_src_t = 426;
pub const en_int_src_t_INT_SRC_I2C2_EEI: en_int_src_t = 427;
pub const en_int_src_t_INT_SRC_I2C3_RXI: en_int_src_t = 428;
pub const en_int_src_t_INT_SRC_I2C3_TXI: en_int_src_t = 429;
pub const en_int_src_t_INT_SRC_I2C3_TEI: en_int_src_t = 430;
pub const en_int_src_t_INT_SRC_I2C3_EEI: en_int_src_t = 431;
pub const en_int_src_t_INT_SRC_LVD1: en_int_src_t = 433;
pub const en_int_src_t_INT_SRC_LVD2: en_int_src_t = 434;
pub const en_int_src_t_INT_SRC_OTS: en_int_src_t = 435;
pub const en_int_src_t_INT_SRC_FCMFERRI: en_int_src_t = 436;
pub const en_int_src_t_INT_SRC_FCMMENDI: en_int_src_t = 437;
pub const en_int_src_t_INT_SRC_FCMCOVFI: en_int_src_t = 438;
pub const en_int_src_t_INT_SRC_WDT_REFUDF: en_int_src_t = 439;
pub const en_int_src_t_INT_SRC_ADC1_EOCA: en_int_src_t = 448;
pub const en_int_src_t_INT_SRC_ADC1_EOCB: en_int_src_t = 449;
pub const en_int_src_t_INT_SRC_ADC1_CHCMP: en_int_src_t = 450;
pub const en_int_src_t_INT_SRC_ADC1_SEQCMP: en_int_src_t = 451;
pub const en_int_src_t_INT_SRC_ADC2_EOCA: en_int_src_t = 452;
pub const en_int_src_t_INT_SRC_ADC2_EOCB: en_int_src_t = 453;
pub const en_int_src_t_INT_SRC_ADC2_CHCMP: en_int_src_t = 454;
pub const en_int_src_t_INT_SRC_ADC2_SEQCMP: en_int_src_t = 455;
pub const en_int_src_t_INT_SRC_TRNG_END: en_int_src_t = 456;
pub const en_int_src_t_INT_SRC_SDIOC1_SD: en_int_src_t = 482;
pub const en_int_src_t_INT_SRC_SDIOC2_SD: en_int_src_t = 485;
pub const en_int_src_t_INT_SRC_CAN_INT: en_int_src_t = 486;
pub const en_int_src_t_INT_SRC_MAX: en_int_src_t = 511;
#[doc = " \\brief Interrupt number enumeration"]
pub type en_int_src_t = ::core::ffi::c_uint;
#[doc = " @brief ADC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_ADC_TypeDef {
pub STR: u8,
pub RESERVED0: [u8; 1usize],
pub CR0: u16,
pub CR1: u16,
pub RESERVED1: [u8; 4usize],
pub TRGSR: u16,
pub CHSELRA: u32,
pub CHSELRB: u32,
pub AVCHSELR: u32,
pub RESERVED2: [u8; 8usize],
pub SSTR0: u8,
pub SSTR1: u8,
pub SSTR2: u8,
pub SSTR3: u8,
pub SSTR4: u8,
pub SSTR5: u8,
pub SSTR6: u8,
pub SSTR7: u8,
pub SSTR8: u8,
pub SSTR9: u8,
pub SSTR10: u8,
pub SSTR11: u8,
pub SSTR12: u8,
pub SSTR13: u8,
pub SSTR14: u8,
pub SSTR15: u8,
pub SSTRL: u8,
pub RESERVED3: [u8; 7usize],
pub CHMUXR0: u16,
pub CHMUXR1: u16,
pub CHMUXR2: u16,
pub CHMUXR3: u16,
pub RESERVED4: [u8; 6usize],
pub ISR: u8,
pub ICR: u8,
pub RESERVED5: [u8; 4usize],
pub SYNCCR: u16,
pub RESERVED6: [u8; 2usize],
pub DR0: u16,
pub DR1: u16,
pub DR2: u16,
pub DR3: u16,
pub DR4: u16,
pub DR5: u16,
pub DR6: u16,
pub DR7: u16,
pub DR8: u16,
pub DR9: u16,
pub DR10: u16,
pub DR11: u16,
pub DR12: u16,
pub DR13: u16,
pub DR14: u16,
pub DR15: u16,
pub DR16: u16,
pub RESERVED7: [u8; 46usize],
pub AWDCR: u16,
pub RESERVED8: [u8; 2usize],
pub AWDDR0: u16,
pub AWDDR1: u16,
pub RESERVED9: [u8; 4usize],
pub AWDCHSR: u32,
pub AWDSR: u32,
pub RESERVED10: [u8; 12usize],
pub PGACR: u16,
pub PGAGSR: u16,
pub RESERVED11: [u8; 8usize],
pub PGAINSR0: u16,
pub PGAINSR1: u16,
}
#[doc = " @brief CAN"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_CAN_TypeDef {
pub RBUF: u32,
pub RESERVED0: [u8; 76usize],
pub TBUF: u32,
pub RESERVED1: [u8; 76usize],
pub CFG_STAT: u8,
pub TCMD: u8,
pub TCTRL: u8,
pub RCTRL: u8,
pub RTIE: u8,
pub RTIF: u8,
pub ERRINT: u8,
pub LIMIT: u8,
pub SBT: u32,
pub RESERVED2: [u8; 4usize],
pub EALCAP: u8,
pub RESERVED3: [u8; 1usize],
pub RECNT: u8,
pub TECNT: u8,
pub ACFCTRL: u8,
pub RESERVED4: [u8; 1usize],
pub ACFEN: u8,
pub RESERVED5: [u8; 1usize],
pub ACF: u32,
pub RESERVED6: [u8; 2usize],
pub TBSLOT: u8,
pub TTCFG: u8,
pub REF_MSG: u32,
pub TRG_CFG: u16,
pub TT_TRIG: u16,
pub TT_WTRIG: u16,
}
#[doc = " @brief CMP"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_CMP_TypeDef {
pub CTRL: u16,
pub VLTSEL: u16,
pub OUTMON: u16,
pub CVSSTB: u16,
pub CVSPRD: u16,
}
#[doc = " @brief DCU"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_DCU_TypeDef {
pub CTL: u32,
pub FLAG: u32,
pub DATA0: u32,
pub DATA1: u32,
pub DATA2: u32,
pub FLAGCLR: u32,
pub INTEVTSEL: u32,
}
#[doc = " @brief DMA"]
#[repr(C)]
#[derive(Copy, Clone)]
pub struct CM_DMA_TypeDef {
pub EN: u32,
pub INTSTAT0: u32,
pub INTSTAT1: u32,
pub INTMASK0: u32,
pub INTMASK1: u32,
pub INTCLR0: u32,
pub INTCLR1: u32,
pub CHEN: u32,
pub REQSTAT: u32,
pub CHSTAT: u32,
pub RESERVED0: [u8; 4usize],
pub RCFGCTL: u32,
pub SWREQ: u32,
pub RESERVED1: [u8; 12usize],
pub SAR0: u32,
pub DAR0: u32,
pub DTCTL0: u32,
pub __bindgen_anon_1: CM_DMA_TypeDef__bindgen_ty_1,
pub __bindgen_anon_2: CM_DMA_TypeDef__bindgen_ty_2,
pub __bindgen_anon_3: CM_DMA_TypeDef__bindgen_ty_3,
pub LLP0: u32,
pub CHCTL0: u32,
pub MONSAR0: u32,
pub MONDAR0: u32,
pub MONDTCTL0: u32,
pub MONRPT0: u32,
pub MONSNSEQCTL0: u32,
pub MONDNSEQCTL0: u32,
pub RESERVED2: [u8; 8usize],
pub SAR1: u32,
pub DAR1: u32,
pub DTCTL1: u32,
pub __bindgen_anon_4: CM_DMA_TypeDef__bindgen_ty_4,
pub __bindgen_anon_5: CM_DMA_TypeDef__bindgen_ty_5,
pub __bindgen_anon_6: CM_DMA_TypeDef__bindgen_ty_6,
pub LLP1: u32,
pub CHCTL1: u32,
pub MONSAR1: u32,
pub MONDAR1: u32,
pub MONDTCTL1: u32,
pub MONRPT1: u32,
pub MONSNSEQCTL1: u32,
pub MONDNSEQCTL1: u32,
pub RESERVED3: [u8; 8usize],
pub SAR2: u32,
pub DAR2: u32,
pub DTCTL2: u32,
pub __bindgen_anon_7: CM_DMA_TypeDef__bindgen_ty_7,
pub __bindgen_anon_8: CM_DMA_TypeDef__bindgen_ty_8,
pub __bindgen_anon_9: CM_DMA_TypeDef__bindgen_ty_9,
pub LLP2: u32,
pub CHCTL2: u32,
pub MONSAR2: u32,
pub MONDAR2: u32,
pub MONDTCTL2: u32,
pub MONRPT2: u32,
pub MONSNSEQCTL2: u32,
pub MONDNSEQCTL2: u32,
pub RESERVED4: [u8; 8usize],
pub SAR3: u32,
pub DAR3: u32,
pub DTCTL3: u32,
pub __bindgen_anon_10: CM_DMA_TypeDef__bindgen_ty_10,
pub __bindgen_anon_11: CM_DMA_TypeDef__bindgen_ty_11,
pub __bindgen_anon_12: CM_DMA_TypeDef__bindgen_ty_12,
pub LLP3: u32,
pub CHCTL3: u32,
pub MONSAR3: u32,
pub MONDAR3: u32,
pub MONDTCTL3: u32,
pub MONRPT3: u32,
pub MONSNSEQCTL3: u32,
pub MONDNSEQCTL3: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_1 {
pub RPT0: u32,
pub RPTB0: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_2 {
pub SNSEQCTL0: u32,
pub SNSEQCTLB0: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_3 {
pub DNSEQCTL0: u32,
pub DNSEQCTLB0: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_4 {
pub RPT1: u32,
pub RPTB1: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_5 {
pub SNSEQCTL1: u32,
pub SNSEQCTLB1: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_6 {
pub DNSEQCTL1: u32,
pub DNSEQCTLB1: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_7 {
pub RPT2: u32,
pub RPTB2: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_8 {
pub SNSEQCTL2: u32,
pub SNSEQCTLB2: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_9 {
pub DNSEQCTL2: u32,
pub DNSEQCTLB2: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_10 {
pub RPT3: u32,
pub RPTB3: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_11 {
pub SNSEQCTL3: u32,
pub SNSEQCTLB3: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union CM_DMA_TypeDef__bindgen_ty_12 {
pub DNSEQCTL3: u32,
pub DNSEQCTLB3: u32,
}
#[doc = " @brief EMB"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_EMB_TypeDef {
pub CTL: u32,
pub PWMLV: u32,
pub SOE: u32,
pub STAT: u32,
pub STATCLR: u32,
pub INTEN: u32,
}
#[doc = " @brief FCM"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_FCM_TypeDef {
pub LVR: u32,
pub UVR: u32,
pub CNTR: u32,
pub STR: u32,
pub MCCR: u32,
pub RCCR: u32,
pub RIER: u32,
pub SR: u32,
pub CLR: u32,
}
#[doc = " @brief I2C"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_I2C_TypeDef {
pub CR1: u32,
pub CR2: u32,
pub CR3: u32,
pub CR4: u32,
pub SLR0: u32,
pub SLR1: u32,
pub SLTR: u32,
pub SR: u32,
pub CLR: u32,
pub DTR: u8,
pub RESERVED0: [u8; 3usize],
pub DRR: u8,
pub RESERVED1: [u8; 3usize],
pub CCR: u32,
pub FLTR: u32,
}
#[doc = " @brief I2S"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_I2S_TypeDef {
pub CTRL: u32,
pub SR: u32,
pub ER: u32,
pub CFGR: u32,
pub TXBUF: u32,
pub RXBUF: u32,
pub PR: u32,
}
#[doc = " @brief SDIOC"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_SDIOC_TypeDef {
pub RESERVED0: [u8; 4usize],
pub BLKSIZE: u16,
pub BLKCNT: u16,
pub ARG0: u16,
pub ARG1: u16,
pub TRANSMODE: u16,
pub CMD: u16,
pub RESP0: u16,
pub RESP1: u16,
pub RESP2: u16,
pub RESP3: u16,
pub RESP4: u16,
pub RESP5: u16,
pub RESP6: u16,
pub RESP7: u16,
pub BUF0: u16,
pub BUF1: u16,
pub PSTAT: u32,
pub HOSTCON: u8,
pub PWRCON: u8,
pub BLKGPCON: u8,
pub RESERVED1: [u8; 1usize],
pub CLKCON: u16,
pub TOUTCON: u8,
pub SFTRST: u8,
pub NORINTST: u16,
pub ERRINTST: u16,
pub NORINTSTEN: u16,
pub ERRINTSTEN: u16,
pub NORINTSGEN: u16,
pub ERRINTSGEN: u16,
pub ATCERRST: u16,
pub RESERVED2: [u8; 18usize],
pub FEA: u16,
pub FEE: u16,
}
#[doc = " @brief SPI"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_SPI_TypeDef {
pub DR: u32,
pub CR1: u32,
pub RESERVED0: [u8; 4usize],
pub CFG1: u32,
pub RESERVED1: [u8; 4usize],
pub SR: u32,
pub CFG2: u32,
}
#[doc = " @brief TMR0"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMR0_TypeDef {
pub CNTAR: u32,
pub CNTBR: u32,
pub CMPAR: u32,
pub CMPBR: u32,
pub BCONR: u32,
pub STFLR: u32,
}
#[doc = " @brief TMR4"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMR4_TypeDef {
pub RESERVED0: [u8; 2usize],
pub OCCRUH: u16,
pub RESERVED1: [u8; 2usize],
pub OCCRUL: u16,
pub RESERVED2: [u8; 2usize],
pub OCCRVH: u16,
pub RESERVED3: [u8; 2usize],
pub OCCRVL: u16,
pub RESERVED4: [u8; 2usize],
pub OCCRWH: u16,
pub RESERVED5: [u8; 2usize],
pub OCCRWL: u16,
pub OCSRU: u16,
pub OCERU: u16,
pub OCSRV: u16,
pub OCERV: u16,
pub OCSRW: u16,
pub OCERW: u16,
pub OCMRUH: u16,
pub RESERVED6: [u8; 2usize],
pub OCMRUL: u32,
pub OCMRVH: u16,
pub RESERVED7: [u8; 2usize],
pub OCMRVL: u32,
pub OCMRWH: u16,
pub RESERVED8: [u8; 2usize],
pub OCMRWL: u32,
pub RESERVED9: [u8; 6usize],
pub CPSR: u16,
pub RESERVED10: [u8; 2usize],
pub CNTR: u16,
pub CCSR: u16,
pub CVPR: u16,
pub RESERVED11: [u8; 54usize],
pub PFSRU: u16,
pub PDARU: u16,
pub PDBRU: u16,
pub RESERVED12: [u8; 2usize],
pub PFSRV: u16,
pub PDARV: u16,
pub PDBRV: u16,
pub RESERVED13: [u8; 2usize],
pub PFSRW: u16,
pub PDARW: u16,
pub PDBRW: u16,
pub POCRU: u16,
pub RESERVED14: [u8; 2usize],
pub POCRV: u16,
pub RESERVED15: [u8; 2usize],
pub POCRW: u16,
pub RESERVED16: [u8; 2usize],
pub RCSR: u16,
pub RESERVED17: [u8; 12usize],
pub SCCRUH: u16,
pub RESERVED18: [u8; 2usize],
pub SCCRUL: u16,
pub RESERVED19: [u8; 2usize],
pub SCCRVH: u16,
pub RESERVED20: [u8; 2usize],
pub SCCRVL: u16,
pub RESERVED21: [u8; 2usize],
pub SCCRWH: u16,
pub RESERVED22: [u8; 2usize],
pub SCCRWL: u16,
pub SCSRUH: u16,
pub SCMRUH: u16,
pub SCSRUL: u16,
pub SCMRUL: u16,
pub SCSRVH: u16,
pub SCMRVH: u16,
pub SCSRVL: u16,
pub SCMRVL: u16,
pub SCSRWH: u16,
pub SCMRWH: u16,
pub SCSRWL: u16,
pub SCMRWL: u16,
pub RESERVED23: [u8; 16usize],
pub ECSR: u16,
}
#[doc = " @brief TMR6"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMR6_TypeDef {
pub CNTER: u32,
pub PERAR: u32,
pub PERBR: u32,
pub PERCR: u32,
pub GCMAR: u32,
pub GCMBR: u32,
pub GCMCR: u32,
pub GCMDR: u32,
pub GCMER: u32,
pub GCMFR: u32,
pub SCMAR: u32,
pub SCMBR: u32,
pub SCMCR: u32,
pub SCMDR: u32,
pub SCMER: u32,
pub SCMFR: u32,
pub DTUAR: u32,
pub DTDAR: u32,
pub DTUBR: u32,
pub DTDBR: u32,
pub GCONR: u32,
pub ICONR: u32,
pub PCONR: u32,
pub BCONR: u32,
pub DCONR: u32,
pub RESERVED0: [u8; 4usize],
pub FCONR: u32,
pub VPERR: u32,
pub STFLR: u32,
pub HSTAR: u32,
pub HSTPR: u32,
pub HCLRR: u32,
pub HCPAR: u32,
pub HCPBR: u32,
pub HCUPR: u32,
pub HCDOR: u32,
}
#[doc = " @brief TMRA"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMRA_TypeDef {
pub CNTER: u16,
pub RESERVED0: [u8; 2usize],
pub PERAR: u16,
pub RESERVED1: [u8; 58usize],
pub CMPAR1: u16,
pub RESERVED2: [u8; 2usize],
pub CMPAR2: u16,
pub RESERVED3: [u8; 2usize],
pub CMPAR3: u16,
pub RESERVED4: [u8; 2usize],
pub CMPAR4: u16,
pub RESERVED5: [u8; 2usize],
pub CMPAR5: u16,
pub RESERVED6: [u8; 2usize],
pub CMPAR6: u16,
pub RESERVED7: [u8; 2usize],
pub CMPAR7: u16,
pub RESERVED8: [u8; 2usize],
pub CMPAR8: u16,
pub RESERVED9: [u8; 34usize],
pub BCSTRL: u8,
pub BCSTRH: u8,
pub RESERVED10: [u8; 2usize],
pub HCONR: u16,
pub RESERVED11: [u8; 2usize],
pub HCUPR: u16,
pub RESERVED12: [u8; 2usize],
pub HCDOR: u16,
pub RESERVED13: [u8; 2usize],
pub ICONR: u16,
pub RESERVED14: [u8; 2usize],
pub ECONR: u16,
pub RESERVED15: [u8; 2usize],
pub FCONR: u16,
pub RESERVED16: [u8; 2usize],
pub STFLR: u16,
pub RESERVED17: [u8; 34usize],
pub BCONR1: u16,
pub RESERVED18: [u8; 6usize],
pub BCONR2: u16,
pub RESERVED19: [u8; 6usize],
pub BCONR3: u16,
pub RESERVED20: [u8; 6usize],
pub BCONR4: u16,
pub RESERVED21: [u8; 38usize],
pub CCONR1: u16,
pub RESERVED22: [u8; 2usize],
pub CCONR2: u16,
pub RESERVED23: [u8; 2usize],
pub CCONR3: u16,
pub RESERVED24: [u8; 2usize],
pub CCONR4: u16,
pub RESERVED25: [u8; 2usize],
pub CCONR5: u16,
pub RESERVED26: [u8; 2usize],
pub CCONR6: u16,
pub RESERVED27: [u8; 2usize],
pub CCONR7: u16,
pub RESERVED28: [u8; 2usize],
pub CCONR8: u16,
pub RESERVED29: [u8; 34usize],
pub PCONR1: u16,
pub RESERVED30: [u8; 2usize],
pub PCONR2: u16,
pub RESERVED31: [u8; 2usize],
pub PCONR3: u16,
pub RESERVED32: [u8; 2usize],
pub PCONR4: u16,
pub RESERVED33: [u8; 2usize],
pub PCONR5: u16,
pub RESERVED34: [u8; 2usize],
pub PCONR6: u16,
pub RESERVED35: [u8; 2usize],
pub PCONR7: u16,
pub RESERVED36: [u8; 2usize],
pub PCONR8: u16,
}
#[doc = " @brief USART"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_USART_TypeDef {
pub SR: u32,
pub TDR: u16,
pub RDR: u16,
pub BRR: u32,
pub CR1: u32,
pub CR2: u32,
pub CR3: u32,
pub PR: u32,
}
#[doc = " @brief Single precision floating point number (4 byte)"]
pub type float32_t = f32;
#[doc = " @brief Double precision floating point number (8 byte)"]
pub type float64_t = f64;
#[doc = " @brief Function pointer type to void/void function"]
pub type func_ptr_t = ::core::option::Option<unsafe extern "C" fn()>;
pub const en_functional_state_t_DISABLE: en_functional_state_t = 0;
pub const en_functional_state_t_ENABLE: en_functional_state_t = 1;
#[doc = " @brief Functional state"]
pub type en_functional_state_t = ::core::ffi::c_uint;
pub const en_flag_status_t_RESET: en_flag_status_t = 0;
pub const en_flag_status_t_SET: en_flag_status_t = 1;
#[doc = " @brief Flag status"]
pub type en_flag_status_t = ::core::ffi::c_uint;
#[doc = " @brief Flag status"]
pub use self::en_flag_status_t as en_int_status_t;
#[doc = " @}\n/\n/*******************************************************************************\n Global type definitions ('typedef')\n/\n/**\n @defgroup USB_Global_Types USB Global Types\n @{"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct USB_CORE_GREGS {
pub GVBUSCFG: u32,
pub Reserved04: u32,
pub GAHBCFG: u32,
pub GUSBCFG: u32,
pub GRSTCTL: u32,
pub GINTSTS: u32,
pub GINTMSK: u32,
pub GRXSTSR: u32,
pub GRXSTSP: u32,
pub GRXFSIZ: u32,
pub HNPTXFSIZ: u32,
pub HNPTXSTS: u32,
pub Reserved30: [u32; 3usize],
pub CID: u32,
pub Reserved40: [u32; 5usize],
pub GLPMCFG: u32,
pub Reserved58: [u32; 42usize],
pub HPTXFSIZ: u32,
pub DIEPTXF: [u32; 6usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct USB_CORE_DREGS {
pub DCFG: u32,
pub DCTL: u32,
pub DSTS: u32,
pub Reserved0C: u32,
pub DIEPMSK: u32,
pub DOEPMSK: u32,
pub DAINT: u32,
pub DAINTMSK: u32,
pub Reserved20: [u32; 4usize],
pub DTHRCTL: u32,
pub DIEPEMPMSK: u32,
pub DEACHINT: u32,
pub DEACHINTMSK: u32,
pub Reserved40: u32,
pub DIEPEACHMSK1: u32,
pub Reserved48: [u32; 15usize],
pub DOEPEACHMSK1: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct USB_CORE_INEPREGS {
pub DIEPCTL: u32,
pub Reserved04: u32,
pub DIEPINT: u32,
pub Reserved0C: u32,
pub DIEPTSIZ: u32,
pub DIEPDMA: u32,
pub DTXFSTS: u32,
pub Reserved18: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct USB_CORE_OUTEPREGS {
pub DOEPCTL: u32,
pub Reserved04: u32,
pub DOEPINT: u32,
pub Reserved0C: u32,
pub DOEPTSIZ: u32,
pub DOEPDMA: u32,
pub Reserved18: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct USB_CORE_HREGS {
pub HCFG: u32,
pub HFIR: u32,
pub HFNUM: u32,
pub Reserved40C: u32,
pub HPTXSTS: u32,
pub HAINT: u32,
pub HAINTMSK: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct USB_CORE_HC_REGS {
pub HCCHAR: u32,
pub HCSPLT: u32,
pub HCINT: u32,
pub HCINTMSK: u32,
pub HCTSIZ: u32,
pub HCDMA: u32,
pub Reserved: [u32; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct LL_USB_TypeDef {
pub GREGS: *mut USB_CORE_GREGS,
pub DREGS: *mut USB_CORE_DREGS,
pub HREGS: *mut USB_CORE_HREGS,
pub INEP_REGS: [*mut USB_CORE_INEPREGS; 6usize],
pub OUTEP_REGS: [*mut USB_CORE_OUTEPREGS; 6usize],
pub HC_REGS: [*mut USB_CORE_HC_REGS; 12usize],
pub HPRT: *mut u32,
pub DFIFO: [*mut u32; 6usize],
pub GCCTL: *mut u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct USB_CORE_BASIC_CFGS {
pub host_chnum: u8,
pub dev_epnum: u8,
pub dmaen: u8,
pub low_power: u8,
pub phy_type: u8,
pub core_type: u8,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct USB_HOST_CH {
pub dev_addr: u8,
pub ep_idx: u8,
pub is_epin: u8,
pub ch_speed: u8,
pub do_ping: u8,
pub ep_type: u8,
pub max_packet: u16,
pub pid_type: u8,
pub in_toggle: u8,
pub out_toggle: u8,
pub dma_addr: u32,
pub xfer_len: u32,
pub xfer_count: u32,
pub xfer_buff: *mut u8,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct USB_DEV_EP {
pub epidx: u8,
pub ep_dir: u8,
pub trans_type: u8,
pub ep_stall: u8,
pub data_pid_start: u8,
pub datax_pid: u8,
pub tx_fifo_num: u16,
pub maxpacket: u32,
pub rem_data_len: u32,
pub total_data_len: u32,
pub ctl_data_len: u32,
pub dma_addr: u32,
pub xfer_len: u32,
pub xfer_count: u32,
pub xfer_buff: *mut u8,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usb_port_identify {
pub u8CoreID: u8,
}
pub const HOST_CH_STATUS_HOST_CH_IDLE: HOST_CH_STATUS = 0;
pub const HOST_CH_STATUS_HOST_CH_XFERCOMPL: HOST_CH_STATUS = 1;
pub const HOST_CH_STATUS_HOST_CH_CHHLTD: HOST_CH_STATUS = 2;
pub const HOST_CH_STATUS_HOST_CH_NAK: HOST_CH_STATUS = 3;
pub const HOST_CH_STATUS_HOST_CH_NYET: HOST_CH_STATUS = 4;
pub const HOST_CH_STATUS_HOST_CH_STALL: HOST_CH_STATUS = 5;
pub const HOST_CH_STATUS_HOST_CH_XACTERR: HOST_CH_STATUS = 6;
pub const HOST_CH_STATUS_HOST_CH_BBLERR: HOST_CH_STATUS = 7;
pub const HOST_CH_STATUS_HOST_CH_DATATGLERR: HOST_CH_STATUS = 8;
pub const HOST_CH_STATUS_HOST_CH_AHBERR: HOST_CH_STATUS = 9;
pub const HOST_CH_STATUS_HOST_CH_FRMOVRUN: HOST_CH_STATUS = 10;
pub const HOST_CH_STATUS_HOST_CH_BNAINTR: HOST_CH_STATUS = 11;
pub const HOST_CH_STATUS_HOST_CH_XCS_XACT_ERR: HOST_CH_STATUS = 12;
pub const HOST_CH_STATUS_HOST_CH_DESC_LST_ROLLINTR: HOST_CH_STATUS = 13;
#[doc = " Global type definitions ('typedef')"]
pub type HOST_CH_STATUS = ::core::ffi::c_uint;
pub const HOST_CH_XFER_STATE_HOST_CH_XFER_IDLE: HOST_CH_XFER_STATE = 0;
pub const HOST_CH_XFER_STATE_HOST_CH_XFER_DONE: HOST_CH_XFER_STATE = 1;
pub const HOST_CH_XFER_STATE_HOST_CH_XFER_UNREADY: HOST_CH_XFER_STATE = 2;
pub const HOST_CH_XFER_STATE_HOST_CH_XFER_ERROR: HOST_CH_XFER_STATE = 3;
pub const HOST_CH_XFER_STATE_HOST_CH_XFER_STALL: HOST_CH_XFER_STATE = 4;
pub type HOST_CH_XFER_STATE = ::core::ffi::c_uint;
pub const CTRL_HANDLE_STATUS_CTRL_START: CTRL_HANDLE_STATUS = 0;
pub const CTRL_HANDLE_STATUS_CTRL_XFRC: CTRL_HANDLE_STATUS = 1;
pub const CTRL_HANDLE_STATUS_CTRL_HALTED: CTRL_HANDLE_STATUS = 2;
pub const CTRL_HANDLE_STATUS_CTRL_NAK: CTRL_HANDLE_STATUS = 3;
pub const CTRL_HANDLE_STATUS_CTRL_STALL: CTRL_HANDLE_STATUS = 4;
pub const CTRL_HANDLE_STATUS_CTRL_XACTERR: CTRL_HANDLE_STATUS = 5;
pub const CTRL_HANDLE_STATUS_CTRL_BBLERR: CTRL_HANDLE_STATUS = 6;
pub const CTRL_HANDLE_STATUS_CTRL_DATATGLERR: CTRL_HANDLE_STATUS = 7;
pub const CTRL_HANDLE_STATUS_CTRL_FAIL: CTRL_HANDLE_STATUS = 8;
pub type CTRL_HANDLE_STATUS = ::core::ffi::c_uint;
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct USB_SETUP_REQ {
pub bmRequest: u8,
pub bRequest: u8,
pub wValue: u16,
pub wIndex: u16,
pub wLength: u16,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct usb_dev_desc_func {
pub get_dev_desc: ::core::option::Option<unsafe extern "C" fn(length: *mut u16) -> *mut u8>,
pub get_dev_langiddesc:
::core::option::Option<unsafe extern "C" fn(length: *mut u16) -> *mut u8>,
pub get_dev_manufacturerstr:
::core::option::Option<unsafe extern "C" fn(length: *mut u16) -> *mut u8>,
pub get_dev_productstr:
::core::option::Option<unsafe extern "C" fn(length: *mut u16) -> *mut u8>,
pub get_dev_serialstr:
::core::option::Option<unsafe extern "C" fn(length: *mut u16) -> *mut u8>,
pub get_dev_configstr:
::core::option::Option<unsafe extern "C" fn(length: *mut u16) -> *mut u8>,
pub get_dev_interfacestr:
::core::option::Option<unsafe extern "C" fn(length: *mut u16) -> *mut u8>,
pub get_dev_winusbosstr:
::core::option::Option<unsafe extern "C" fn(length: *mut u16) -> *mut u8>,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct usb_dev_class_func {
pub class_init: ::core::option::Option<unsafe extern "C" fn(pdev: *mut ::core::ffi::c_void)>,
pub class_deinit: ::core::option::Option<unsafe extern "C" fn(pdev: *mut ::core::ffi::c_void)>,
pub ep0_setup: ::core::option::Option<
unsafe extern "C" fn(pdev: *mut ::core::ffi::c_void, req: *mut USB_SETUP_REQ) -> u8,
>,
pub ep0_datain: ::core::option::Option<unsafe extern "C" fn(pdev: *mut ::core::ffi::c_void)>,
pub ep0_dataout: ::core::option::Option<unsafe extern "C" fn(pdev: *mut ::core::ffi::c_void)>,
pub class_getconfigdesc:
::core::option::Option<unsafe extern "C" fn(length: *mut u16) -> *mut u8>,
pub class_sof:
::core::option::Option<unsafe extern "C" fn(pdev: *mut ::core::ffi::c_void) -> u8>,
pub class_datain:
::core::option::Option<unsafe extern "C" fn(pdev: *mut ::core::ffi::c_void, epnum: u8)>,
pub class_dataout:
::core::option::Option<unsafe extern "C" fn(pdev: *mut ::core::ffi::c_void, epnum: u8)>,
pub class_syn_in_incomplt:
::core::option::Option<unsafe extern "C" fn(pdev: *mut ::core::ffi::c_void)>,
pub class_syn_out_incomplt:
::core::option::Option<unsafe extern "C" fn(pdev: *mut ::core::ffi::c_void)>,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct usb_dev_user_func {
pub user_init: ::core::option::Option<unsafe extern "C" fn()>,
pub user_devrst: ::core::option::Option<unsafe extern "C" fn()>,
pub user_devconfig: ::core::option::Option<unsafe extern "C" fn()>,
pub user_devsusp: ::core::option::Option<unsafe extern "C" fn()>,
pub user_devresume: ::core::option::Option<unsafe extern "C" fn()>,
pub user_devconn: ::core::option::Option<unsafe extern "C" fn()>,
pub user_devdisconn: ::core::option::Option<unsafe extern "C" fn()>,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct USB_DEV_PARAM {
pub device_config: u8,
pub device_address: u8,
pub device_state: u8,
pub device_old_status: u8,
pub device_cur_status: u8,
pub connection_status: u8,
pub device_remote_wakeup: u8,
pub test_mode: u8,
pub in_ep: [USB_DEV_EP; 6usize],
pub out_ep: [USB_DEV_EP; 6usize],
pub setup_pkt_buf: [u8; 24usize],
pub class_callback: *mut usb_dev_class_func,
pub user_callback: *mut usb_dev_user_func,
pub desc_callback: *mut usb_dev_desc_func,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct USB_HOST_PARAM {
pub channel: [u16; 12usize],
pub hc: [USB_HOST_CH; 12usize],
pub is_dev_connect: u32,
pub Rx_Buffer: [u8; 512usize],
pub ErrCnt: [u32; 12usize],
pub XferCnt: [u32; 12usize],
pub HC_Status: [HOST_CH_STATUS; 12usize],
pub URB_State: [HOST_CH_XFER_STATE; 12usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct usb_core_instance {
pub basic_cfgs: USB_CORE_BASIC_CFGS,
pub regs: LL_USB_TypeDef,
pub dev: USB_DEV_PARAM,
}
#[doc = " Global type definitions ('typedef')\n/\n/**\n @defgroup ADC_Global_Types ADC Global Types\n @{\n/\n/**\n @brief Structure definition of analog watchdog(AWD) configuration."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_awd_config_t {
#[doc = "< Specifies the ADC analog watchdog mode.\nThis parameter can be a value of @ref ADC_AWD_Mode"]
pub u16WatchdogMode: u16,
#[doc = "< Specifies the ADC analog watchdog Low threshold value."]
pub u16LowThreshold: u16,
#[doc = "< Specifies the ADC analog watchdog High threshold value."]
pub u16HighThreshold: u16,
}
#[doc = " @brief Structure definition of ADC initialization."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_adc_init_t {
#[doc = "< Specifies the ADC scan convert mode.\nThis parameter can be a value of @ref ADC_Scan_Mode"]
pub u16ScanMode: u16,
#[doc = "< Specifies the ADC resolution.\nThis parameter can be a value of @ref ADC_Resolution"]
pub u16Resolution: u16,
#[doc = "< Specifies ADC data alignment.\nThis parameter can be a value of @ref ADC_Data_Align"]
pub u16DataAlign: u16,
}
#[doc = " Global type definitions ('typedef')\n/\n/**\n @defgroup CAN_Global_Types CAN Global Types\n @{\n/\n/**\n @brief CAN bit time configuration structure.\n @note 1. TQ = u32Prescaler / CANClock.\n @note 2. Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.\n @note 3. Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))\n @note 4. See user manual of the target MCU and ISO11898-1 for more details."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_bit_time_config_t {
#[doc = "< Specifies the prescaler of CAN clock, [1, 256]."]
pub u32Prescaler: u32,
#[doc = "< Specifies the number of time quanta in Bit Segment 1.\nu32TimeSeg1 Contains synchronization segment,\npropagation time segment and phase buffer segment 1."]
pub u32TimeSeg1: u32,
#[doc = "< Specifies the number of time quanta in Bit Segment 2.\nPhase buffer segment 2."]
pub u32TimeSeg2: u32,
#[doc = "< Synchronization Jump Width.\nSpecifies the maximum number of time quanta the CAN hardware\nis allowed to lengthen or shorten a bit to perform resynchronization."]
pub u32SJW: u32,
}
#[doc = " @brief CAN acceptance filter configuration structure."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_filter_config_t {
#[doc = "< Specifies the identifier(ID). 11 bits standard ID or 29 bits extended ID, depending on IDE."]
pub u32ID: u32,
#[doc = "< Specifies the identifier(ID) mask. The mask bits of ID will be ignored by the acceptance filter."]
pub u32IDMask: u32,
#[doc = "< Specifies the identifier(ID) type. This parameter can be a value of @ref CAN_ID_Type"]
pub u32IDType: u32,
}
#[doc = " @brief TTCAN configuration structure."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_ttc_config_t {
#[doc = "< Reference message identifier."]
pub u32RefMsgID: u32,
#[doc = "< Reference message identifier extension bit.\n'1' to set the ID which is specified by parameter 'u32RefMsgID' as an extended ID while\n'0' to set it as a standard ID."]
pub u32RefMsgIDE: u32,
#[doc = "< Prescaler of NTU(network time unit). The source is the bit time which is defined by SBT.\nThis parameter can be a value of @ref TTCAN_NTU_Prescaler"]
pub u8NTUPrescaler: u8,
#[doc = "< TTCAN Transmit Buffer Mode.\nThis parameter can be a value of @ref TTCAN_Tx_Buf_Mode"]
pub u8TxBufMode: u8,
#[doc = "< Trigger type of TTCAN.\nThis parameter can be a value of @ref TTCAN_Trigger_Type"]
pub u16TriggerType: u16,
#[doc = "< Tx_Enable window. Time period within which the transmission of a message may be started. Range is [1, 16]"]
pub u16TxEnableWindow: u16,
#[doc = "< Specifies for the referred message the time window of the matrix cycle at which it is to be transmitted. Range is [0, 65535]"]
pub u16TxTriggerTime: u16,
#[doc = "< Time mark used to check whether the time since the last valid reference message has been too long. Range is [0, 65535]"]
pub u16WatchTriggerTime: u16,
}
#[doc = " @brief CAN initialization structure."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_init_t {
#[doc = "< Bit time configuration of classical CAN bit. @ref stc_can_bit_time_config_t"]
pub stcBitCfg: stc_can_bit_time_config_t,
#[doc = "< Pointer to a @ref stc_can_filter_config_t structure that\ncontains the configuration informations for the acceptance filters."]
pub pstcFilter: *mut stc_can_filter_config_t,
#[doc = "< Selects acceptance filters.\nThis parameter can be values of @ref CAN_Acceptance_Filter"]
pub u16FilterSelect: u16,
#[doc = "< Specifies the work mode of CAN.\nThis parameter can be a value of @ref CAN_Work_Mode"]
pub u8WorkMode: u8,
#[doc = "< Enable or disable single shot transmission of PTB.\nThis parameter can be a value of @ref PTB_SingleShot_Tx_En"]
pub u8PTBSingleShotTx: u8,
#[doc = "< Enable or disable single shot transmission of STB.\nThis parameter can be a value of @ref STB_SingleShot_Tx_En"]
pub u8STBSingleShotTx: u8,
#[doc = "< Enable or disable the priority decision mode of STB.\nThis parameter can be a value of @ref CAN_STB_Prio_Mode_En\nNOTE: A frame in the PTB has always the highest priority regardless of the ID."]
pub u8STBPrioMode: u8,
#[doc = "< Specifies receive buffer almost full warning limit. Rang is [1, 8].\nEach CAN unit has 8 receive buffers. When the number of received frames reaches\nthe value specified by u8RxWarnLimit, register bit RTIF.RAFIF is set and the interrupt occurred\nif it was enabled."]
pub u8RxWarnLimit: u8,
#[doc = "< Specifies programmable error warning limit. Range is [0, 15].\nError warning limit = (u8ErrorWarnLimit + 1) * 8."]
pub u8ErrorWarnLimit: u8,
#[doc = "< Enable or disable receive all frames(includes frames with error).\nThis parameter can be a value of @ref CAN_Rx_All_En"]
pub u8RxAllFrame: u8,
#[doc = "< Receive buffer overflow mode. In case of a full receive buffer when a new frame is received.\nThis parameter can be a value of @ref CAN_Rx_Ovf_Mode"]
pub u8RxOvfMode: u8,
#[doc = "< Enable or disable self-acknowledge.\nThis parameter can be a value of @ref CAN_Self_ACK_En"]
pub u8SelfAck: u8,
#[doc = "< Pointer to a TTCAN configuration structure. @ref stc_can_ttc_config_t\nSet it to NULL if not needed TTCAN."]
pub pstcCanTtc: *mut stc_can_ttc_config_t,
}
#[doc = " @brief CAN error information structure."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_error_info_t {
#[doc = "< Bit position in the frame where the arbitration has been lost."]
pub u8ArbitrLostPos: u8,
#[doc = "< CAN error type. This parameter can be a value of @ref CAN_Err_Type"]
pub u8ErrorType: u8,
#[doc = "< Receive error count."]
pub u8RxErrorCount: u8,
#[doc = "< Transmit error count."]
pub u8TxErrorCount: u8,
}
#[doc = " @brief CAN TX frame data structure."]
#[repr(C)]
#[derive(Copy, Clone)]
pub struct stc_can_tx_frame_t {
#[doc = "< 11 bits standard ID or 29 bits extended ID, depending on IDE."]
pub u32ID: u32,
pub __bindgen_anon_1: stc_can_tx_frame_t__bindgen_ty_1,
#[doc = "< TX data payload."]
pub au8Data: [u8; 8usize],
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union stc_can_tx_frame_t__bindgen_ty_1 {
pub u32Ctrl: u32,
pub __bindgen_anon_1: stc_can_tx_frame_t__bindgen_ty_1__bindgen_ty_1,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_tx_frame_t__bindgen_ty_1__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl stc_can_tx_frame_t__bindgen_ty_1__bindgen_ty_1 {
#[inline]
pub fn DLC(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 4u8) as u32) }
}
#[inline]
pub fn set_DLC(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 4u8, val as u64)
}
}
#[inline]
pub unsafe fn DLC_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
0usize,
4u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_DLC_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
0usize,
4u8,
val as u64,
)
}
}
#[inline]
pub fn BRS(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_BRS(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn BRS_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
4usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_BRS_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
4usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn FDF(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_FDF(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn FDF_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
5usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_FDF_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
5usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn RTR(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_RTR(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn RTR_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
6usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_RTR_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
6usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn IDE(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_IDE(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn IDE_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
7usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_IDE_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
7usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn RSVD(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_RSVD(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub unsafe fn RSVD_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
8usize,
24u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_RSVD_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
8usize,
24u8,
val as u64,
)
}
}
#[inline]
pub fn new_bitfield_1(
DLC: u32,
BRS: u32,
FDF: u32,
RTR: u32,
IDE: u32,
RSVD: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 4u8, {
let DLC: u32 = unsafe { ::core::mem::transmute(DLC) };
DLC as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let BRS: u32 = unsafe { ::core::mem::transmute(BRS) };
BRS as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let FDF: u32 = unsafe { ::core::mem::transmute(FDF) };
FDF as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let RTR: u32 = unsafe { ::core::mem::transmute(RTR) };
RTR as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let IDE: u32 = unsafe { ::core::mem::transmute(IDE) };
IDE as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let RSVD: u32 = unsafe { ::core::mem::transmute(RSVD) };
RSVD as u64
});
__bindgen_bitfield_unit
}
}
#[doc = " @brief CAN RX frame data structure."]
#[repr(C)]
#[derive(Copy, Clone)]
pub struct stc_can_rx_frame_t {
#[doc = "< 11 bits standard ID or 29 bits extended ID, depending on IDE."]
pub u32ID: u32,
pub __bindgen_anon_1: stc_can_rx_frame_t__bindgen_ty_1,
#[doc = "< RX data payload."]
pub au8Data: [u8; 8usize],
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union stc_can_rx_frame_t__bindgen_ty_1 {
pub u32Ctrl: u32,
pub __bindgen_anon_1: stc_can_rx_frame_t__bindgen_ty_1__bindgen_ty_1,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_can_rx_frame_t__bindgen_ty_1__bindgen_ty_1 {
pub _bitfield_align_1: [u16; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl stc_can_rx_frame_t__bindgen_ty_1__bindgen_ty_1 {
#[inline]
pub fn DLC(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 4u8) as u32) }
}
#[inline]
pub fn set_DLC(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 4u8, val as u64)
}
}
#[inline]
pub unsafe fn DLC_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
0usize,
4u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_DLC_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
0usize,
4u8,
val as u64,
)
}
}
#[inline]
pub fn BRS(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_BRS(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn BRS_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
4usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_BRS_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
4usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn FDF(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_FDF(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn FDF_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
5usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_FDF_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
5usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn RTR(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_RTR(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn RTR_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
6usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_RTR_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
6usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn IDE(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_IDE(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn IDE_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
7usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_IDE_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
7usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn RSVD(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 4u8) as u32) }
}
#[inline]
pub fn set_RSVD(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 4u8, val as u64)
}
}
#[inline]
pub unsafe fn RSVD_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
8usize,
4u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_RSVD_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
8usize,
4u8,
val as u64,
)
}
}
#[inline]
pub fn TX(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_TX(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn TX_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
12usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_TX_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
12usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn ERRT(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 3u8) as u32) }
}
#[inline]
pub fn set_ERRT(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 3u8, val as u64)
}
}
#[inline]
pub unsafe fn ERRT_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
13usize,
3u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_ERRT_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
13usize,
3u8,
val as u64,
)
}
}
#[inline]
pub fn CYCLE_TIME(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
}
#[inline]
pub fn set_CYCLE_TIME(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 16u8, val as u64)
}
}
#[inline]
pub unsafe fn CYCLE_TIME_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
16usize,
16u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_CYCLE_TIME_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
16usize,
16u8,
val as u64,
)
}
}
#[inline]
pub fn new_bitfield_1(
DLC: u32,
BRS: u32,
FDF: u32,
RTR: u32,
IDE: u32,
RSVD: u32,
TX: u32,
ERRT: u32,
CYCLE_TIME: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 4u8, {
let DLC: u32 = unsafe { ::core::mem::transmute(DLC) };
DLC as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let BRS: u32 = unsafe { ::core::mem::transmute(BRS) };
BRS as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let FDF: u32 = unsafe { ::core::mem::transmute(FDF) };
FDF as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let RTR: u32 = unsafe { ::core::mem::transmute(RTR) };
RTR as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let IDE: u32 = unsafe { ::core::mem::transmute(IDE) };
IDE as u64
});
__bindgen_bitfield_unit.set(8usize, 4u8, {
let RSVD: u32 = unsafe { ::core::mem::transmute(RSVD) };
RSVD as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let TX: u32 = unsafe { ::core::mem::transmute(TX) };
TX as u64
});
__bindgen_bitfield_unit.set(13usize, 3u8, {
let ERRT: u32 = unsafe { ::core::mem::transmute(ERRT) };
ERRT as u64
});
__bindgen_bitfield_unit.set(16usize, 16u8, {
let CYCLE_TIME: u32 = unsafe { ::core::mem::transmute(CYCLE_TIME) };
CYCLE_TIME as u64
});
__bindgen_bitfield_unit
}
}
#[doc = " Global type definitions ('typedef')\n/\n/**\n @defgroup CLK_Global_Types CLK Global Types\n @{\n/\n/**\n @brief CLK XTAL configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_clock_xtal_init_t {
#[doc = "< The new state of the XTAL.\nThis parameter can be a value of @ref CLK_XTAL_State"]
pub u8State: u8,
#[doc = "< The XTAL drive ability.\nThis parameter can be a value of @ref CLK_XTAL_Driver"]
pub u8Drv: u8,
#[doc = "< The XTAL mode selection osc or exclk.\nThis parameter can be a value of @ref CLK_XTAL_Mode_Selection"]
pub u8Mode: u8,
#[doc = "< The XTAL super drive on or off.\nThis parameter can be a value of @ref CLK_XTAL_Super_Drive_State"]
pub u8SuperDrv: u8,
#[doc = "< The XTAL stable time selection.\nThis parameter can be a value of @ref CLK_XTAL_Stable_Time_Selection"]
pub u8StableTime: u8,
}
#[doc = " @brief CLK XTAL fault detect configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_clock_xtalstd_init_t {
#[doc = "< Specifies the new state of XTALSTD.\nThis parameter can be a value of @ref CLK_XTALSTD_State"]
pub u8State: u8,
#[doc = "< Specifies the XTALSTD exception type.\nThis parameter can be a value of @ref CLK_XTALSTD_Exception_type"]
pub u8ExceptionType: u8,
}
#[doc = " @brief CLK XTAL32 configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_clock_xtal32_init_t {
#[doc = "< The new state of the XTAL32 divide.\nThis parameter can be a value of @ref CLK_XTAL32_State"]
pub u8State: u8,
#[doc = "< The Xtal32 drive ability setting,\nThis parameter can be a value of @ref CLK_XTAL32_Drive"]
pub u8Drv: u8,
#[doc = "< Xtal32 noise filter setting,\nThis parameter can be a value of@ref CLK_XTAL32_Filter_Selection"]
pub u8Filter: u8,
}
#[doc = " @brief CLK clock frequency configuration structure definition"]
#[repr(C)]
#[derive(Copy, Clone)]
pub struct stc_clock_scale_t {
pub __bindgen_anon_1: stc_clock_scale_t__bindgen_ty_1,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union stc_clock_scale_t__bindgen_ty_1 {
#[doc = "< clock frequency config register"]
pub SCFGR: u32,
pub SCFGR_f: stc_clock_scale_t__bindgen_ty_1__bindgen_ty_1,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_clock_scale_t__bindgen_ty_1__bindgen_ty_1 {
pub _bitfield_align_1: [u8; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl stc_clock_scale_t__bindgen_ty_1__bindgen_ty_1 {
#[inline]
pub fn PCLK0S(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 3u8) as u32) }
}
#[inline]
pub fn set_PCLK0S(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 3u8, val as u64)
}
}
#[inline]
pub unsafe fn PCLK0S_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
0usize,
3u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PCLK0S_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
0usize,
3u8,
val as u64,
)
}
}
#[inline]
pub fn resvd0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_resvd0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn resvd0_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
3usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_resvd0_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
3usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn PCLK1S(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 3u8) as u32) }
}
#[inline]
pub fn set_PCLK1S(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 3u8, val as u64)
}
}
#[inline]
pub unsafe fn PCLK1S_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
4usize,
3u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PCLK1S_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
4usize,
3u8,
val as u64,
)
}
}
#[inline]
pub fn resvd1(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_resvd1(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn resvd1_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
7usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_resvd1_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
7usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn PCLK2S(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 3u8) as u32) }
}
#[inline]
pub fn set_PCLK2S(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 3u8, val as u64)
}
}
#[inline]
pub unsafe fn PCLK2S_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
8usize,
3u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PCLK2S_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
8usize,
3u8,
val as u64,
)
}
}
#[inline]
pub fn resvd2(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_resvd2(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn resvd2_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
11usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_resvd2_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
11usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn PCLK3S(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 3u8) as u32) }
}
#[inline]
pub fn set_PCLK3S(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 3u8, val as u64)
}
}
#[inline]
pub unsafe fn PCLK3S_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
12usize,
3u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PCLK3S_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
12usize,
3u8,
val as u64,
)
}
}
#[inline]
pub fn resvd3(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_resvd3(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn resvd3_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
15usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_resvd3_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
15usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn PCLK4S(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 3u8) as u32) }
}
#[inline]
pub fn set_PCLK4S(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 3u8, val as u64)
}
}
#[inline]
pub unsafe fn PCLK4S_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
16usize,
3u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PCLK4S_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
16usize,
3u8,
val as u64,
)
}
}
#[inline]
pub fn resvd4(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(19usize, 1u8) as u32) }
}
#[inline]
pub fn set_resvd4(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(19usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn resvd4_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
19usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_resvd4_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
19usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn EXCKS(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 3u8) as u32) }
}
#[inline]
pub fn set_EXCKS(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 3u8, val as u64)
}
}
#[inline]
pub unsafe fn EXCKS_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
20usize,
3u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_EXCKS_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
20usize,
3u8,
val as u64,
)
}
}
#[inline]
pub fn resvd5(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(23usize, 1u8) as u32) }
}
#[inline]
pub fn set_resvd5(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(23usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn resvd5_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
23usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_resvd5_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
23usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn HCLKS(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 3u8) as u32) }
}
#[inline]
pub fn set_HCLKS(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 3u8, val as u64)
}
}
#[inline]
pub unsafe fn HCLKS_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
24usize,
3u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_HCLKS_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
24usize,
3u8,
val as u64,
)
}
}
#[inline]
pub fn resvd6(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(27usize, 5u8) as u32) }
}
#[inline]
pub fn set_resvd6(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(27usize, 5u8, val as u64)
}
}
#[inline]
pub unsafe fn resvd6_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
27usize,
5u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_resvd6_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
27usize,
5u8,
val as u64,
)
}
}
#[inline]
pub fn new_bitfield_1(
PCLK0S: u32,
resvd0: u32,
PCLK1S: u32,
resvd1: u32,
PCLK2S: u32,
resvd2: u32,
PCLK3S: u32,
resvd3: u32,
PCLK4S: u32,
resvd4: u32,
EXCKS: u32,
resvd5: u32,
HCLKS: u32,
resvd6: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 3u8, {
let PCLK0S: u32 = unsafe { ::core::mem::transmute(PCLK0S) };
PCLK0S as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let resvd0: u32 = unsafe { ::core::mem::transmute(resvd0) };
resvd0 as u64
});
__bindgen_bitfield_unit.set(4usize, 3u8, {
let PCLK1S: u32 = unsafe { ::core::mem::transmute(PCLK1S) };
PCLK1S as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let resvd1: u32 = unsafe { ::core::mem::transmute(resvd1) };
resvd1 as u64
});
__bindgen_bitfield_unit.set(8usize, 3u8, {
let PCLK2S: u32 = unsafe { ::core::mem::transmute(PCLK2S) };
PCLK2S as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let resvd2: u32 = unsafe { ::core::mem::transmute(resvd2) };
resvd2 as u64
});
__bindgen_bitfield_unit.set(12usize, 3u8, {
let PCLK3S: u32 = unsafe { ::core::mem::transmute(PCLK3S) };
PCLK3S as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let resvd3: u32 = unsafe { ::core::mem::transmute(resvd3) };
resvd3 as u64
});
__bindgen_bitfield_unit.set(16usize, 3u8, {
let PCLK4S: u32 = unsafe { ::core::mem::transmute(PCLK4S) };
PCLK4S as u64
});
__bindgen_bitfield_unit.set(19usize, 1u8, {
let resvd4: u32 = unsafe { ::core::mem::transmute(resvd4) };
resvd4 as u64
});
__bindgen_bitfield_unit.set(20usize, 3u8, {
let EXCKS: u32 = unsafe { ::core::mem::transmute(EXCKS) };
EXCKS as u64
});
__bindgen_bitfield_unit.set(23usize, 1u8, {
let resvd5: u32 = unsafe { ::core::mem::transmute(resvd5) };
resvd5 as u64
});
__bindgen_bitfield_unit.set(24usize, 3u8, {
let HCLKS: u32 = unsafe { ::core::mem::transmute(HCLKS) };
HCLKS as u64
});
__bindgen_bitfield_unit.set(27usize, 5u8, {
let resvd6: u32 = unsafe { ::core::mem::transmute(resvd6) };
resvd6 as u64
});
__bindgen_bitfield_unit
}
}
#[doc = " @brief CLK PLL configuration structure definition\n @note PLL for MPLL"]
#[repr(C)]
#[derive(Copy, Clone)]
pub struct stc_clock_pll_init_t {
#[doc = "< PLL new state, @ref CLK_PLL_State for details"]
pub u8PLLState: u8,
pub __bindgen_anon_1: stc_clock_pll_init_t__bindgen_ty_1,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union stc_clock_pll_init_t__bindgen_ty_1 {
#[doc = "< PLL config register"]
pub PLLCFGR: u32,
pub PLLCFGR_f: stc_clock_pll_init_t__bindgen_ty_1__bindgen_ty_1,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_clock_pll_init_t__bindgen_ty_1__bindgen_ty_1 {
pub _bitfield_align_1: [u16; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl stc_clock_pll_init_t__bindgen_ty_1__bindgen_ty_1 {
#[inline]
pub fn PLLM(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 5u8) as u32) }
}
#[inline]
pub fn set_PLLM(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 5u8, val as u64)
}
}
#[inline]
pub unsafe fn PLLM_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
0usize,
5u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PLLM_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
0usize,
5u8,
val as u64,
)
}
}
#[inline]
pub fn resvd0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 2u8) as u32) }
}
#[inline]
pub fn set_resvd0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn resvd0_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
5usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_resvd0_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
5usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn PLLSRC(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_PLLSRC(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn PLLSRC_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
7usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PLLSRC_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
7usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn PLLN(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 9u8) as u32) }
}
#[inline]
pub fn set_PLLN(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 9u8, val as u64)
}
}
#[inline]
pub unsafe fn PLLN_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
8usize,
9u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PLLN_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
8usize,
9u8,
val as u64,
)
}
}
#[inline]
pub fn resvd1(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 3u8) as u32) }
}
#[inline]
pub fn set_resvd1(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 3u8, val as u64)
}
}
#[inline]
pub unsafe fn resvd1_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
17usize,
3u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_resvd1_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
17usize,
3u8,
val as u64,
)
}
}
#[inline]
pub fn PLLR(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 4u8) as u32) }
}
#[inline]
pub fn set_PLLR(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 4u8, val as u64)
}
}
#[inline]
pub unsafe fn PLLR_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
20usize,
4u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PLLR_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
20usize,
4u8,
val as u64,
)
}
}
#[inline]
pub fn PLLQ(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 4u8) as u32) }
}
#[inline]
pub fn set_PLLQ(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 4u8, val as u64)
}
}
#[inline]
pub unsafe fn PLLQ_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
24usize,
4u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PLLQ_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
24usize,
4u8,
val as u64,
)
}
}
#[inline]
pub fn PLLP(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 4u8) as u32) }
}
#[inline]
pub fn set_PLLP(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 4u8, val as u64)
}
}
#[inline]
pub unsafe fn PLLP_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
28usize,
4u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PLLP_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
28usize,
4u8,
val as u64,
)
}
}
#[inline]
pub fn new_bitfield_1(
PLLM: u32,
resvd0: u32,
PLLSRC: u32,
PLLN: u32,
resvd1: u32,
PLLR: u32,
PLLQ: u32,
PLLP: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 5u8, {
let PLLM: u32 = unsafe { ::core::mem::transmute(PLLM) };
PLLM as u64
});
__bindgen_bitfield_unit.set(5usize, 2u8, {
let resvd0: u32 = unsafe { ::core::mem::transmute(resvd0) };
resvd0 as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let PLLSRC: u32 = unsafe { ::core::mem::transmute(PLLSRC) };
PLLSRC as u64
});
__bindgen_bitfield_unit.set(8usize, 9u8, {
let PLLN: u32 = unsafe { ::core::mem::transmute(PLLN) };
PLLN as u64
});
__bindgen_bitfield_unit.set(17usize, 3u8, {
let resvd1: u32 = unsafe { ::core::mem::transmute(resvd1) };
resvd1 as u64
});
__bindgen_bitfield_unit.set(20usize, 4u8, {
let PLLR: u32 = unsafe { ::core::mem::transmute(PLLR) };
PLLR as u64
});
__bindgen_bitfield_unit.set(24usize, 4u8, {
let PLLQ: u32 = unsafe { ::core::mem::transmute(PLLQ) };
PLLQ as u64
});
__bindgen_bitfield_unit.set(28usize, 4u8, {
let PLLP: u32 = unsafe { ::core::mem::transmute(PLLP) };
PLLP as u64
});
__bindgen_bitfield_unit
}
}
#[doc = " @brief CLK PLLx configuration structure definition\n @note PLLx for UPLL"]
#[repr(C)]
#[derive(Copy, Clone)]
pub struct stc_clock_pllx_init_t {
#[doc = "< PLLx new state, @ref CLK_PLLx_State for details"]
pub u8PLLState: u8,
pub __bindgen_anon_1: stc_clock_pllx_init_t__bindgen_ty_1,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union stc_clock_pllx_init_t__bindgen_ty_1 {
#[doc = "< PLLx config register"]
pub PLLCFGR: u32,
pub PLLCFGR_f: stc_clock_pllx_init_t__bindgen_ty_1__bindgen_ty_1,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_clock_pllx_init_t__bindgen_ty_1__bindgen_ty_1 {
pub _bitfield_align_1: [u16; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl stc_clock_pllx_init_t__bindgen_ty_1__bindgen_ty_1 {
#[inline]
pub fn PLLM(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 5u8) as u32) }
}
#[inline]
pub fn set_PLLM(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 5u8, val as u64)
}
}
#[inline]
pub unsafe fn PLLM_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
0usize,
5u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PLLM_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
0usize,
5u8,
val as u64,
)
}
}
#[inline]
pub fn resvd0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 3u8) as u32) }
}
#[inline]
pub fn set_resvd0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 3u8, val as u64)
}
}
#[inline]
pub unsafe fn resvd0_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
5usize,
3u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_resvd0_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
5usize,
3u8,
val as u64,
)
}
}
#[inline]
pub fn PLLN(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 9u8) as u32) }
}
#[inline]
pub fn set_PLLN(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 9u8, val as u64)
}
}
#[inline]
pub unsafe fn PLLN_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
8usize,
9u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PLLN_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
8usize,
9u8,
val as u64,
)
}
}
#[inline]
pub fn resvd1(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 3u8) as u32) }
}
#[inline]
pub fn set_resvd1(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 3u8, val as u64)
}
}
#[inline]
pub unsafe fn resvd1_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
17usize,
3u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_resvd1_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
17usize,
3u8,
val as u64,
)
}
}
#[inline]
pub fn PLLR(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 4u8) as u32) }
}
#[inline]
pub fn set_PLLR(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 4u8, val as u64)
}
}
#[inline]
pub unsafe fn PLLR_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
20usize,
4u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PLLR_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
20usize,
4u8,
val as u64,
)
}
}
#[inline]
pub fn PLLQ(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 4u8) as u32) }
}
#[inline]
pub fn set_PLLQ(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 4u8, val as u64)
}
}
#[inline]
pub unsafe fn PLLQ_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
24usize,
4u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PLLQ_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
24usize,
4u8,
val as u64,
)
}
}
#[inline]
pub fn PLLP(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 4u8) as u32) }
}
#[inline]
pub fn set_PLLP(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 4u8, val as u64)
}
}
#[inline]
pub unsafe fn PLLP_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
28usize,
4u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_PLLP_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
28usize,
4u8,
val as u64,
)
}
}
#[inline]
pub fn new_bitfield_1(
PLLM: u32,
resvd0: u32,
PLLN: u32,
resvd1: u32,
PLLR: u32,
PLLQ: u32,
PLLP: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 5u8, {
let PLLM: u32 = unsafe { ::core::mem::transmute(PLLM) };
PLLM as u64
});
__bindgen_bitfield_unit.set(5usize, 3u8, {
let resvd0: u32 = unsafe { ::core::mem::transmute(resvd0) };
resvd0 as u64
});
__bindgen_bitfield_unit.set(8usize, 9u8, {
let PLLN: u32 = unsafe { ::core::mem::transmute(PLLN) };
PLLN as u64
});
__bindgen_bitfield_unit.set(17usize, 3u8, {
let resvd1: u32 = unsafe { ::core::mem::transmute(resvd1) };
resvd1 as u64
});
__bindgen_bitfield_unit.set(20usize, 4u8, {
let PLLR: u32 = unsafe { ::core::mem::transmute(PLLR) };
PLLR as u64
});
__bindgen_bitfield_unit.set(24usize, 4u8, {
let PLLQ: u32 = unsafe { ::core::mem::transmute(PLLQ) };
PLLQ as u64
});
__bindgen_bitfield_unit.set(28usize, 4u8, {
let PLLP: u32 = unsafe { ::core::mem::transmute(PLLP) };
PLLP as u64
});
__bindgen_bitfield_unit
}
}
#[doc = " @brief CLK bus frequency structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_clock_freq_t {
#[doc = "< System clock frequency."]
pub u32SysclkFreq: u32,
#[doc = "< Hclk frequency."]
pub u32HclkFreq: u32,
#[doc = "< Pclk0 frequency."]
pub u32Pclk0Freq: u32,
#[doc = "< Pclk1 frequency."]
pub u32Pclk1Freq: u32,
#[doc = "< Pclk2 frequency."]
pub u32Pclk2Freq: u32,
#[doc = "< Pclk3 frequency."]
pub u32Pclk3Freq: u32,
#[doc = "< Pclk4 frequency."]
pub u32Pclk4Freq: u32,
#[doc = "< Exclk frequency."]
pub u32ExclkFreq: u32,
}
#[doc = " @brief CLK PLL clock frequency structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pll_clock_freq_t {
#[doc = "< PLL vcin clock frequency."]
pub u32PllVcin: u32,
#[doc = "< PLL vco clock frequency."]
pub u32PllVco: u32,
#[doc = "< PLLp clock frequency."]
pub u32PllP: u32,
#[doc = "< PLLq clock frequency."]
pub u32PllQ: u32,
#[doc = "< PLLr clock frequency."]
pub u32PllR: u32,
#[doc = "< pllx vcin clock frequency."]
pub u32PllxVcin: u32,
#[doc = "< pllx vco clock frequency."]
pub u32PllxVco: u32,
#[doc = "< pllxp clock frequency."]
pub u32PllxP: u32,
#[doc = "< pllxq clock frequency."]
pub u32PllxQ: u32,
#[doc = "< pllxr clock frequency."]
pub u32PllxR: u32,
}
#[doc = " @brief CMP normal mode configuration structure"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_cmp_init_t {
#[doc = "< Positive(compare voltage) input @ref CMP_Positive_Input_Select"]
pub u16PositiveInput: u16,
#[doc = "< Negative(Reference voltage) input @ref CMP_Negative_Input_Select"]
pub u16NegativeInput: u16,
#[doc = "< Output polarity select, @ref CMP_Out_Polarity_Select"]
pub u16OutPolarity: u16,
#[doc = "< Output detect edge, @ref CMP_Out_Detect_Edge_Select"]
pub u16OutDetectEdge: u16,
#[doc = "< Output Filter, @ref CMP_Out_Filter"]
pub u16OutFilter: u16,
}
#[doc = " @brief CRC initialization structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_crc_init_t {
#[doc = "< Specifies CRC Protocol.\nThis parameter can be a value of @ref CRC_Protocol_Control_Bit"]
pub u32Protocol: u32,
#[doc = "< Specifies initial CRC value.\nThis parameter can be CRC_INIT_VALUE_DEFAULT @ref CRC_Init_Value_Default"]
pub u32InitValue: u32,
#[doc = "< Specifies CRC Retroflexion Input.\nThis parameter can be a value of @ref CRC_Retroflexion_Input"]
pub u32RefIn: u32,
#[doc = "< Specifies CRC Retroflexion Output.\nThis parameter can be a value of @ref CRC_Retroflexion_Output"]
pub u32RefOut: u32,
#[doc = "< Specifies CRC XOR Output.\nThis parameter can be a value of @ref CRC_XOR_Output"]
pub u32XorOut: u32,
}
#[doc = " @brief DCU initialization structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dcu_init_t {
#[doc = "< Specifies DCU operation.\nThis parameter can be a value of @ref DCU_Mode"]
pub u32Mode: u32,
#[doc = "< Specifies DCU data width.\nThis parameter can be a value of @ref DCU_Data_Width"]
pub u32DataWidth: u32,
}
#[doc = " @brief DMA basic configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_init_t {
#[doc = "< Specifies the DMA interrupt function.\nThis parameter can be a value of @ref DMA_Int_Config"]
pub u32IntEn: u32,
#[doc = "< Specifies the DMA source address."]
pub u32SrcAddr: u32,
#[doc = "< Specifies the DMA destination address."]
pub u32DestAddr: u32,
#[doc = "< Specifies the DMA transfer data width.\nThis parameter can be a value of @ref DMA_DataWidth_Sel"]
pub u32DataWidth: u32,
#[doc = "< Specifies the DMA block size."]
pub u32BlockSize: u32,
#[doc = "< Specifies the DMA transfer count."]
pub u32TransCount: u32,
#[doc = "< Specifies the source address increment mode.\nThis parameter can be a value of @ref DMA_SrcAddr_Incremented_Mode"]
pub u32SrcAddrInc: u32,
#[doc = "< Specifies the destination address increment mode.\nThis parameter can be a value of @ref DMA_DesAddr_Incremented_Mode"]
pub u32DestAddrInc: u32,
}
#[doc = " @brief DMA repeat mode configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_repeat_init_t {
#[doc = "< Specifies the DMA source repeat function.\nThis parameter can be a value of @ref DMA_Repeat_Config"]
pub u32Mode: u32,
#[doc = "< Specifies the DMA source repeat size."]
pub u32SrcCount: u32,
#[doc = "< Specifies the DMA destination repeat size."]
pub u32DestCount: u32,
}
#[doc = " @brief DMA non-sequence mode configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_nonseq_init_t {
#[doc = "< Specifies the DMA source non-sequence function.\nThis parameter can be a value of @ref DMA_NonSeq_Config"]
pub u32Mode: u32,
#[doc = "< Specifies the DMA source non-sequence function count."]
pub u32SrcCount: u32,
#[doc = "< Specifies the DMA source non-sequence function offset."]
pub u32SrcOffset: u32,
#[doc = "< Specifies the DMA destination non-sequence function count."]
pub u32DestCount: u32,
#[doc = "< Specifies the DMA destination non-sequence function offset."]
pub u32DestOffset: u32,
}
#[doc = " @brief DMA Link List Pointer (LLP) mode configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_llp_init_t {
#[doc = "< Specifies the DMA LLP function.\nThis parameter can be a value of @ref DMA_Llp_En"]
pub u32State: u32,
#[doc = "< Specifies the DMA LLP auto or wait REQ.\nThis parameter can be a value of @ref DMA_Llp_Mode"]
pub u32Mode: u32,
#[doc = "< Specifies the DMA list pointer address for LLP function."]
pub u32Addr: u32,
}
#[doc = " @brief DMA re-config function configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_reconfig_init_t {
#[doc = "< Specifies the DMA reconfig function count mode.\nThis parameter can be a value of @ref DMA_Reconfig_Count_Sel"]
pub u32CountMode: u32,
#[doc = "< Specifies the DMA reconfig function destination address mode.\nThis parameter can be a value of @ref DMA_Reconfig_DestAddr_Sel"]
pub u32DestAddrMode: u32,
#[doc = "< Specifies the DMA reconfig function source address mode.\nThis parameter can be a value of @ref DMA_Reconfig_SrcAddr_Sel"]
pub u32SrcAddrMode: u32,
}
#[doc = " @brief DMA re-config non-sequence mode configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_rc_nonseq_init_t {
#[doc = "< Specifies the DMA source non-sequence function.\nThis parameter can be a value of @ref DMA_NonSeq_Config"]
pub u32Mode: u32,
#[doc = "< Specifies the DMA source non-sequence function count."]
pub u32SrcCount: u32,
#[doc = "< Specifies the DMA source non-sequence function distance."]
pub u32SrcDist: u32,
#[doc = "< Specifies the DMA destination non-sequence function count."]
pub u32DestCount: u32,
#[doc = "< Specifies the DMA destination non-sequence function distance."]
pub u32DestDist: u32,
}
#[doc = " @brief Dma LLP(linked list pointer) descriptor structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_dma_llp_descriptor_t {
#[doc = "< LLP source address"]
pub SARx: u32,
#[doc = "< LLP destination address"]
pub DARx: u32,
#[doc = "< LLP transfer count and block size"]
pub DTCTLx: u32,
#[doc = "< LLP source & destination repeat size"]
pub RPTx: u32,
#[doc = "< LLP source non-seq count and offset"]
pub SNSEQCTLx: u32,
#[doc = "< LLP destination non-seq count and offset"]
pub DNSEQCTLx: u32,
#[doc = "< LLP next list pointer"]
pub LLPx: u32,
#[doc = "< LLP channel control"]
pub CHCTLx: u32,
}
#[doc = " Global type definitions ('typedef')\n/\n/**\n @defgroup EFM_Global_Types EFM Global Types\n @{\n/\n/**\n @brief EFM unique ID definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_unique_id_t {
#[doc = "< unique ID 0."]
pub u32UniqueID0: u32,
#[doc = "< unique ID 1."]
pub u32UniqueID1: u32,
#[doc = "< unique ID 2."]
pub u32UniqueID2: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_efm_remap_init_t {
pub u32State: u32,
pub u32Addr: u32,
pub u32Size: u32,
}
#[doc = " @brief EMB monitor OSC failure configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_monitor_osc_t {
#[doc = "< Enable or disable EMB detect OSC failure function\nThis parameter can be a value of @ref EMB_OSC_Selection"]
pub u32OscState: u32,
}
#[doc = " @brief EMB monitor EMB port configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_monitor_port_config_t {
#[doc = "< Enable or disable EMB detect port in control function\nThis parameter can be a value of @ref EMB_Port_Selection"]
pub u32PortState: u32,
#[doc = "< EMB detect port level\nThis parameter can be a value of @ref EMB_Detect_Port_Level"]
pub u32PortLevel: u32,
#[doc = "< EMB port filter division\nThis parameter can be a value of @ref EMB_Port_Filter_Clock_Division"]
pub u32PortFilterDiv: u32,
#[doc = "< Enable or disable EMB detect port filter in control function\nThis parameter can be a value of @ref EMB_Port_Filter_Selection"]
pub u32PortFilterState: u32,
}
#[doc = " @brief EMB monitor PWM configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_monitor_tmr_pwm_t {
#[doc = "< Enable or disable EMB detect timer same phase function\nThis parameter can be a value of @ref EMB_Detect_PWM state."]
pub u32PwmState: u32,
#[doc = "< Detect timer polarity level\nThis parameter can be a value of @ref EMB_Detect_PWM level"]
pub u32PwmLevel: u32,
}
#[doc = " @brief EMB monitor port in configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_monitor_port_t {
#[doc = "< EMB detect EMB port in function\nThis parameter details refer @ref stc_emb_monitor_port_config_t structure"]
pub stcPort1: stc_emb_monitor_port_config_t,
}
#[doc = " @brief EMB monitor CMP configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_monitor_cmp_t {
#[doc = "< Enable or disable EMB detect CMP1 result function\nThis parameter can be a value of @ref EMB_CMP_Selection"]
pub u32Cmp1State: u32,
#[doc = "< Enable or disable EMB detect CMP2 result function\nThis parameter can be a value of @ref EMB_CMP_Selection"]
pub u32Cmp2State: u32,
#[doc = "< Enable or disable EMB detect CMP3 result function\nThis parameter can be a value of @ref EMB_CMP_Selection"]
pub u32Cmp3State: u32,
}
#[doc = " @brief EMB monitor TMR4 configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_monitor_tmr4_t {
#[doc = "< EMB detect TMR4 function\nThis parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure"]
pub stcTmr4PwmU: stc_emb_monitor_tmr_pwm_t,
#[doc = "< EMB detect TMR4 function\nThis parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure"]
pub stcTmr4PwmV: stc_emb_monitor_tmr_pwm_t,
#[doc = "< EMB detect TMR4 function\nThis parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure"]
pub stcTmr4PwmW: stc_emb_monitor_tmr_pwm_t,
}
#[doc = " @brief EMB control TMR4 initialization configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_tmr4_init_t {
#[doc = "< EMB detect CMP function\nThis parameter details refer @ref stc_emb_monitor_cmp_t structure"]
pub stcCmp: stc_emb_monitor_cmp_t,
#[doc = "< EMB detect OSC function\nThis parameter details refer @ref stc_emb_monitor_osc_t structure"]
pub stcOsc: stc_emb_monitor_osc_t,
#[doc = "< EMB detect EMB port function\nThis parameter details refer @ref stc_emb_monitor_port_t structure"]
pub stcPort: stc_emb_monitor_port_t,
#[doc = "< EMB detect TMR4 function\nThis parameter details refer @ref stc_emb_monitor_tmr4_t structure"]
pub stcTmr4: stc_emb_monitor_tmr4_t,
}
#[doc = " @brief EMB monitor TMR6 configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_monitor_tmr6_t {
#[doc = "< EMB detect TMR6 function\nThis parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure"]
pub stcTmr6_1: stc_emb_monitor_tmr_pwm_t,
#[doc = "< EMB detect TMR6 function\nThis parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure"]
pub stcTmr6_2: stc_emb_monitor_tmr_pwm_t,
#[doc = "< EMB detect TMR6 function\nThis parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure"]
pub stcTmr6_3: stc_emb_monitor_tmr_pwm_t,
}
#[doc = " @brief EMB control TMR6 initialization configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_emb_tmr6_init_t {
#[doc = "< EMB detect CMP function\nThis parameter details refer @ref stc_emb_monitor_cmp_t structure"]
pub stcCmp: stc_emb_monitor_cmp_t,
#[doc = "< EMB detect OSC function\nThis parameter details refer @ref stc_emb_monitor_osc_t structure"]
pub stcOsc: stc_emb_monitor_osc_t,
#[doc = "< EMB detect EMB port function\nThis parameter details refer @ref stc_emb_monitor_port_t structure"]
pub stcPort: stc_emb_monitor_port_t,
#[doc = "< EMB detect TMR6 function\nThis parameter details refer @ref stc_emb_monitor_tmr6_t structure"]
pub stcTmr6: stc_emb_monitor_tmr6_t,
}
#[doc = "< Pin reset"]
pub const en_ep_state_t_EVT_PIN_RESET: en_ep_state_t = 0;
#[doc = "< Pin set"]
pub const en_ep_state_t_EVT_PIN_SET: en_ep_state_t = 1;
#[doc = " @brief Event Pin Set and Reset enumeration"]
pub type en_ep_state_t = ::core::ffi::c_uint;
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_ep_init_t {
#[doc = "< Input/Output setting, @ref EP_PinDirection_Sel for details"]
pub u32PinDir: u32,
#[doc = "< Corresponding pin initial state, @ref en_ep_state_t for details"]
pub enPinState: en_ep_state_t,
#[doc = "< Corresponding pin state after triggered, @ref EP_TriggerOps_Sel for details"]
pub u32PinTriggerOps: u32,
#[doc = "< Event port trigger edge, @ref EP_Trigger_Sel for details"]
pub u32Edge: u32,
#[doc = "< Filter clock function setting, @ref EP_FilterClock_Sel for details"]
pub u32Filter: u32,
#[doc = "< Filter clock, ref@ EP_FilterClock_Div for details"]
pub u32FilterClock: u32,
}
#[doc = " Global type definitions ('typedef')\n/\n/**\n @defgroup FCM_Global_Types FCM Global Types\n @{\n/\n/**\n @brief FCM Init structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_fcm_init_t {
#[doc = "< FCM lower limit value"]
pub u16LowerLimit: u16,
#[doc = "< FCM upper limit value"]
pub u16UpperLimit: u16,
#[doc = "< FCM target clock source selection, @ref FCM_Target_Clock_Src"]
pub u32TargetClock: u32,
#[doc = "< FCM target clock source division selection, @ref FCM_Target_Clock_Div"]
pub u32TargetClockDiv: u32,
#[doc = "< FCM external reference clock function config, @ref FCM_Ext_Ref_Clock_Config"]
pub u32ExtRefClockEnable: u32,
#[doc = "< FCM reference clock trigger edge selection, @ref FCM_Ref_Clock_Edge"]
pub u32RefClockEdge: u32,
#[doc = "< FCM digital filter function config, @ref FCM_Digital_Filter_Config"]
pub u32DigitalFilter: u32,
#[doc = "< FCM reference clock source selection, @ref FCM_Ref_Clock_Src"]
pub u32RefClock: u32,
#[doc = "< FCM reference clock source division selection, @ref FCM_Ref_Clock_Div"]
pub u32RefClockDiv: u32,
#[doc = "< FCM exception type select, @ref FCM_Exception_Type"]
pub u32ExceptionType: u32,
}
#[doc = "< Pin reset"]
pub const en_pin_state_t_PIN_RESET: en_pin_state_t = 0;
#[doc = "< Pin set"]
pub const en_pin_state_t_PIN_SET: en_pin_state_t = 1;
#[doc = " @brief GPIO Pin Set and Reset enumeration"]
pub type en_pin_state_t = ::core::ffi::c_uint;
#[doc = " @brief GPIO Init structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_gpio_init_t {
#[doc = "< Set pin state to High or Low, @ref GPIO_PinState_Sel for details"]
pub u16PinState: u16,
#[doc = "< Pin mode setting, @ref GPIO_PinDirection_Sel for details"]
pub u16PinDir: u16,
#[doc = "< Output type setting, @ref GPIO_PinOutType_Sel for details"]
pub u16PinOutputType: u16,
#[doc = "< Pin drive capacity setting, @ref GPIO_PinDrv_Sel for details"]
pub u16PinDrv: u16,
#[doc = "< Pin latch setting, @ref GPIO_PinLatch_Sel for details"]
pub u16Latch: u16,
#[doc = "< Internal pull-up resistor setting, @ref GPIO_PinPU_Sel for details"]
pub u16PullUp: u16,
#[doc = "< Pin input/output invert setting, @ref GPIO_PinInvert_Sel for details"]
pub u16Invert: u16,
#[doc = "< External interrupt pin setting, @ref GPIO_PinExtInt_Sel for details"]
pub u16ExtInt: u16,
#[doc = "< Digital or analog attribute setting, @ref GPIO_PinMode_Sel for details"]
pub u16PinAttr: u16,
}
#[doc = " @brief I2c configuration structure"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2c_init_t {
#[doc = "< I2C clock division for i2c source clock"]
pub u32ClockDiv: u32,
#[doc = "< I2C baudrate config"]
pub u32Baudrate: u32,
#[doc = "< The SCL rising and falling time, count of T(i2c source clock after frequency divider)"]
pub u32SclTime: u32,
}
#[doc = " @brief I2S Init structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_i2s_init_t {
#[doc = "< Specifies the clock source of I2S.\nThis parameter can be a value of @ref I2S_Clock_Source"]
pub u32ClockSrc: u32,
#[doc = "< Specifies the master/slave mode of I2S.\nThis parameter can be a value of @ref I2S_Mode"]
pub u32Mode: u32,
#[doc = "< Specifies the communication protocol of I2S.\nThis parameter can be a value of @ref I2S_Protocol"]
pub u32Protocol: u32,
#[doc = "< Specifies the transmission mode for the I2S communication.\nThis parameter can be a value of @ref I2S_Trans_Mode"]
pub u32TransMode: u32,
#[doc = "< Specifies the frequency selected for the I2S communication.\nThis parameter can be a value of @ref I2S_Audio_Frequency"]
pub u32AudioFreq: u32,
#[doc = "< Specifies the channel length for the I2S communication.\nThis parameter can be a value of @ref I2S_Channel_Length"]
pub u32ChWidth: u32,
#[doc = "< Specifies the data length for the I2S communication.\nThis parameter can be a value of @ref I2S_Data_Length"]
pub u32DataWidth: u32,
#[doc = "< Specifies the validity of the MCK output for I2S.\nThis parameter can be a value of @ref I2S_MCK_Output"]
pub u32MCKOutput: u32,
#[doc = "< Specifies the level of transfer FIFO.\nThis parameter can be a value of @ref I2S_Trans_Level"]
pub u32TransFIFOLevel: u32,
#[doc = "< Specifies the level of receive FIFO.\nThis parameter can be a value of @ref I2S_Receive_Level"]
pub u32ReceiveFIFOLevel: u32,
}
#[doc = " @brief Interrupt registration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_irq_signin_config_t {
#[doc = "< Peripheral interrupt number, can be any value @ref en_int_src_t"]
pub enIntSrc: en_int_src_t,
#[doc = "< Peripheral IRQ type, can be INT000_IRQn~INT127_IRQn @ref IRQn_Type"]
pub enIRQn: IRQn_Type,
#[doc = "< Callback function for corresponding peripheral IRQ"]
pub pfnCallback: func_ptr_t,
}
#[doc = " @brief NMI initialize configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_nmi_init_t {
#[doc = "< NMI trigger source, @ref NMI_TriggerSrc_Sel for details"]
pub u32Src: u32,
#[doc = "< NMI pin trigger edge, @ref NMI_Trigger_level_Sel for details"]
pub u32Edge: u32,
#[doc = "< NMI filter function setting, @ref NMI_FilterClock_Sel for details"]
pub u32Filter: u32,
#[doc = "< NMI filter clock division, @ref NMI_FilterClock_Div for details"]
pub u32FilterClock: u32,
}
#[doc = " @brief EXTINT initialize configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_extint_init_t {
#[doc = "< ExtInt filter (A) function setting, @ref EXTINT_FilterClock_Sel for details"]
pub u32Filter: u32,
#[doc = "< ExtInt filter (A) clock division, @ref EXTINT_FilterClock_Div for details"]
pub u32FilterClock: u32,
#[doc = "< ExtInt trigger edge, @ref EXTINT_Trigger_Sel for details"]
pub u32Edge: u32,
}
#[doc = " @brief KEYSCAN configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_keyscan_init_t {
#[doc = "< Specifies the KEYSCAN Hiz cycles.\nThis parameter can be a value of @ref KEYSCAN_Hiz_Cycle_Sel"]
pub u32HizCycle: u32,
#[doc = "< Specifies the KEYSCAN low cycles.\nThis parameter can be a value of @ref KEYSCAN_Low_Cycle_Sel"]
pub u32LowCycle: u32,
#[doc = "< Specifies the KEYSCAN low cycles.\nThis parameter can be a value of @ref KEYSCAN_Clock_Sel"]
pub u32KeyClock: u32,
#[doc = "< Specifies the KEYSCAN low cycles.\nThis parameter can be a value of @ref KEYSCAN_Keyout_Sel"]
pub u32KeyOut: u32,
#[doc = "< Specifies the KEYSCAN low cycles.\nThis parameter can be a value of @ref KEYSCAN_Keyin_Sel"]
pub u32KeyIn: u32,
}
#[doc = " @brief MPU Unit configure structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_unit_config_t {
#[doc = "< Specifies the type of exception that occurs when the unit accesses a protected region.\nThis parameter can be a value of @ref MPU_Exception_Type"]
pub u32ExceptionType: u32,
#[doc = "< Specifies the unit's write permission for the background space.\nThis parameter can be a value of @ref MPU_Background_Write_Permission"]
pub u32BackgroundWrite: u32,
#[doc = "< Specifies the unit's read permission for the background space\nThis parameter can be a value of @ref MPU_Background_Read_Permission"]
pub u32BackgroundRead: u32,
}
#[doc = " @brief MPU Unit initialize structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_unit_init_t {
#[doc = "< Specifies the unit's state of mpu\nThis parameter can be a value of @ref MPU_Unit_State"]
pub u32MpuState: u32,
#[doc = "< Specifies the type of exception that occurs when the unit accesses a protected region.\nThis parameter can be a value of @ref MPU_Exception_Type"]
pub u32ExceptionType: u32,
#[doc = "< Specifies the unit's write permission for the background space.\nThis parameter can be a value of @ref MPU_Background_Write_Permission"]
pub u32BackgroundWrite: u32,
#[doc = "< Specifies the unit's read permission for the background space\nThis parameter can be a value of @ref MPU_Background_Read_Permission"]
pub u32BackgroundRead: u32,
}
#[doc = " @brief MPU Init structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_init_t {
#[doc = "< Configure storage protection unit of DMA1"]
pub stcDma1: stc_mpu_unit_config_t,
#[doc = "< Configure storage protection unit of DMA2"]
pub stcDma2: stc_mpu_unit_config_t,
#[doc = "< Configure storage protection unit of USBFS_DMA"]
pub stcUsbFSDma: stc_mpu_unit_config_t,
}
#[doc = " @brief MPU Region Permission structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_region_permission_t {
#[doc = "< Specifies the unit's write permission for the region.\nThis parameter can be a value of @ref MPU_Region_Write_Permission"]
pub u32RegionWrite: u32,
#[doc = "< Specifies the unit's read permission for the region.\nThis parameter can be a value of @ref MPU_Region_Read_Permission"]
pub u32RegionRead: u32,
}
#[doc = " @brief MPU region initialization structure definition\n @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region,\n and the low 'u32Size+1' bits are fixed at 0."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_mpu_region_init_t {
#[doc = "< Specifies the base address of the region.\nThis parameter can be a number between 0UL and 0xFFFFFFE0UL"]
pub u32BaseAddr: u32,
#[doc = "< Specifies the size of the region.\nThis parameter can be a value of @ref MPU_Region_Size"]
pub u32Size: u32,
#[doc = "< Specifies the DMA1 access permission for the region"]
pub stcDma1: stc_mpu_region_permission_t,
#[doc = "< Specifies the DMA2 access permission for the region"]
pub stcDma2: stc_mpu_region_permission_t,
#[doc = "< Specifies the USBFS_DMA access permission for the region"]
pub stcUsbFSDma: stc_mpu_region_permission_t,
}
#[doc = " @brief OTS initialization structure."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_ots_init_t {
#[doc = "< Specifies clock source for OTS.\nThis parameter can be a value of @ref OTS_Clock_Source"]
pub u16ClockSrc: u16,
#[doc = "< Enable or disable OTS automatic-off(after sampled temperature).\nThis parameter can be a value of @ref OTS_Auto_Off_En"]
pub u16AutoOffEn: u16,
#[doc = "< K: Temperature slope (calculated by calibration experiment).\nIf you want to use the default parameters(slope K and offset M),\nspecify both 'f32SlopeK' and 'f32OffsetM' as ZERO."]
pub f32SlopeK: float32_t,
#[doc = "< M: Temperature offset (calculated by calibration experiment).\nIf you want to use the default parameters(slope K and offset M),\nspecify both 'f32SlopeK' and 'f32OffsetM' as ZERO."]
pub f32OffsetM: float32_t,
}
#[doc = " Global type definitions ('typedef')\n/\n/**\n @defgroup PWC_Global_Types PWC Global Types\n @{\n/\n/**\n @brief PWC LVD Init"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_lvd_init_t {
#[doc = "< LVD function setting, @ref PWC_LVD_Config for details"]
pub u32State: u32,
#[doc = "< LVD compare output function setting, @ref PWC_LVD_CMP_Config for details"]
pub u32CompareOutputState: u32,
#[doc = "< LVD interrupt or reset selection, @ref PWC_LVD_Exception_Type_Sel for details"]
pub u32ExceptionType: u32,
#[doc = "< LVD digital filter function setting, @ref PWC_LVD_DF_Config for details"]
pub u32Filter: u32,
#[doc = "< LVD digital filter clock setting, @ref PWC_LVD_DFS_Clk_Sel for details"]
pub u32FilterClock: u32,
#[doc = "< LVD detect voltage setting, @ref PWC_LVD_Detection_Voltage_Sel for details"]
pub u32ThresholdVoltage: u32,
}
#[doc = " @brief PWC power down mode innit"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_pd_mode_config_t {
#[doc = "< Power down mode, @ref PWC_PDMode_Sel for details."]
pub u8Mode: u8,
#[doc = "< IO state in power down mode, @ref PWC_PDMode_IO_Sel for details."]
pub u8IOState: u8,
#[doc = "< Power down Wakeup time control, @ref PWC_PD_VCAP_Sel for details."]
pub u8VcapCtrl: u8,
}
#[doc = " @brief PWC Stop mode Init"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_pwc_stop_mode_config_t {
#[doc = "< System clock setting after wake-up from stop mode,\n@ref PWC_STOP_CLK_Sel for details."]
pub u16Clock: u16,
#[doc = "< Stop mode drive capacity,\n@ref PWC_STOP_DRV_Sel for details."]
pub u8StopDrv: u8,
#[doc = "< Waiting flash stable after wake-up from stop mode,\n@ref PWC_STOP_Flash_Wait_Sel for details."]
pub u16FlashWait: u16,
}
#[doc = " @brief QSPI initialization structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_qspi_init_t {
#[doc = "< Specifies the clock division.\nThis parameter can be a value of @ref QSPI_Clock_Division"]
pub u32ClockDiv: u32,
#[doc = "< Specifies the SPI mode.\nThis parameter can be a value of @ref QSPI_SPI_Mode"]
pub u32SpiMode: u32,
#[doc = "< Specifies the prefetch mode.\nThis parameter can be a value of @ref QSPI_Prefetch_Mode"]
pub u32PrefetchMode: u32,
#[doc = "< Specifies the read mode.\nThis parameter can be a value of @ref QSPI_Read_Mode"]
pub u32ReadMode: u32,
#[doc = "< Specifies the number of dummy cycles.\nThis parameter can be a value of @ref QSPI_Dummy_Cycle"]
pub u32DummyCycle: u32,
#[doc = "< Specifies the address width.\nThis parameter can be a value of @ref QSPI_Addr_Width"]
pub u32AddrWidth: u32,
#[doc = "< Specifies the advance time of QSSN setup.\nThis parameter can be a value of @ref QSPI_QSSN_Setup_Time"]
pub u32SetupTime: u32,
#[doc = "< Specifies the delay time of QSSN release.\nThis parameter can be a value of @ref QSPI_QSSN_Release_Time"]
pub u32ReleaseTime: u32,
#[doc = "< Specifies the minimum interval time of QSSN.\nThis parameter can be a value of @ref QSPI_QSSN_Interval_Time"]
pub u32IntervalTime: u32,
}
#[doc = " @brief QSPI Custom read mode structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_qspi_custom_mode_t {
#[doc = "< Specifies the instruction stage protocol.\nThis parameter can be a value of @ref QSPI_Instruction_Protocol"]
pub u32InstrProtocol: u32,
#[doc = "< Specifies the address stage protocol.\nThis parameter can be a value of @ref QSPI_Addr_Protocol"]
pub u32AddrProtocol: u32,
#[doc = "< Specifies the data stage protocol.\nThis parameter can be a value of @ref QSPI_Data_Protocol"]
pub u32DataProtocol: u32,
#[doc = "< Specifies the instruction code in custom read mode.\nThis parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF"]
pub u8InstrCode: u8,
}
#[doc = " @brief RTC Init structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rtc_init_t {
#[doc = "< Specifies the RTC clock source.\nThis parameter can be a value of @ref RTC_Clock_Source"]
pub u8ClockSrc: u8,
#[doc = "< Specifies the RTC hour format.\nThis parameter can be a value of @ref RTC_Hour_Format"]
pub u8HourFormat: u8,
#[doc = "< Specifies the RTC interrupt period.\nThis parameter can be a value of @ref RTC_Interrupt_Period"]
pub u8IntPeriod: u8,
#[doc = "< Specifies the validity of RTC clock compensation.\nThis parameter can be a value of @ref RTC_Clock_Compensation"]
pub u8ClockCompen: u8,
#[doc = "< Specifies the mode of RTC clock compensation.\nThis parameter can be a value of @ref RTC_Clock_Compensation_Mode"]
pub u8CompenMode: u8,
#[doc = "< Specifies the value of RTC clock compensation.\nThis parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF"]
pub u16CompenValue: u16,
}
#[doc = " @brief RTC Date structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rtc_date_t {
#[doc = "< Specifies the RTC Year.\nThis parameter can be a number between Min_Data = 0 and Max_Data = 99"]
pub u8Year: u8,
#[doc = "< Specifies the RTC Month (in Decimal format).\nThis parameter can be a value of @ref RTC_Month"]
pub u8Month: u8,
#[doc = "< Specifies the RTC Day.\nThis parameter can be a number between Min_Data = 1 and Max_Data = 31"]
pub u8Day: u8,
#[doc = "< Specifies the RTC Weekday.\nThis parameter can be a value of @ref RTC_Weekday"]
pub u8Weekday: u8,
}
#[doc = " @brief RTC Time structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rtc_time_t {
#[doc = "< Specifies the RTC Hour.\nThis parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected.\nThis parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected"]
pub u8Hour: u8,
#[doc = "< Specifies the RTC Minute.\nThis parameter can be a number between Min_Data = 0 and Max_Data = 59"]
pub u8Minute: u8,
#[doc = "< Specifies the RTC Second.\nThis parameter can be a number between Min_Data = 0 and Max_Data = 59"]
pub u8Second: u8,
#[doc = "< Specifies the RTC Am/Pm Time (in RTC_HOUR_FMT_12H mode).\nThis parameter can be a value of @ref RTC_Hour12_AM_PM"]
pub u8AmPm: u8,
}
#[doc = " @brief RTC Alarm structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_rtc_alarm_t {
#[doc = "< Specifies the RTC Alarm Hour.\nThis parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected.\nThis parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected"]
pub u8AlarmHour: u8,
#[doc = "< Specifies the RTC Alarm Minute.\nThis parameter can be a number between Min_Data = 0 and Max_Data = 59"]
pub u8AlarmMinute: u8,
#[doc = "< Specifies the RTC Alarm Weekday.\nThis parameter can be a value of @ref RTC_Alarm_Weekday"]
pub u8AlarmWeekday: u8,
#[doc = "< Specifies the RTC Alarm Am/Pm Time (in RTC_HOUR_FMT_12H mode).\nThis parameter can be a value of @ref RTC_Hour12_AM_PM"]
pub u8AlarmAmPm: u8,
}
#[doc = " @brief SDIOC Init structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_init_t {
#[doc = "< Specifies the SDIOC work mode.\nThis parameter can be a value of @ref SDIOC_Mode"]
pub u32Mode: u32,
#[doc = "< Specifies the SDIOC card detect way.\nThis parameter can be a value of @ref SDIOC_Card_Detect_Way"]
pub u8CardDetect: u8,
#[doc = "< Specifies the SDIOC speed mode.\nThis parameter can be a value of @ref SDIOC_Speed_Mode"]
pub u8SpeedMode: u8,
#[doc = "< Specifies the SDIOC bus width.\nThis parameter can be a value of @ref SDIOC_Bus_Width"]
pub u8BusWidth: u8,
#[doc = "< Specifies the SDIOC clock division.\nThis parameter can be a value of @ref SDIOC_Clock_Division"]
pub u16ClockDiv: u16,
}
#[doc = " @brief SDIOC Command Configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_cmd_config_t {
#[doc = "< Specifies the SDIOC command argument."]
pub u32Argument: u32,
#[doc = "< Specifies the SDIOC command index.\nThis parameter must be a number between Min_Data = 0 and Max_Data = 63"]
pub u16CmdIndex: u16,
#[doc = "< Specifies the SDIOC command type.\nThis parameter can be a value of @ref SDIOC_Command_Type"]
pub u16CmdType: u16,
#[doc = "< Specifies whether SDIOC uses data lines in current command.\nThis parameter can be a value of @ref SDIOC_Data_Line_Valid"]
pub u16DataLine: u16,
#[doc = "< Specifies the SDIOC response type.\nThis parameter can be a value of @ref SDIOC_Response_Type"]
pub u16ResponseType: u16,
}
#[doc = " @brief SDIOC Data Configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdioc_data_config_t {
#[doc = "< Specifies the SDIOC data block size.\nThis parameter must be a number between Min_Data = 1 and Max_Data = 512"]
pub u16BlockSize: u16,
#[doc = "< Specifies the SDIOC data block count.\nThis parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF"]
pub u16BlockCount: u16,
#[doc = "< Specifies the SDIOC data transfer direction.\nThis parameter can be a value of @ref SDIOC_Transfer_Direction"]
pub u16TransDir: u16,
#[doc = "< Specifies the validity of the SDIOC Auto Send CMD12.\nThis parameter can be a value of @ref SDIOC_Auto_Send_CMD12"]
pub u16AutoCmd12: u16,
#[doc = "< Specifies the SDIOC data transfer mode.\nThis parameter can be a value of @ref SDIOC_Transfer_Mode"]
pub u16TransMode: u16,
#[doc = "< Specifies the SDIOC data timeout time.\nThis parameter can be a value of @ref SDIOC_Data_Timeout_Time"]
pub u16DataTimeout: u8,
}
#[doc = " @brief SDIO CMD52 arguments structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdio_cmd52_arg_t {
#[doc = "< Specifies the number of the function within the I/O card.\nThis parameter must be a number between Min_Data = 0 and Max_Data = 7"]
pub u8FuncNum: u8,
#[doc = "< Specifies the direction of the I/O operation.\nThis parameter can be a value of @ref SDIO_CMD52_Arguments_RW_Flag"]
pub u32RwFlag: u32,
#[doc = "< Specifies the address of the byte of data inside of the selected function.\nThis parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFF"]
pub u32RegAddr: u32,
#[doc = "< Specifies the direction of the I/O operation.\nThis parameter can be a value of @ref SDIO_CMD52_Arguments_RAW_Flag"]
pub u32RawFlag: u32,
}
#[doc = " @brief SDIO CMD53 arguments structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_sdio_cmd53_arg_t {
#[doc = "< Specifies the number of the function within the I/O card.\nThis parameter must be a number between Min_Data = 0 and Max_Data = 7"]
pub u8FuncNum: u8,
#[doc = "< Specifies the direction of the I/O operation.\nThis parameter can be a value of @ref SDIO_CMD53_Arguments_RW_Flag"]
pub u32RwFlag: u32,
#[doc = "< Specifies the address of the byte of data inside of the selected function.\nThis parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFF"]
pub u32RegAddr: u32,
#[doc = "< Specifies the operation code.\nThis parameter can be a value of @ref SDIO_CMD53_Arguments_Operate_Code"]
pub u32OperateCode: u32,
#[doc = "< Specifies the operation code.\nThis parameter can be a value of @ref SDIO_CMD53_Arguments_Block_Mode"]
pub u32BlockMode: u32,
#[doc = "< Specifies the byte/block count.\nThis parameter must be a number between Min_Data = 0 and Max_Data = 0x1FF"]
pub u32Count: u32,
}
#[doc = " @brief Structure definition of SPI initialization.\n @note The parameter u32BaudRatePrescaler is invalid while slave mode"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_spi_init_t {
#[doc = "< SPI wire mode, 3 wire mode or 4 wire mode.\nThis parameter can be a value of @ref SPI_Wire_Mode_Define"]
pub u32WireMode: u32,
#[doc = "< SPI transfer mode, send only or full duplex.\nThis parameter can be a value of @ref SPI_Trans_Mode_Define"]
pub u32TransMode: u32,
#[doc = "< SPI master/slave mode.\nThis parameter can be a value of @ref SPI_Master_Slave_Mode_Define"]
pub u32MasterSlave: u32,
#[doc = "< SPI mode fault detect command.\nThis parameter can be a value of @ref SPI_Mode_Fault_Detect_Command_Define"]
pub u32ModeFaultDetect: u32,
#[doc = "< SPI parity check selection.\nThis parameter can be a value of @ref SPI_Parity_Check_Define"]
pub u32Parity: u32,
#[doc = "< SPI mode.\nThis parameter can be a value of @ref SPI_Mode_Define"]
pub u32SpiMode: u32,
#[doc = "< SPI baud rate prescaler.\nThis parameter can be a value of @ref SPI_Baud_Rate_Prescaler_Define"]
pub u32BaudRatePrescaler: u32,
#[doc = "< SPI data bits, 4 bits ~ 32 bits.\nThis parameter can be a value of @ref SPI_Data_Size_Define"]
pub u32DataBits: u32,
#[doc = "< MSB first or LSB first.\nThis parameter can be a value of @ref SPI_First_Bit_Define"]
pub u32FirstBit: u32,
#[doc = "< SPI communication suspend function.\nThis parameter can be a value of @ref SPI_Com_Suspend_Func_Define"]
pub u32SuspendMode: u32,
#[doc = "< SPI frame level, SPI_1_FRAME ~ SPI_4_FRAME.\nThis parameter can be a value of @ref SPI_Frame_Level_Define"]
pub u32FrameLevel: u32,
}
#[doc = " @brief Structure definition of SPI delay time configuration."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_spi_delay_t {
#[doc = "< SPI interval time delay (Next access delay time)\nThis parameter can be a value of @ref SPI_Interval_Delay_Time_define"]
pub u32IntervalDelay: u32,
#[doc = "< SPI release time delay (SCK invalid delay time)\nThis parameter can be a value of @ref SPI_Release_Delay_Time_define"]
pub u32ReleaseDelay: u32,
#[doc = "< SPI Setup time delay (SCK valid delay time) define\nThis parameter can be a value of @ref SPI_Setup_Delay_Time_define"]
pub u32SetupDelay: u32,
}
#[doc = " @brief TMR0 initialization structure definition\n @note The 'u32ClockDiv' is invalid when the value of 'u32ClockSrc' is \"TMR0_CLK_SRC_SPEC_EVT\"."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr0_init_t {
#[doc = "< Specifies the clock source of TMR0 channel.\nThis parameter can be a value of @ref TMR0_Clock_Source"]
pub u32ClockSrc: u32,
#[doc = "< Specifies the clock division of TMR0 channel.\nThis parameter can be a value of @ref TMR0_Clock_Division"]
pub u32ClockDiv: u32,
#[doc = "< Specifies the function of TMR0 channel.\nThis parameter can be a value of @ref TMR0_Function"]
pub u32Func: u32,
#[doc = "< Specifies the compare value of TMR0 channel.\nThis parameter can be a value of half-word"]
pub u16CompareValue: u16,
}
#[doc = " @brief TMR4 Counter function initialization configuration\n @note The TMR4 division(u16ClockDiv) is valid when clock source is the internal clock."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_init_t {
#[doc = "< TMR4 counter clock source.\nThis parameter can be a value of @ref TMR4_Count_Clock_Source"]
pub u16ClockSrc: u16,
#[doc = "< TMR4 counter internal clock division.\nThis parameter can be a value of @ref TMR4_Count_Clock_Division."]
pub u16ClockDiv: u16,
#[doc = "< TMR4 counter mode.\nThis parameter can be a value of @ref TMR4_Count_Mode"]
pub u16CountMode: u16,
#[doc = "< TMR4 counter period value.\nThis parameter can be a value of half-word"]
pub u16PeriodValue: u16,
}
#[doc = " @brief The configuration of Output-Compare high channel(OUH/OVH/OWH)"]
#[repr(C)]
#[derive(Copy, Clone)]
pub union un_tmr4_oc_ocmrh_t {
#[doc = "< OCMRxH(x=U/V/W) register"]
pub OCMRx: u16,
pub OCMRx_f: un_tmr4_oc_ocmrh_t__bindgen_ty_1,
}
#[repr(C)]
#[repr(align(2))]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct un_tmr4_oc_ocmrh_t__bindgen_ty_1 {
pub _bitfield_align_1: [u8; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 2usize]>,
}
impl un_tmr4_oc_ocmrh_t__bindgen_ty_1 {
#[inline]
pub fn OCFDCH(&self) -> u16 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u16) }
}
#[inline]
pub fn set_OCFDCH(&mut self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn OCFDCH_raw(this: *const Self) -> u16 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
0usize,
1u8,
) as u16)
}
}
#[inline]
pub unsafe fn set_OCFDCH_raw(this: *mut Self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
0usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn OCFPKH(&self) -> u16 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u16) }
}
#[inline]
pub fn set_OCFPKH(&mut self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn OCFPKH_raw(this: *const Self) -> u16 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
1usize,
1u8,
) as u16)
}
}
#[inline]
pub unsafe fn set_OCFPKH_raw(this: *mut Self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
1usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn OCFUCH(&self) -> u16 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u16) }
}
#[inline]
pub fn set_OCFUCH(&mut self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn OCFUCH_raw(this: *const Self) -> u16 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
2usize,
1u8,
) as u16)
}
}
#[inline]
pub unsafe fn set_OCFUCH_raw(this: *mut Self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
2usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn OCFZRH(&self) -> u16 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u16) }
}
#[inline]
pub fn set_OCFZRH(&mut self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn OCFZRH_raw(this: *const Self) -> u16 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
3usize,
1u8,
) as u16)
}
}
#[inline]
pub unsafe fn set_OCFZRH_raw(this: *mut Self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
3usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn OPDCH(&self) -> u16 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 2u8) as u16) }
}
#[inline]
pub fn set_OPDCH(&mut self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn OPDCH_raw(this: *const Self) -> u16 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
4usize,
2u8,
) as u16)
}
}
#[inline]
pub unsafe fn set_OPDCH_raw(this: *mut Self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
4usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn OPPKH(&self) -> u16 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 2u8) as u16) }
}
#[inline]
pub fn set_OPPKH(&mut self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn OPPKH_raw(this: *const Self) -> u16 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
6usize,
2u8,
) as u16)
}
}
#[inline]
pub unsafe fn set_OPPKH_raw(this: *mut Self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
6usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn OPUCH(&self) -> u16 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 2u8) as u16) }
}
#[inline]
pub fn set_OPUCH(&mut self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn OPUCH_raw(this: *const Self) -> u16 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
8usize,
2u8,
) as u16)
}
}
#[inline]
pub unsafe fn set_OPUCH_raw(this: *mut Self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
8usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn OPZRH(&self) -> u16 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 2u8) as u16) }
}
#[inline]
pub fn set_OPZRH(&mut self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn OPZRH_raw(this: *const Self) -> u16 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
10usize,
2u8,
) as u16)
}
}
#[inline]
pub unsafe fn set_OPZRH_raw(this: *mut Self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
10usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn OPNPKH(&self) -> u16 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 2u8) as u16) }
}
#[inline]
pub fn set_OPNPKH(&mut self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn OPNPKH_raw(this: *const Self) -> u16 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
12usize,
2u8,
) as u16)
}
}
#[inline]
pub unsafe fn set_OPNPKH_raw(this: *mut Self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
12usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn OPNZRH(&self) -> u16 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 2u8) as u16) }
}
#[inline]
pub fn set_OPNZRH(&mut self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn OPNZRH_raw(this: *const Self) -> u16 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
14usize,
2u8,
) as u16)
}
}
#[inline]
pub unsafe fn set_OPNZRH_raw(this: *mut Self, val: u16) {
unsafe {
let val: u16 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 2usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
14usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn new_bitfield_1(
OCFDCH: u16,
OCFPKH: u16,
OCFUCH: u16,
OCFZRH: u16,
OPDCH: u16,
OPPKH: u16,
OPUCH: u16,
OPZRH: u16,
OPNPKH: u16,
OPNZRH: u16,
) -> __BindgenBitfieldUnit<[u8; 2usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 2usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let OCFDCH: u16 = unsafe { ::core::mem::transmute(OCFDCH) };
OCFDCH as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let OCFPKH: u16 = unsafe { ::core::mem::transmute(OCFPKH) };
OCFPKH as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let OCFUCH: u16 = unsafe { ::core::mem::transmute(OCFUCH) };
OCFUCH as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let OCFZRH: u16 = unsafe { ::core::mem::transmute(OCFZRH) };
OCFZRH as u64
});
__bindgen_bitfield_unit.set(4usize, 2u8, {
let OPDCH: u16 = unsafe { ::core::mem::transmute(OPDCH) };
OPDCH as u64
});
__bindgen_bitfield_unit.set(6usize, 2u8, {
let OPPKH: u16 = unsafe { ::core::mem::transmute(OPPKH) };
OPPKH as u64
});
__bindgen_bitfield_unit.set(8usize, 2u8, {
let OPUCH: u16 = unsafe { ::core::mem::transmute(OPUCH) };
OPUCH as u64
});
__bindgen_bitfield_unit.set(10usize, 2u8, {
let OPZRH: u16 = unsafe { ::core::mem::transmute(OPZRH) };
OPZRH as u64
});
__bindgen_bitfield_unit.set(12usize, 2u8, {
let OPNPKH: u16 = unsafe { ::core::mem::transmute(OPNPKH) };
OPNPKH as u64
});
__bindgen_bitfield_unit.set(14usize, 2u8, {
let OPNZRH: u16 = unsafe { ::core::mem::transmute(OPNZRH) };
OPNZRH as u64
});
__bindgen_bitfield_unit
}
}
#[doc = " @brief The configuration of Output-Compare low channel(OUL/OVL/OWL)"]
#[repr(C)]
#[derive(Copy, Clone)]
pub union un_tmr4_oc_ocmrl_t {
#[doc = "< OCMRxL(x=U/V/W) register"]
pub OCMRx: u32,
pub OCMRx_f: un_tmr4_oc_ocmrl_t__bindgen_ty_1,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct un_tmr4_oc_ocmrl_t__bindgen_ty_1 {
pub _bitfield_align_1: [u8; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl un_tmr4_oc_ocmrl_t__bindgen_ty_1 {
#[inline]
pub fn OCFDCL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_OCFDCL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn OCFDCL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
0usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_OCFDCL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
0usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn OCFPKL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_OCFPKL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn OCFPKL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
1usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_OCFPKL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
1usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn OCFUCL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_OCFUCL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn OCFUCL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
2usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_OCFUCL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
2usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn OCFZRL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_OCFZRL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub unsafe fn OCFZRL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
3usize,
1u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_OCFZRL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
3usize,
1u8,
val as u64,
)
}
}
#[inline]
pub fn OPDCL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 2u8) as u32) }
}
#[inline]
pub fn set_OPDCL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn OPDCL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
4usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_OPDCL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
4usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn OPPKL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 2u8) as u32) }
}
#[inline]
pub fn set_OPPKL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn OPPKL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
6usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_OPPKL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
6usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn OPUCL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 2u8) as u32) }
}
#[inline]
pub fn set_OPUCL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn OPUCL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
8usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_OPUCL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
8usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn OPZRL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 2u8) as u32) }
}
#[inline]
pub fn set_OPZRL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn OPZRL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
10usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_OPZRL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
10usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn OPNPKL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 2u8) as u32) }
}
#[inline]
pub fn set_OPNPKL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn OPNPKL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
12usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_OPNPKL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
12usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn OPNZRL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 2u8) as u32) }
}
#[inline]
pub fn set_OPNZRL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn OPNZRL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
14usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_OPNZRL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
14usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn EOPNDCL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 2u8) as u32) }
}
#[inline]
pub fn set_EOPNDCL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn EOPNDCL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
16usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_EOPNDCL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
16usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn EOPNUCL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 2u8) as u32) }
}
#[inline]
pub fn set_EOPNUCL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn EOPNUCL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
18usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_EOPNUCL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
18usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn EOPDCL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 2u8) as u32) }
}
#[inline]
pub fn set_EOPDCL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn EOPDCL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
20usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_EOPDCL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
20usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn EOPPKL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 2u8) as u32) }
}
#[inline]
pub fn set_EOPPKL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn EOPPKL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
22usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_EOPPKL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
22usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn EOPUCL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 2u8) as u32) }
}
#[inline]
pub fn set_EOPUCL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn EOPUCL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
24usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_EOPUCL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
24usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn EOPZRL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(26usize, 2u8) as u32) }
}
#[inline]
pub fn set_EOPZRL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(26usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn EOPZRL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
26usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_EOPZRL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
26usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn EOPNPKL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 2u8) as u32) }
}
#[inline]
pub fn set_EOPNPKL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn EOPNPKL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
28usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_EOPNPKL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
28usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn EOPNZRL(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(30usize, 2u8) as u32) }
}
#[inline]
pub fn set_EOPNZRL(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(30usize, 2u8, val as u64)
}
}
#[inline]
pub unsafe fn EOPNZRL_raw(this: *const Self) -> u32 {
unsafe {
::core::mem::transmute(<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_get(
::core::ptr::addr_of!((*this)._bitfield_1),
30usize,
2u8,
) as u32)
}
}
#[inline]
pub unsafe fn set_EOPNZRL_raw(this: *mut Self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
<__BindgenBitfieldUnit<[u8; 4usize]>>::raw_set(
::core::ptr::addr_of_mut!((*this)._bitfield_1),
30usize,
2u8,
val as u64,
)
}
}
#[inline]
pub fn new_bitfield_1(
OCFDCL: u32,
OCFPKL: u32,
OCFUCL: u32,
OCFZRL: u32,
OPDCL: u32,
OPPKL: u32,
OPUCL: u32,
OPZRL: u32,
OPNPKL: u32,
OPNZRL: u32,
EOPNDCL: u32,
EOPNUCL: u32,
EOPDCL: u32,
EOPPKL: u32,
EOPUCL: u32,
EOPZRL: u32,
EOPNPKL: u32,
EOPNZRL: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let OCFDCL: u32 = unsafe { ::core::mem::transmute(OCFDCL) };
OCFDCL as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let OCFPKL: u32 = unsafe { ::core::mem::transmute(OCFPKL) };
OCFPKL as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let OCFUCL: u32 = unsafe { ::core::mem::transmute(OCFUCL) };
OCFUCL as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let OCFZRL: u32 = unsafe { ::core::mem::transmute(OCFZRL) };
OCFZRL as u64
});
__bindgen_bitfield_unit.set(4usize, 2u8, {
let OPDCL: u32 = unsafe { ::core::mem::transmute(OPDCL) };
OPDCL as u64
});
__bindgen_bitfield_unit.set(6usize, 2u8, {
let OPPKL: u32 = unsafe { ::core::mem::transmute(OPPKL) };
OPPKL as u64
});
__bindgen_bitfield_unit.set(8usize, 2u8, {
let OPUCL: u32 = unsafe { ::core::mem::transmute(OPUCL) };
OPUCL as u64
});
__bindgen_bitfield_unit.set(10usize, 2u8, {
let OPZRL: u32 = unsafe { ::core::mem::transmute(OPZRL) };
OPZRL as u64
});
__bindgen_bitfield_unit.set(12usize, 2u8, {
let OPNPKL: u32 = unsafe { ::core::mem::transmute(OPNPKL) };
OPNPKL as u64
});
__bindgen_bitfield_unit.set(14usize, 2u8, {
let OPNZRL: u32 = unsafe { ::core::mem::transmute(OPNZRL) };
OPNZRL as u64
});
__bindgen_bitfield_unit.set(16usize, 2u8, {
let EOPNDCL: u32 = unsafe { ::core::mem::transmute(EOPNDCL) };
EOPNDCL as u64
});
__bindgen_bitfield_unit.set(18usize, 2u8, {
let EOPNUCL: u32 = unsafe { ::core::mem::transmute(EOPNUCL) };
EOPNUCL as u64
});
__bindgen_bitfield_unit.set(20usize, 2u8, {
let EOPDCL: u32 = unsafe { ::core::mem::transmute(EOPDCL) };
EOPDCL as u64
});
__bindgen_bitfield_unit.set(22usize, 2u8, {
let EOPPKL: u32 = unsafe { ::core::mem::transmute(EOPPKL) };
EOPPKL as u64
});
__bindgen_bitfield_unit.set(24usize, 2u8, {
let EOPUCL: u32 = unsafe { ::core::mem::transmute(EOPUCL) };
EOPUCL as u64
});
__bindgen_bitfield_unit.set(26usize, 2u8, {
let EOPZRL: u32 = unsafe { ::core::mem::transmute(EOPZRL) };
EOPZRL as u64
});
__bindgen_bitfield_unit.set(28usize, 2u8, {
let EOPNPKL: u32 = unsafe { ::core::mem::transmute(EOPNPKL) };
EOPNPKL as u64
});
__bindgen_bitfield_unit.set(30usize, 2u8, {
let EOPNZRL: u32 = unsafe { ::core::mem::transmute(EOPNZRL) };
EOPNZRL as u64
});
__bindgen_bitfield_unit
}
}
#[doc = " @brief TMR4 Output-Compare(OC) initialization configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_oc_init_t {
#[doc = "< TMR4 OC compare match value.\nThis parameter can be a value of half-word."]
pub u16CompareValue: u16,
#[doc = "< Port output polarity when OC is disabled.\nThis parameter can be a value of @ref TMR4_OC_Invalid_Output_Polarity."]
pub u16OcInvalidPolarity: u16,
#[doc = "< Register OCMR buffer transfer condition.\nThis parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition."]
pub u16CompareModeBufCond: u16,
#[doc = "< Register OCCR buffer transfer condition.\nThis parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition."]
pub u16CompareValueBufCond: u16,
#[doc = "< Enable the specified object(OCMR/OCCR) register buffer linked transfer with the counter interrupt mask.\nThis parameter can be a value of @ref TMR4_OC_Buffer_Object."]
pub u16BufLinkTransObject: u16,
}
#[doc = " @brief TMR4 PWM initialization configuration\n @note The clock division(u16ClockDiv) is valid when TMR4 clock source is the internal clock."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_pwm_init_t {
#[doc = "< Select PWM mode\nThis parameter can be a value of @ref TMR4_PWM_Mode"]
pub u16Mode: u16,
#[doc = "< The internal clock division of PWM timer.\nThis parameter can be a value of @ref TMR4_PWM_Clock_Division."]
pub u16ClockDiv: u16,
#[doc = "< TMR4 PWM polarity\nThis parameter can be a value of @ref TMR4_PWM_Polarity"]
pub u16Polarity: u16,
}
#[doc = " @brief TMR4 Special-Event(EVT) initialization configuration"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr4_evt_init_t {
#[doc = "< TMR4 event mode\nThis parameter can be a value of @ref TMR4_Event_Mode"]
pub u16Mode: u16,
#[doc = "< TMR4 event compare match value.\nThis parameter can be a value of half-word"]
pub u16CompareValue: u16,
#[doc = "< TMR4 event output event when match count compare condition.\nThis parameter can be a value of @ref TMR4_Event_Output_Event"]
pub u16OutputEvent: u16,
#[doc = "< Enable the specified count compare type with counter count to generate event.\nThis parameter can be a value of @ref TMR4_Event_Match_Condition"]
pub u16MatchCond: u16,
}
#[doc = " @brief Timer6 count function structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_init_t {
#[doc = "< Specifies the count source @ref TMR6_Count_Src_Define"]
pub u8CountSrc: u8,
pub sw_count: stc_tmr6_init_t__bindgen_ty_1,
pub hw_count: stc_tmr6_init_t__bindgen_ty_2,
#[doc = "< The period reference value. (0x00 ~ 0xFFFF) or (0x00 ~ 0xFFFFFFFF)"]
pub u32PeriodValue: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_init_t__bindgen_ty_1 {
#[doc = "< Count clock division select, @ref TMR6_Count_Clock_Define"]
pub u32ClockDiv: u32,
#[doc = "< Count mode, @ref TMR6_Count_Mode_Define"]
pub u32CountMode: u32,
#[doc = "< Count direction, @ref TMR6_Count_Dir_Define"]
pub u32CountDir: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_init_t__bindgen_ty_2 {
#[doc = "< Hardware count up condition. @ref TMR6_HW_Count_Up_Cond_Define"]
pub u32CountUpCond: u32,
#[doc = "< Hardware count down condition. @ref TMR6_HW_Count_Down_Cond_Define"]
pub u32CountDownCond: u32,
}
#[doc = " @brief Timer6 pwm output function structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_pwm_init_t {
#[doc = "< Range (0 ~ 0xFFFF) or (0 ~ 0xFFFFFFFF)"]
pub u32CompareValue: u32,
#[doc = "< Pin polarity when count start @ref TMR6_Pin_Polarity_Define"]
pub u32StartPolarity: u32,
#[doc = "< Pin polarity when count stop @ref TMR6_Pin_Polarity_Define"]
pub u32StopPolarity: u32,
pub u32CompareMatchPolarity: u32,
#[doc = " Pin polarity when compare register @ref TMR6_Pin_Polarity_Define"]
pub u32PeriodMatchPolarity: u32,
#[doc = " Pin polarity when period register @ref TMR6_Pin_Polarity_Define"]
pub u32StartStopHold: u32,
}
#[doc = " @brief Timer6 buffer function configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_buf_config_t {
#[doc = "< The buffer number, and this parameter can be a value of \\\n@ref TMR6_Buf_Num_Define"]
pub u32BufNum: u32,
#[doc = "< The buffer send time, and this parameter can be a value of \\\n@ref TMR6_Buf_Trans_Cond_Define"]
pub u32BufTransCond: u32,
}
#[doc = " @brief Timer6 Valid period function configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_valid_period_config_t {
#[doc = "< The count condition, and this parameter can be a value of \\\n@ref TMR6_Valid_Period_Count_Cond_Define"]
pub u32CountCond: u32,
#[doc = "< The interval of the valid period @ref TMR6_Valid_Period_Count_Define"]
pub u32PeriodInterval: u32,
}
#[doc = " @brief Timer6 EMB configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_emb_config_t {
#[doc = "< Pin output status when EMB event valid @ref TMR6_Emb_Pin_Status_Define"]
pub u32PinStatus: u32,
}
#[doc = " @brief Timer6 Dead time function configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_deadtime_config_t {
#[doc = "< Enable down count dead time register equal to up count DT register \\\n@ref TMR6_DeadTime_Reg_Equal_Func_Define"]
pub u32EqualUpDown: u32,
#[doc = "< Enable buffer transfer for up count dead time register (DTUBR-->DTUAR) \\\n@ref TMR6_DeadTime_CountUp_Buf_Func_Define"]
pub u32BufUp: u32,
#[doc = "< Enable buffer transfer for down count dead time register (DTDBR-->DTDAR) \\\n@ref TMR6_DeadTime_CountDown_Buf_Func_Define"]
pub u32BufDown: u32,
}
#[doc = " @brief Timer6 Dead time function configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_zmask_config_t {
#[doc = "< Z phase input mask periods selection @ref TMR6_Zmask_Cycle_Define"]
pub u32ZMaskCycle: u32,
#[doc = "< As position count timer, clear function enable(TRUE) or disable(FALSE) during \\\nthe time of Z phase input mask @ref TMR6_Zmask_Pos_Unit_Clear_Func_Define"]
pub u32PosCountMaskFunc: u32,
#[doc = "< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) \\\nduring the time of Z phase input mask \\\n@ref TMR6_Zmask_Revo_Unit_Count_Func_Define"]
pub u32RevoCountMaskFunc: u32,
}
#[doc = " Global type definitions ('typedef')\n/\n/**\n @defgroup TMRA_Global_Types TMRA Global Types\n @{\n/\n/**\n @brief TMRA initialization structure."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_init_t {
#[doc = "< Specifies the count source of TMRA.\nThis parameter can be a value of @ref TMRA_Count_Src"]
pub u8CountSrc: u8,
pub sw_count: stc_tmra_init_t__bindgen_ty_1,
pub hw_count: stc_tmra_init_t__bindgen_ty_2,
#[doc = "< Specifies the period reference value.\nThis parameter can be a number between 0U and 0xFFFFU, inclusive."]
pub u32PeriodValue: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_init_t__bindgen_ty_1 {
#[doc = "< Specifies the divider of software clock source.\nThis parameter can be a value of @ref TMRA_Clock_Divider"]
pub u8ClockDiv: u8,
#[doc = "< Specifies count mode.\nThis parameter can be a value of @ref TMRA_Count_Mode"]
pub u8CountMode: u8,
#[doc = "< Specifies count direction.\nThis parameter can be a value of @ref TMRA_Count_Dir"]
pub u8CountDir: u8,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_init_t__bindgen_ty_2 {
#[doc = "< Hardware count up condition.\nThis parameter can be a value of @ref TMRA_Hard_Count_Up_Condition"]
pub u16CountUpCond: u16,
#[doc = "< Hardware count down condition.\nThis parameter can be a value of @ref TMRA_Hard_Count_Down_Condition"]
pub u16CountDownCond: u16,
}
#[doc = " @brief TMRA PWM configuration structure."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmra_pwm_init_t {
#[doc = "< Specifies compare value of the TMRA channel.\nThis parameter can be a number between:\n0UL and 0xFFFFFFFFUL for 32-bit TimerA units.\n0UL and 0xFFFFUL for 16-bit TimerA units."]
pub u32CompareValue: u32,
#[doc = "< Specifies the polarity when the counter start counting.\nThis parameter can be a value of @ref TMRA_PWM_Polarity\nNOTE: CAN NOT be specified as TMRA_PWM_LOW or TMRA_PWM_HIGH when\nsw_count.u16ClockDiv of @ref stc_tmra_init_t is NOT specified\nas @ref TMRA_CLK_DIV1"]
pub u16StartPolarity: u16,
#[doc = "< Specifies the polarity when the counter stop counting.\nThis parameter can be a value of @ref TMRA_PWM_Polarity"]
pub u16StopPolarity: u16,
#[doc = "< Specifies the polarity when the counter matches the compare register.\nThis parameter can be a value of @ref TMRA_PWM_Polarity"]
pub u16CompareMatchPolarity: u16,
#[doc = "< Specifies the polarity when the counter matches the period register.\nThis parameter can be a value of @ref TMRA_PWM_Polarity"]
pub u16PeriodMatchPolarity: u16,
}
#[doc = " @brief clock synchronization mode initialization structure definition\n @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_clocksync_init_t {
#[doc = "< Clock Source.\nThis parameter can be a value of @ref USART_Clock_Source"]
pub u32ClockSrc: u32,
#[doc = "< Clock division.\nThis parameter can be a value of @ref USART_Clock_Division."]
pub u32ClockDiv: u32,
#[doc = "< USART baudrate.\nThis parameter is valid when clock source is the internal clock."]
pub u32Baudrate: u32,
#[doc = "< Significant bit.\nThis parameter can be a value of @ref USART_First_Bit"]
pub u32FirstBit: u32,
#[doc = "< Hardware flow control.\nThis parameter can be a value of @ref USART_Hardware_Flow_Control"]
pub u32HWFlowControl: u32,
}
#[doc = " @brief UART multiple-processor initialization structure definition\n @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_multiprocessor_init_t {
#[doc = "< Clock Source.\nThis parameter can be a value of @ref USART_Clock_Source"]
pub u32ClockSrc: u32,
#[doc = "< Clock division.\nThis parameter can be a value of @ref USART_Clock_Division."]
pub u32ClockDiv: u32,
#[doc = "< USART_CK output selection.\nThis parameter can be a value of @ref USART_CK_Output_Selection."]
pub u32CKOutput: u32,
#[doc = "< USART baudrate.\nThis parameter is valid when clock source is the internal clock."]
pub u32Baudrate: u32,
#[doc = "< Data width.\nThis parameter can be a value of @ref USART_Data_Width_Bit"]
pub u32DataWidth: u32,
#[doc = "< Stop Bits.\nThis parameter can be a value of @ref USART_Stop_Bit"]
pub u32StopBit: u32,
#[doc = "< Oversampling Bits.\nThis parameter can be a value of @ref USART_Over_Sample_Bit"]
pub u32OverSampleBit: u32,
#[doc = "< Significant bit.\nThis parameter can be a value of @ref USART_First_Bit"]
pub u32FirstBit: u32,
#[doc = "< Start Bit Detect Polarity.\nThis parameter can be a value of @ref USART_Start_Bit_Polarity"]
pub u32StartBitPolarity: u32,
#[doc = "< Hardware flow control.\nThis parameter can be a value of @ref USART_Hardware_Flow_Control"]
pub u32HWFlowControl: u32,
}
#[doc = " @brief UART mode initialization structure definition\n @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock."]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_uart_init_t {
#[doc = "< Clock Source.\nThis parameter can be a value of @ref USART_Clock_Source"]
pub u32ClockSrc: u32,
#[doc = "< Clock division.\nThis parameter can be a value of @ref USART_Clock_Division."]
pub u32ClockDiv: u32,
#[doc = "< USART_CK output selection.\nThis parameter can be a value of @ref USART_CK_Output_Selection."]
pub u32CKOutput: u32,
#[doc = "< USART baudrate.\nThis parameter is valid when clock source is the internal clock."]
pub u32Baudrate: u32,
#[doc = "< Data width.\nThis parameter can be a value of @ref USART_Data_Width_Bit"]
pub u32DataWidth: u32,
#[doc = "< Stop Bits.\nThis parameter can be a value of @ref USART_Stop_Bit"]
pub u32StopBit: u32,
#[doc = "< Parity format.\nThis parameter can be a value of @ref USART_Parity_Control"]
pub u32Parity: u32,
#[doc = "< Oversampling Bits.\nThis parameter can be a value of @ref USART_Over_Sample_Bit"]
pub u32OverSampleBit: u32,
#[doc = "< Significant bit.\nThis parameter can be a value of @ref USART_First_Bit"]
pub u32FirstBit: u32,
#[doc = "< Start Bit Detect Polarity.\nThis parameter can be a value of @ref USART_Start_Bit_Polarity"]
pub u32StartBitPolarity: u32,
#[doc = "< Hardware flow control.\nThis parameter can be a value of @ref USART_Hardware_Flow_Control"]
pub u32HWFlowControl: u32,
}
#[doc = " @brief Smartcard mode initialization structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_usart_smartcard_init_t {
#[doc = "< Clock division. This parameter can be a value of @ref USART_Clock_Division.\n@note This parameter is valid when clock source is the internal clock."]
pub u32ClockDiv: u32,
#[doc = "< USART_CK output selection. This parameter can be a value of @ref USART_CK_Output_Selection.\n@note This parameter is valid when clock source is the internal clock."]
pub u32CKOutput: u32,
#[doc = "< USART baudrate.\nThis parameter is calculated according with smartcard default ETU and clock."]
pub u32Baudrate: u32,
#[doc = "< Significant bit.\nThis parameter can be a value of @ref USART_First_Bit"]
pub u32FirstBit: u32,
}
#[doc = " @brief WDT Init structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_wdt_init_t {
#[doc = "< Specifies the counting period of WDT.\nThis parameter can be a value of @ref WDT_Count_Period"]
pub u32CountPeriod: u32,
#[doc = "< Specifies the clock division factor of WDT.\nThis parameter can be a value of @ref WDT_Clock_Division"]
pub u32ClockDiv: u32,
#[doc = "< Specifies the allow refresh range of WDT.\nThis parameter can be a value of @ref WDT_Refresh_Range"]
pub u32RefreshRange: u32,
#[doc = "< Specifies the count state in Low Power Mode (Sleep Mode).\nThis parameter can be a value of @ref WDT_LPM_Count"]
pub u32LPMCount: u32,
#[doc = "< Specifies the type of exception response for WDT.\nThis parameter can be a value of @ref WDT_Exception_Type"]
pub u32ExceptionType: u32,
}
unsafe extern "C" {
pub fn usb_initusbcore(USBx: *mut LL_USB_TypeDef, basic_cfgs: *mut USB_CORE_BASIC_CFGS);
pub fn usb_setregaddr(
USBx: *mut LL_USB_TypeDef,
pstcPortIdentify: *mut stc_usb_port_identify,
basic_cfgs: *mut USB_CORE_BASIC_CFGS,
);
pub fn usb_rdpkt(USBx: *mut LL_USB_TypeDef, pu8dest: *mut u8, len: u16);
pub fn usb_wrpkt(
USBx: *mut LL_USB_TypeDef,
pu8src: *const u8,
ch_ep_num: u8,
len: u16,
u8DmaEn: u8,
);
pub fn usb_txfifoflush(USBx: *mut LL_USB_TypeDef, num: u32);
pub fn usb_rxfifoflush(USBx: *mut LL_USB_TypeDef);
pub fn usb_modeset(USBx: *mut LL_USB_TypeDef, mode: u8);
pub fn usb_coresoftrst(USBx: *mut LL_USB_TypeDef);
pub fn usb_devmodeinit(USBx: *mut LL_USB_TypeDef, basic_cfgs: *mut USB_CORE_BASIC_CFGS);
pub fn usb_devinten(USBx: *mut LL_USB_TypeDef, u8DmaEn: u8);
pub fn usb_ep0activate(USBx: *mut LL_USB_TypeDef);
pub fn usb_epactive(USBx: *mut LL_USB_TypeDef, ep: *mut USB_DEV_EP);
pub fn usb_epdeactive(USBx: *mut LL_USB_TypeDef, ep: *mut USB_DEV_EP);
pub fn usb_epntransbegin(USBx: *mut LL_USB_TypeDef, ep: *mut USB_DEV_EP, u8DmaEn: u8);
pub fn usb_ep0transbegin(USBx: *mut LL_USB_TypeDef, ep: *mut USB_DEV_EP, u8DmaEn: u8);
pub fn usb_setepstall(USBx: *mut LL_USB_TypeDef, ep: *mut USB_DEV_EP);
pub fn usb_clearepstall(USBx: *mut LL_USB_TypeDef, ep: *mut USB_DEV_EP);
pub fn usb_ep0revcfg(USBx: *mut LL_USB_TypeDef, u8DmaEn: u8, u8RevBuf: *mut u8);
pub fn usb_remotewakeupen(USBx: *mut LL_USB_TypeDef);
pub fn usb_epstatusset(USBx: *mut LL_USB_TypeDef, ep: *mut USB_DEV_EP, Status: u32);
pub fn usb_epstatusget(USBx: *mut LL_USB_TypeDef, ep: *mut USB_DEV_EP) -> u32;
pub fn usb_devepdis(USBx: *mut LL_USB_TypeDef, u8EpNum: u8);
pub fn usb_ctrldevconnect(USBx: *mut LL_USB_TypeDef, link: u8);
#[doc = " Global function prototypes (definition in C source)\n/\n/**\n @addtogroup LL_Global_Functions\n @{"]
pub fn LL_PERIPH_WE(u32Peripheral: u32);
pub fn LL_PERIPH_WP(u32Peripheral: u32);
#[doc = "Global function prototypes (definition in C source)"]
pub fn usb_bsp_init(pdev: *mut usb_core_instance, pstcPortIdentify: *mut stc_usb_port_identify);
pub fn usb_udelay(usec: u32);
pub fn usb_mdelay(msec: u32);
pub fn usb_bsp_nvicconfig(pdev: *mut usb_core_instance);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup Share_Interrupts_Global_Functions\n @{"]
pub fn INTC_ShareIrqCmd(enIntSrc: en_int_src_t, enNewState: en_functional_state_t) -> i32;
pub fn IRQ128_Handler();
pub fn IRQ129_Handler();
pub fn IRQ130_Handler();
pub fn IRQ131_Handler();
pub fn IRQ132_Handler();
pub fn IRQ136_Handler();
pub fn IRQ137_Handler();
pub fn IRQ138_Handler();
pub fn IRQ139_Handler();
pub fn IRQ140_Handler();
pub fn IRQ141_Handler();
pub fn IRQ142_Handler();
pub fn IRQ143_Handler();
pub fn EXTINT00_IrqHandler();
pub fn EXTINT01_IrqHandler();
pub fn EXTINT02_IrqHandler();
pub fn EXTINT03_IrqHandler();
pub fn EXTINT04_IrqHandler();
pub fn EXTINT05_IrqHandler();
pub fn EXTINT06_IrqHandler();
pub fn EXTINT07_IrqHandler();
pub fn EXTINT08_IrqHandler();
pub fn EXTINT09_IrqHandler();
pub fn EXTINT10_IrqHandler();
pub fn EXTINT11_IrqHandler();
pub fn EXTINT12_IrqHandler();
pub fn EXTINT13_IrqHandler();
pub fn EXTINT14_IrqHandler();
pub fn EXTINT15_IrqHandler();
pub fn DMA1_TC0_IrqHandler();
pub fn DMA1_TC1_IrqHandler();
pub fn DMA1_TC2_IrqHandler();
pub fn DMA1_TC3_IrqHandler();
pub fn DMA2_TC0_IrqHandler();
pub fn DMA2_TC1_IrqHandler();
pub fn DMA2_TC2_IrqHandler();
pub fn DMA2_TC3_IrqHandler();
pub fn DMA1_BTC0_IrqHandler();
pub fn DMA1_BTC1_IrqHandler();
pub fn DMA1_BTC2_IrqHandler();
pub fn DMA1_BTC3_IrqHandler();
pub fn DMA2_BTC0_IrqHandler();
pub fn DMA2_BTC1_IrqHandler();
pub fn DMA2_BTC2_IrqHandler();
pub fn DMA2_BTC3_IrqHandler();
pub fn DMA1_Error0_IrqHandler();
pub fn DMA1_Error1_IrqHandler();
pub fn DMA1_Error2_IrqHandler();
pub fn DMA1_Error3_IrqHandler();
pub fn DMA2_Error0_IrqHandler();
pub fn DMA2_Error1_IrqHandler();
pub fn DMA2_Error2_IrqHandler();
pub fn DMA2_Error3_IrqHandler();
pub fn EFM_ProgramEraseError_IrqHandler();
pub fn EFM_ColError_IrqHandler();
pub fn EFM_OpEnd_IrqHandler();
pub fn QSPI_Error_IrqHandler();
pub fn DCU1_IrqHandler();
pub fn DCU2_IrqHandler();
pub fn DCU3_IrqHandler();
pub fn DCU4_IrqHandler();
pub fn TMR0_1_CmpA_IrqHandler();
pub fn TMR0_1_CmpB_IrqHandler();
pub fn TMR0_2_CmpA_IrqHandler();
pub fn TMR0_2_CmpB_IrqHandler();
pub fn CLK_XtalStop_IrqHandler();
pub fn PWC_WakeupTimer_IrqHandler();
pub fn SWDT_IrqHandler();
pub fn WDT_IrqHandler();
pub fn TMR6_1_GCmpA_IrqHandler();
pub fn TMR6_1_GCmpB_IrqHandler();
pub fn TMR6_1_GCmpC_IrqHandler();
pub fn TMR6_1_GCmpD_IrqHandler();
pub fn TMR6_1_GCmpE_IrqHandler();
pub fn TMR6_1_GCmpF_IrqHandler();
pub fn TMR6_1_GOvf_IrqHandler();
pub fn TMR6_1_GUdf_IrqHandler();
pub fn TMR6_1_GDte_IrqHandler();
pub fn TMR6_1_SCmpA_IrqHandler();
pub fn TMR6_1_SCmpB_IrqHandler();
pub fn TMR6_2_GCmpA_IrqHandler();
pub fn TMR6_2_GCmpB_IrqHandler();
pub fn TMR6_2_GCmpC_IrqHandler();
pub fn TMR6_2_GCmpD_IrqHandler();
pub fn TMR6_2_GCmpE_IrqHandler();
pub fn TMR6_2_GCmpF_IrqHandler();
pub fn TMR6_2_GOvf_IrqHandler();
pub fn TMR6_2_GUdf_IrqHandler();
pub fn TMR6_2_GDte_IrqHandler();
pub fn TMR6_2_SCmpA_IrqHandler();
pub fn TMR6_2_SCmpB_IrqHandler();
pub fn TMR6_3_GCmpA_IrqHandler();
pub fn TMR6_3_GCmpB_IrqHandler();
pub fn TMR6_3_GCmpC_IrqHandler();
pub fn TMR6_3_GCmpD_IrqHandler();
pub fn TMR6_3_GCmpE_IrqHandler();
pub fn TMR6_3_GCmpF_IrqHandler();
pub fn TMR6_3_GOvf_IrqHandler();
pub fn TMR6_3_GUdf_IrqHandler();
pub fn TMR6_3_GDte_IrqHandler();
pub fn TMR6_3_SCmpA_IrqHandler();
pub fn TMR6_3_SCmpB_IrqHandler();
pub fn TMRA_1_Ovf_IrqHandler();
pub fn TMRA_1_Udf_IrqHandler();
pub fn TMRA_1_Cmp_IrqHandler();
pub fn TMRA_2_Ovf_IrqHandler();
pub fn TMRA_2_Udf_IrqHandler();
pub fn TMRA_2_Cmp_IrqHandler();
pub fn TMRA_3_Ovf_IrqHandler();
pub fn TMRA_3_Udf_IrqHandler();
pub fn TMRA_3_Cmp_IrqHandler();
pub fn TMRA_4_Ovf_IrqHandler();
pub fn TMRA_4_Udf_IrqHandler();
pub fn TMRA_4_Cmp_IrqHandler();
pub fn TMRA_5_Ovf_IrqHandler();
pub fn TMRA_5_Udf_IrqHandler();
pub fn TMRA_5_Cmp_IrqHandler();
pub fn TMRA_6_Ovf_IrqHandler();
pub fn TMRA_6_Udf_IrqHandler();
pub fn TMRA_6_Cmp_IrqHandler();
pub fn USBFS_Global_IrqHandler();
pub fn USART1_RxError_IrqHandler();
pub fn USART1_RxFull_IrqHandler();
pub fn USART1_TxEmpty_IrqHandler();
pub fn USART1_TxComplete_IrqHandler();
pub fn USART1_RxTO_IrqHandler();
pub fn USART2_RxError_IrqHandler();
pub fn USART2_RxFull_IrqHandler();
pub fn USART2_TxEmpty_IrqHandler();
pub fn USART2_TxComplete_IrqHandler();
pub fn USART2_RxTO_IrqHandler();
pub fn USART3_RxError_IrqHandler();
pub fn USART3_RxFull_IrqHandler();
pub fn USART3_TxEmpty_IrqHandler();
pub fn USART3_TxComplete_IrqHandler();
pub fn USART3_RxTO_IrqHandler();
pub fn USART4_RxError_IrqHandler();
pub fn USART4_RxFull_IrqHandler();
pub fn USART4_TxEmpty_IrqHandler();
pub fn USART4_TxComplete_IrqHandler();
pub fn USART4_RxTO_IrqHandler();
pub fn SPI1_RxFull_IrqHandler();
pub fn SPI1_TxEmpty_IrqHandler();
pub fn SPI1_Error_IrqHandler();
pub fn SPI1_Idle_IrqHandler();
pub fn SPI2_RxFull_IrqHandler();
pub fn SPI2_TxEmpty_IrqHandler();
pub fn SPI2_Error_IrqHandler();
pub fn SPI2_Idle_IrqHandler();
pub fn SPI3_RxFull_IrqHandler();
pub fn SPI3_TxEmpty_IrqHandler();
pub fn SPI3_Error_IrqHandler();
pub fn SPI3_Idle_IrqHandler();
pub fn SPI4_RxFull_IrqHandler();
pub fn SPI4_TxEmpty_IrqHandler();
pub fn SPI4_Error_IrqHandler();
pub fn SPI4_Idle_IrqHandler();
pub fn TMR4_1_GCmpUH_IrqHandler();
pub fn TMR4_1_GCmpUL_IrqHandler();
pub fn TMR4_1_GCmpVH_IrqHandler();
pub fn TMR4_1_GCmpVL_IrqHandler();
pub fn TMR4_1_GCmpWH_IrqHandler();
pub fn TMR4_1_GCmpWL_IrqHandler();
pub fn TMR4_1_GOvf_IrqHandler();
pub fn TMR4_1_GUdf_IrqHandler();
pub fn TMR4_1_ReloadU_IrqHandler();
pub fn TMR4_1_ReloadV_IrqHandler();
pub fn TMR4_1_ReloadW_IrqHandler();
pub fn TMR4_2_GCmpUH_IrqHandler();
pub fn TMR4_2_GCmpUL_IrqHandler();
pub fn TMR4_2_GCmpVH_IrqHandler();
pub fn TMR4_2_GCmpVL_IrqHandler();
pub fn TMR4_2_GCmpWH_IrqHandler();
pub fn TMR4_2_GCmpWL_IrqHandler();
pub fn TMR4_2_GOvf_IrqHandler();
pub fn TMR4_2_GUdf_IrqHandler();
pub fn TMR4_2_ReloadU_IrqHandler();
pub fn TMR4_2_ReloadV_IrqHandler();
pub fn TMR4_2_ReloadW_IrqHandler();
pub fn TMR4_3_GCmpUH_IrqHandler();
pub fn TMR4_3_GCmpUL_IrqHandler();
pub fn TMR4_3_GCmpVH_IrqHandler();
pub fn TMR4_3_GCmpVL_IrqHandler();
pub fn TMR4_3_GCmpWH_IrqHandler();
pub fn TMR4_3_GCmpWL_IrqHandler();
pub fn TMR4_3_GOvf_IrqHandler();
pub fn TMR4_3_GUdf_IrqHandler();
pub fn TMR4_3_ReloadU_IrqHandler();
pub fn TMR4_3_ReloadV_IrqHandler();
pub fn TMR4_3_ReloadW_IrqHandler();
pub fn EMB_GR0_IrqHandler();
pub fn EMB_GR1_IrqHandler();
pub fn EMB_GR2_IrqHandler();
pub fn EMB_GR3_IrqHandler();
pub fn I2S1_Tx_IrqHandler();
pub fn I2S1_Rx_IrqHandler();
pub fn I2S1_Error_IrqHandler();
pub fn I2S2_Tx_IrqHandler();
pub fn I2S2_Rx_IrqHandler();
pub fn I2S2_Error_IrqHandler();
pub fn I2S3_Tx_IrqHandler();
pub fn I2S3_Rx_IrqHandler();
pub fn I2S3_Error_IrqHandler();
pub fn I2S4_Tx_IrqHandler();
pub fn I2S4_Rx_IrqHandler();
pub fn I2S4_Error_IrqHandler();
pub fn I2C1_RxFull_IrqHandler();
pub fn I2C1_TxComplete_IrqHandler();
pub fn I2C1_TxEmpty_IrqHandler();
pub fn I2C1_EE_IrqHandler();
pub fn I2C2_RxFull_IrqHandler();
pub fn I2C2_TxComplete_IrqHandler();
pub fn I2C2_TxEmpty_IrqHandler();
pub fn I2C2_EE_IrqHandler();
pub fn I2C3_RxFull_IrqHandler();
pub fn I2C3_TxComplete_IrqHandler();
pub fn I2C3_TxEmpty_IrqHandler();
pub fn I2C3_EE_IrqHandler();
pub fn PWC_LVD1_IrqHandler();
pub fn PWC_LVD2_IrqHandler();
pub fn FCM_Error_IrqHandler();
pub fn FCM_End_IrqHandler();
pub fn FCM_Ovf_IrqHandler();
pub fn ADC1_SeqA_IrqHandler();
pub fn ADC1_SeqB_IrqHandler();
pub fn ADC1_ChCmp_IrqHandler();
pub fn ADC1_SeqCmp_IrqHandler();
pub fn ADC2_SeqA_IrqHandler();
pub fn ADC2_SeqB_IrqHandler();
pub fn ADC2_ChCmp_IrqHandler();
pub fn ADC2_SeqCmp_IrqHandler();
pub fn SDIOC1_IrqHandler();
pub fn SDIOC2_IrqHandler();
pub fn CAN_IrqHandler();
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup ADC_Global_Functions\n @{\n/\n/*******************************************************************************\nBasic features"]
pub fn ADC_Init(ADCx: *mut CM_ADC_TypeDef, pstcAdcInit: *const stc_adc_init_t) -> i32;
pub fn ADC_DeInit(ADCx: *mut CM_ADC_TypeDef) -> i32;
pub fn ADC_StructInit(pstcAdcInit: *mut stc_adc_init_t) -> i32;
pub fn ADC_ChCmd(
ADCx: *mut CM_ADC_TypeDef,
u8Seq: u8,
u8Ch: u8,
enNewState: en_functional_state_t,
);
pub fn ADC_MxChCmd(
ADCx: *mut CM_ADC_TypeDef,
u8Seq: u8,
u32MxCh: u32,
enNewState: en_functional_state_t,
);
pub fn ADC_SetSampleTime(ADCx: *mut CM_ADC_TypeDef, u8Ch: u8, u8SampleTime: u8);
pub fn ADC_ConvDataAverageConfig(ADCx: *mut CM_ADC_TypeDef, u16AverageCount: u16);
pub fn ADC_ConvDataAverageChCmd(
ADCx: *mut CM_ADC_TypeDef,
u8Ch: u8,
enNewState: en_functional_state_t,
);
pub fn ADC_ConvDataAverageMxChCmd(
ADCx: *mut CM_ADC_TypeDef,
u32MxCh: u32,
enNewState: en_functional_state_t,
);
pub fn ADC_TriggerConfig(ADCx: *mut CM_ADC_TypeDef, u8Seq: u8, u16TriggerSel: u16);
pub fn ADC_TriggerCmd(ADCx: *mut CM_ADC_TypeDef, u8Seq: u8, enNewState: en_functional_state_t);
pub fn ADC_IntCmd(ADCx: *mut CM_ADC_TypeDef, u8IntType: u8, enNewState: en_functional_state_t);
pub fn ADC_Start(ADCx: *mut CM_ADC_TypeDef) -> i32;
pub fn ADC_Stop(ADCx: *mut CM_ADC_TypeDef);
pub fn ADC_GetValue(ADCx: *const CM_ADC_TypeDef, u8Ch: u8) -> u16;
pub fn ADC_GetResolution(ADCx: *const CM_ADC_TypeDef) -> u16;
pub fn ADC_GetStatus(ADCx: *const CM_ADC_TypeDef, u8Flag: u8) -> en_flag_status_t;
pub fn ADC_ClearStatus(ADCx: *mut CM_ADC_TypeDef, u8Flag: u8);
#[doc = "Advanced features"]
pub fn ADC_ChRemap(ADCx: *mut CM_ADC_TypeDef, u8Ch: u8, u8AdcPin: u8);
pub fn ADC_GetChPin(ADCx: *const CM_ADC_TypeDef, u8Ch: u8) -> u8;
pub fn ADC_ResetChMapping(ADCx: *mut CM_ADC_TypeDef);
pub fn ADC_SyncModeConfig(u16SyncUnit: u16, u16SyncMode: u16, u8TriggerDelay: u8);
pub fn ADC_SyncModeCmd(enNewState: en_functional_state_t);
pub fn ADC_AWD_Config(
ADCx: *mut CM_ADC_TypeDef,
u8AwdUnit: u8,
u8Ch: u8,
pstcAwd: *const stc_adc_awd_config_t,
) -> i32;
pub fn ADC_AWD_SetMode(ADCx: *mut CM_ADC_TypeDef, u8AwdUnit: u8, u16WatchdogMode: u16);
pub fn ADC_AWD_GetMode(ADCx: *mut CM_ADC_TypeDef, u8AwdUnit: u8) -> u16;
pub fn ADC_AWD_SetThreshold(
ADCx: *mut CM_ADC_TypeDef,
u8AwdUnit: u8,
u16LowThreshold: u16,
u16HighThreshold: u16,
);
pub fn ADC_AWD_SelectCh(ADCx: *mut CM_ADC_TypeDef, u8AwdUnit: u8, u8Ch: u8);
pub fn ADC_AWD_DeselectCh(ADCx: *mut CM_ADC_TypeDef, u8AwdUnit: u8, u8Ch: u8);
pub fn ADC_AWD_Cmd(ADCx: *mut CM_ADC_TypeDef, u8AwdUnit: u8, enNewState: en_functional_state_t);
pub fn ADC_AWD_IntCmd(
ADCx: *mut CM_ADC_TypeDef,
u16IntType: u16,
enNewState: en_functional_state_t,
);
pub fn ADC_AWD_GetStatus(ADCx: *const CM_ADC_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn ADC_AWD_ClearStatus(ADCx: *mut CM_ADC_TypeDef, u32Flag: u32);
pub fn ADC_PGA_Config(ADCx: *mut CM_ADC_TypeDef, u8PgaUnit: u8, u8Gain: u8, u8PgaVss: u8);
pub fn ADC_PGA_Cmd(ADCx: *mut CM_ADC_TypeDef, u8PgaUnit: u8, enNewState: en_functional_state_t);
pub fn ADC_PGA_SelectInputSrc(ADCx: *mut CM_ADC_TypeDef, u16PgaInputSrc: u16);
pub fn ADC_PGA_DeselectInputSrc(ADCx: *mut CM_ADC_TypeDef);
pub fn ADC_DataRegAutoClearCmd(ADCx: *mut CM_ADC_TypeDef, enNewState: en_functional_state_t);
pub fn ADC_SetSeqAResumeMode(ADCx: *mut CM_ADC_TypeDef, u16SeqAResumeMode: u16);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup AES_Global_Functions\n @{"]
pub fn AES_Encrypt(
pu8Plaintext: *const u8,
u32PlaintextSize: u32,
pu8Key: *const u8,
u8KeySize: u8,
pu8Ciphertext: *mut u8,
) -> i32;
pub fn AES_Decrypt(
pu8Ciphertext: *const u8,
u32CiphertextSize: u32,
pu8Key: *const u8,
u8KeySize: u8,
pu8Plaintext: *mut u8,
) -> i32;
pub fn AES_DeInit() -> i32;
pub fn AOS_CommonTriggerCmd(
u32Target: u32,
u32CommonTrigger: u32,
enNewState: en_functional_state_t,
);
pub fn AOS_SetTriggerEventSrc(u32Target: u32, enSource: en_event_src_t);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup CAN_Global_Functions\n @{"]
pub fn CAN_Init(CANx: *mut CM_CAN_TypeDef, pstcCanInit: *const stc_can_init_t) -> i32;
pub fn CAN_StructInit(pstcCanInit: *mut stc_can_init_t) -> i32;
pub fn CAN_DeInit(CANx: *mut CM_CAN_TypeDef) -> i32;
pub fn CAN_IntCmd(
CANx: *mut CM_CAN_TypeDef,
u32IntType: u32,
enNewState: en_functional_state_t,
);
pub fn CAN_FillTxFrame(
CANx: *mut CM_CAN_TypeDef,
u8TxBufType: u8,
pstcTx: *const stc_can_tx_frame_t,
) -> i32;
pub fn CAN_StartTx(CANx: *mut CM_CAN_TypeDef, u8TxRequest: u8);
pub fn CAN_AbortTx(CANx: *mut CM_CAN_TypeDef, u8TxBufType: u8);
pub fn CAN_GetRxFrame(CANx: *mut CM_CAN_TypeDef, pstcRx: *mut stc_can_rx_frame_t) -> i32;
pub fn CAN_EnterLocalReset(CANx: *mut CM_CAN_TypeDef);
pub fn CAN_ExitLocalReset(CANx: *mut CM_CAN_TypeDef);
pub fn CAN_GetLocalResetStatus(CANx: *mut CM_CAN_TypeDef) -> en_flag_status_t;
pub fn CAN_GetStatus(CANx: *const CM_CAN_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn CAN_ClearStatus(CANx: *mut CM_CAN_TypeDef, u32Flag: u32);
pub fn CAN_GetStatusValue(CANx: *const CM_CAN_TypeDef) -> u32;
pub fn CAN_GetErrorInfo(CANx: *const CM_CAN_TypeDef, pstcErr: *mut stc_can_error_info_t)
-> i32;
pub fn CAN_GetTxBufStatus(CANx: *const CM_CAN_TypeDef) -> u8;
pub fn CAN_GetRxBufStatus(CANx: *const CM_CAN_TypeDef) -> u8;
pub fn CAN_FilterCmd(
CANx: *mut CM_CAN_TypeDef,
u16FilterSelect: u16,
enNewState: en_functional_state_t,
);
pub fn CAN_SetRxWarnLimit(CANx: *mut CM_CAN_TypeDef, u8RxWarnLimit: u8);
pub fn CAN_SetErrorWarnLimit(CANx: *mut CM_CAN_TypeDef, u8ErrorWarnLimit: u8);
pub fn CAN_TTC_StructInit(pstcCanTtc: *mut stc_can_ttc_config_t) -> i32;
pub fn CAN_TTC_Config(
CANx: *mut CM_CAN_TypeDef,
pstcCanTtc: *const stc_can_ttc_config_t,
) -> i32;
pub fn CAN_TTC_IntCmd(
CANx: *mut CM_CAN_TypeDef,
u8IntType: u8,
enNewState: en_functional_state_t,
);
pub fn CAN_TTC_Cmd(CANx: *mut CM_CAN_TypeDef, enNewState: en_functional_state_t);
pub fn CAN_TTC_GetStatus(CANx: *const CM_CAN_TypeDef, u8Flag: u8) -> en_flag_status_t;
pub fn CAN_TTC_ClearStatus(CANx: *mut CM_CAN_TypeDef, u8Flag: u8);
pub fn CAN_TTC_GetStatusValue(CANx: *const CM_CAN_TypeDef) -> u8;
pub fn CAN_TTC_SetTriggerType(CANx: *mut CM_CAN_TypeDef, u16TriggerType: u16);
pub fn CAN_TTC_SetTxEnableWindow(CANx: *mut CM_CAN_TypeDef, u16TxEnableWindow: u16);
pub fn CAN_TTC_SetTxTriggerTime(CANx: *mut CM_CAN_TypeDef, u16TxTriggerTime: u16);
pub fn CAN_TTC_SetWatchTriggerTime(CANx: *mut CM_CAN_TypeDef, u16WatchTriggerTime: u16);
pub fn CAN_TTC_FillTxFrame(
CANx: *mut CM_CAN_TypeDef,
u8CANTTCTxBuf: u8,
pstcTx: *const stc_can_tx_frame_t,
) -> i32;
pub fn CAN_TTC_GetConfig(
CANx: *const CM_CAN_TypeDef,
pstcCanTtc: *mut stc_can_ttc_config_t,
) -> i32;
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup CLK_Global_Functions\n @{"]
pub fn CLK_HrcCmd(enNewState: en_functional_state_t) -> i32;
pub fn CLK_MrcCmd(enNewState: en_functional_state_t) -> i32;
pub fn CLK_LrcCmd(enNewState: en_functional_state_t) -> i32;
pub fn CLK_HrcTrim(i8TrimVal: i8);
pub fn CLK_MrcTrim(i8TrimVal: i8);
pub fn CLK_LrcTrim(i8TrimVal: i8);
pub fn CLK_XtalStructInit(pstcXtalInit: *mut stc_clock_xtal_init_t) -> i32;
pub fn CLK_XtalInit(pstcXtalInit: *const stc_clock_xtal_init_t) -> i32;
pub fn CLK_XtalCmd(enNewState: en_functional_state_t) -> i32;
pub fn CLK_XtalStdCmd(enNewState: en_functional_state_t);
pub fn CLK_XtalStdInit(u8State: u8, u8ExceptionType: u8) -> i32;
pub fn CLK_SetXtalStdExceptionType(u8ExceptionType: u8) -> i32;
pub fn CLK_ClearXtalStdStatus();
pub fn CLK_GetXtalStdStatus() -> en_flag_status_t;
pub fn CLK_Xtal32StructInit(pstcXtal32Init: *mut stc_clock_xtal32_init_t) -> i32;
pub fn CLK_Xtal32Init(pstcXtal32Init: *const stc_clock_xtal32_init_t) -> i32;
pub fn CLK_Xtal32Cmd(enNewState: en_functional_state_t) -> i32;
pub fn CLK_SetPLLSrc(u32PllSrc: u32);
pub fn CLK_PLLStructInit(pstcPLLInit: *mut stc_clock_pll_init_t) -> i32;
pub fn CLK_PLLInit(pstcPLLInit: *const stc_clock_pll_init_t) -> i32;
pub fn CLK_PLLCmd(enNewState: en_functional_state_t) -> i32;
pub fn CLK_GetPLLClockFreq(pstcPllClkFreq: *mut stc_pll_clock_freq_t) -> i32;
pub fn CLK_PLLxStructInit(pstcPLLxInit: *mut stc_clock_pllx_init_t) -> i32;
pub fn CLK_PLLxInit(pstcPLLxInit: *const stc_clock_pllx_init_t) -> i32;
pub fn CLK_PLLxCmd(enNewState: en_functional_state_t) -> i32;
pub fn CLK_MCOConfig(u8Ch: u8, u8Src: u8, u8Div: u8);
pub fn CLK_MCOCmd(u8Ch: u8, enNewState: en_functional_state_t);
pub fn CLK_GetStableStatus(u8Flag: u8) -> en_flag_status_t;
pub fn CLK_SetSysClockSrc(u8Src: u8);
pub fn CLK_SetClockDiv(u32Clock: u32, u32Div: u32);
pub fn CLK_GetClockFreq(pstcClockFreq: *mut stc_clock_freq_t) -> i32;
pub fn CLK_GetBusClockFreq(u32Clock: u32) -> u32;
pub fn CLK_SetPeriClockSrc(u16Src: u16);
pub fn CLK_SetUSBClockSrc(u8Src: u8);
pub fn CLK_SetI2SClockSrc(u8Unit: u8, u8Src: u8);
pub fn CLK_TpiuClockCmd(enNewState: en_functional_state_t);
pub fn CLK_SetTpiuClockDiv(u8Div: u8);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup CMP_Global_Functions\n @{"]
pub fn CMP_StructInit(pstcCmpInit: *mut stc_cmp_init_t) -> i32;
pub fn CMP_NormalModeInit(CMPx: *mut CM_CMP_TypeDef, pstcCmpInit: *const stc_cmp_init_t)
-> i32;
pub fn CMP_DeInit(CMPx: *mut CM_CMP_TypeDef);
pub fn CMP_FuncCmd(CMPx: *mut CM_CMP_TypeDef, enNewState: en_functional_state_t);
pub fn CMP_IntCmd(CMPx: *mut CM_CMP_TypeDef, enNewState: en_functional_state_t);
pub fn CMP_CompareOutCmd(CMPx: *mut CM_CMP_TypeDef, enNewState: en_functional_state_t);
pub fn CMP_PinVcoutCmd(CMPx: *mut CM_CMP_TypeDef, enNewState: en_functional_state_t);
pub fn CMP_GetStatus(CMPx: *const CM_CMP_TypeDef) -> en_flag_status_t;
pub fn CMP_SetOutDetectEdge(CMPx: *mut CM_CMP_TypeDef, u8CmpEdges: u8);
pub fn CMP_SetOutFilter(CMPx: *mut CM_CMP_TypeDef, u8CmpFilter: u8);
pub fn CMP_SetOutPolarity(CMPx: *mut CM_CMP_TypeDef, u16CmpPolarity: u16);
pub fn CMP_SetPositiveInput(CMPx: *mut CM_CMP_TypeDef, u16PositiveInput: u16);
pub fn CMP_SetNegativeInput(CMPx: *mut CM_CMP_TypeDef, u16NegativeInput: u16);
pub fn CMP_GetScanInpSrc(CMPx: *mut CM_CMP_TypeDef) -> u32;
pub fn CMP_ScanTimeConfig(CMPx: *mut CM_CMP_TypeDef, u16Stable: u16, u16Period: u16) -> i32;
pub fn CMP_ScanCmd(CMPx: *mut CM_CMP_TypeDef, enNewState: en_functional_state_t);
pub fn CMP_8BitDAC_Cmd(u8Ch: u8, enNewState: en_functional_state_t);
pub fn CMP_8BitDAC_AdcRefCmd(u16AdcRefSw: u16, enNewState: en_functional_state_t);
pub fn CMP_8BitDAC_WriteData(u8Ch: u8, u16DACData: u16);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup CRC_Global_Functions\n @{"]
pub fn CRC_StructInit(pstcCrcInit: *mut stc_crc_init_t) -> i32;
pub fn CRC_Init(pstcCrcInit: *const stc_crc_init_t) -> i32;
pub fn CRC_DeInit() -> i32;
pub fn CRC_GetResult() -> u32;
pub fn CRC_SetInitValue(u32Value: u32);
pub fn CRC_GetResultStatus() -> en_flag_status_t;
pub fn CRC_CRC16_AccumulateData(
u8DataWidth: u8,
pvData: *const ::core::ffi::c_void,
u32Len: u32,
pu16Out: *mut u16,
) -> i32;
pub fn CRC_CRC16_Calculate(
u16InitValue: u16,
u8DataWidth: u8,
pvData: *const ::core::ffi::c_void,
u32Len: u32,
pu16Out: *mut u16,
) -> i32;
pub fn CRC_CRC16_CheckData(
u16InitValue: u16,
u8DataWidth: u8,
pvData: *const ::core::ffi::c_void,
u32Len: u32,
u16ExpectValue: u16,
) -> en_flag_status_t;
pub fn CRC_CRC16_GetCheckResult(u16ExpectValue: u16) -> en_flag_status_t;
pub fn CRC_CRC32_AccumulateData(
u8DataWidth: u8,
pvData: *const ::core::ffi::c_void,
u32Len: u32,
pu32Out: *mut u32,
) -> i32;
pub fn CRC_CRC32_Calculate(
u32InitValue: u32,
u8DataWidth: u8,
pvData: *const ::core::ffi::c_void,
u32Len: u32,
pu32Out: *mut u32,
) -> i32;
pub fn CRC_CRC32_CheckData(
u32InitValue: u32,
u8DataWidth: u8,
pvData: *const ::core::ffi::c_void,
u32Len: u32,
u32ExpectValue: u32,
) -> en_flag_status_t;
pub fn CRC_CRC32_GetCheckResult(u32ExpectValue: u32) -> en_flag_status_t;
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup DBGC_Global_Functions\n @{"]
pub fn DBGC_PeriphCmd(u32Periph: u32, enNewState: en_functional_state_t);
pub fn DBGC_TraceIoCmd(enNewState: en_functional_state_t);
pub fn DBGC_TraceModeConfig(u32TraceMode: u32);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup DCU_Global_Functions\n @{"]
pub fn DCU_Init(DCUx: *mut CM_DCU_TypeDef, pstcDcuInit: *const stc_dcu_init_t) -> i32;
pub fn DCU_StructInit(pstcDcuInit: *mut stc_dcu_init_t) -> i32;
pub fn DCU_DeInit(DCUx: *mut CM_DCU_TypeDef) -> i32;
pub fn DCU_SetMode(DCUx: *mut CM_DCU_TypeDef, u32Mode: u32);
pub fn DCU_SetDataWidth(DCUx: *mut CM_DCU_TypeDef, u32DataWidth: u32);
pub fn DCU_SetCompareCond(DCUx: *mut CM_DCU_TypeDef, u32Cond: u32);
pub fn DCU_GetStatus(DCUx: *const CM_DCU_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn DCU_ClearStatus(DCUx: *mut CM_DCU_TypeDef, u32Flag: u32);
pub fn DCU_GlobalIntCmd(DCUx: *mut CM_DCU_TypeDef, enNewState: en_functional_state_t);
pub fn DCU_IntCmd(
DCUx: *mut CM_DCU_TypeDef,
u32IntCategory: u32,
u32IntType: u32,
enNewState: en_functional_state_t,
);
pub fn DCU_ReadData8(DCUx: *const CM_DCU_TypeDef, u32DataIndex: u32) -> u8;
pub fn DCU_WriteData8(DCUx: *mut CM_DCU_TypeDef, u32DataIndex: u32, u8Data: u8);
pub fn DCU_ReadData16(DCUx: *const CM_DCU_TypeDef, u32DataIndex: u32) -> u16;
pub fn DCU_WriteData16(DCUx: *mut CM_DCU_TypeDef, u32DataIndex: u32, u16Data: u16);
pub fn DCU_ReadData32(DCUx: *const CM_DCU_TypeDef, u32DataIndex: u32) -> u32;
pub fn DCU_WriteData32(DCUx: *mut CM_DCU_TypeDef, u32DataIndex: u32, u32Data: u32);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup DMA_Global_Functions\n @{"]
pub fn DMA_Cmd(DMAx: *mut CM_DMA_TypeDef, enNewState: en_functional_state_t);
pub fn DMA_ErrIntCmd(
DMAx: *mut CM_DMA_TypeDef,
u32ErrInt: u32,
enNewState: en_functional_state_t,
);
pub fn DMA_GetErrStatus(DMAx: *const CM_DMA_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn DMA_ClearErrStatus(DMAx: *mut CM_DMA_TypeDef, u32Flag: u32);
pub fn DMA_TransCompleteIntCmd(
DMAx: *mut CM_DMA_TypeDef,
u32TransCompleteInt: u32,
enNewState: en_functional_state_t,
);
pub fn DMA_GetTransCompleteStatus(
DMAx: *const CM_DMA_TypeDef,
u32Flag: u32,
) -> en_flag_status_t;
pub fn DMA_ClearTransCompleteStatus(DMAx: *mut CM_DMA_TypeDef, u32Flag: u32);
pub fn DMA_ChCmd(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, enNewState: en_functional_state_t)
-> i32;
pub fn DMA_GetRequestStatus(DMAx: *const CM_DMA_TypeDef, u32Status: u32) -> en_flag_status_t;
pub fn DMA_GetTransStatus(DMAx: *const CM_DMA_TypeDef, u32Status: u32) -> en_flag_status_t;
pub fn DMA_SetSrcAddr(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Addr: u32) -> i32;
pub fn DMA_SetDestAddr(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Addr: u32) -> i32;
pub fn DMA_SetTransCount(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u16Count: u16) -> i32;
pub fn DMA_SetBlockSize(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u16Size: u16) -> i32;
pub fn DMA_SetDataWidth(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32DataWidth: u32) -> i32;
pub fn DMA_SetSrcRepeatSize(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Size: u32) -> i32;
pub fn DMA_SetDestRepeatSize(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Size: u32) -> i32;
pub fn DMA_SetNonSeqSrcCount(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Count: u32) -> i32;
pub fn DMA_SetNonSeqDestCount(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Count: u32) -> i32;
pub fn DMA_SetNonSeqSrcOffset(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Offset: u32) -> i32;
pub fn DMA_SetNonSeqDestOffset(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Offset: u32) -> i32;
pub fn DMA_SetLlpAddr(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, u32Addr: u32);
pub fn DMA_StructInit(pstcDmaInit: *mut stc_dma_init_t) -> i32;
pub fn DMA_Init(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, pstcDmaInit: *const stc_dma_init_t)
-> i32;
pub fn DMA_DeInit(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8);
pub fn DMA_RepeatStructInit(pstcDmaRepeatInit: *mut stc_dma_repeat_init_t) -> i32;
pub fn DMA_RepeatInit(
DMAx: *mut CM_DMA_TypeDef,
u8Ch: u8,
pstcDmaRepeatInit: *const stc_dma_repeat_init_t,
) -> i32;
pub fn DMA_NonSeqStructInit(pstcDmaNonSeqInit: *mut stc_dma_nonseq_init_t) -> i32;
pub fn DMA_NonSeqInit(
DMAx: *mut CM_DMA_TypeDef,
u8Ch: u8,
pstcDmaNonSeqInit: *const stc_dma_nonseq_init_t,
) -> i32;
pub fn DMA_LlpStructInit(pstcDmaLlpInit: *mut stc_dma_llp_init_t) -> i32;
pub fn DMA_LlpInit(
DMAx: *mut CM_DMA_TypeDef,
u8Ch: u8,
pstcDmaLlpInit: *const stc_dma_llp_init_t,
) -> i32;
pub fn DMA_LlpCmd(DMAx: *mut CM_DMA_TypeDef, u8Ch: u8, enNewState: en_functional_state_t);
pub fn DMA_ReconfigStructInit(pstcDmaRCInit: *mut stc_dma_reconfig_init_t) -> i32;
pub fn DMA_ReconfigInit(
DMAx: *mut CM_DMA_TypeDef,
u8Ch: u8,
pstcDmaRCInit: *const stc_dma_reconfig_init_t,
) -> i32;
pub fn DMA_ReconfigCmd(DMAx: *mut CM_DMA_TypeDef, enNewState: en_functional_state_t);
pub fn DMA_ReconfigLlpCmd(
DMAx: *mut CM_DMA_TypeDef,
u8Ch: u8,
enNewState: en_functional_state_t,
);
pub fn DMA_ReconfigNonSeqStructInit(pstcDmaRcNonSeqInit: *mut stc_dma_rc_nonseq_init_t) -> i32;
pub fn DMA_ReconfigNonSeqInit(
DMAx: *mut CM_DMA_TypeDef,
u8Ch: u8,
pstcDmaRcNonSeqInit: *const stc_dma_rc_nonseq_init_t,
) -> i32;
pub fn DMA_GetSrcAddr(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetDestAddr(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetTransCount(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetBlockSize(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetSrcRepeatSize(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetDestRepeatSize(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetNonSeqSrcCount(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetNonSeqDestCount(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetNonSeqSrcOffset(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_GetNonSeqDestOffset(DMAx: *const CM_DMA_TypeDef, u8Ch: u8) -> u32;
pub fn DMA_MxChSWTrigger(DMAx: *mut CM_DMA_TypeDef, u8MxCh: u8);
pub fn DMA_SWReconfig(DMAx: *mut CM_DMA_TypeDef);
pub fn EFM_Cmd(u32Flash: u32, enNewState: en_functional_state_t);
pub fn EFM_FWMC_Cmd(enNewState: en_functional_state_t);
pub fn EFM_SetBusStatus(u32Status: u32);
pub fn EFM_IntCmd(u32EfmInt: u32, enNewState: en_functional_state_t);
pub fn EFM_ClearStatus(u32Flag: u32);
pub fn EFM_SetWaitCycle(u32WaitCycle: u32) -> i32;
pub fn EFM_SetOperateMode(u32Mode: u32) -> i32;
pub fn EFM_ReadByte(u32Addr: u32, pu8ReadBuf: *mut u8, u32ByteLen: u32) -> i32;
pub fn EFM_Program(u32Addr: u32, pu8Buf: *const u8, u32Len: u32) -> i32;
pub fn EFM_SequenceProgram(u32Addr: u32, pu8Buf: *const u8, u32Len: u32) -> i32;
pub fn EFM_ProgramWord(u32Addr: u32, u32Data: u32) -> i32;
pub fn EFM_ProgramWordReadBack(u32Addr: u32, u32Data: u32) -> i32;
pub fn EFM_ChipErase(u8Chip: u8) -> i32;
pub fn EFM_SectorErase(u32Addr: u32) -> i32;
pub fn EFM_GetAnyStatus(u32Flag: u32) -> en_flag_status_t;
pub fn EFM_GetStatus(u32Flag: u32) -> en_flag_status_t;
pub fn EFM_GetUID(pstcUID: *mut stc_efm_unique_id_t);
pub fn EFM_CacheRamReset(enNewState: en_functional_state_t);
pub fn EFM_CacheCmd(enNewState: en_functional_state_t);
pub fn EFM_LowVoltageReadCmd(enNewState: en_functional_state_t);
pub fn EFM_SwapCmd(enNewState: en_functional_state_t) -> i32;
pub fn EFM_GetSwapStatus() -> en_flag_status_t;
pub fn EFM_OTP_Lock(u32Addr: u32) -> i32;
pub fn EFM_REMAP_StructInit(pstcEfmRemapInit: *mut stc_efm_remap_init_t) -> i32;
pub fn EFM_REMAP_Init(u8RemapIdx: u8, pstcEfmRemapInit: *mut stc_efm_remap_init_t) -> i32;
pub fn EFM_REMAP_DeInit();
pub fn EFM_REMAP_Cmd(u8RemapIdx: u8, enNewState: en_functional_state_t);
pub fn EFM_REMAP_SetAddr(u8RemapIdx: u8, u32Addr: u32);
pub fn EFM_REMAP_SetSize(u8RemapIdx: u8, u32Size: u32);
pub fn EFM_LowVoltageCmd(enNewState: en_functional_state_t);
pub fn EFM_SetWindowProtectAddr(u32StartAddr: u32, u32EndAddr: u32);
pub fn EFM_Protect_Enable(u8Level: u8);
pub fn EFM_WriteSecurityCode(pu8Buf: *const u8, u32Len: u32) -> i32;
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup EMB_Global_Functions\n @{"]
pub fn EMB_TMR4_StructInit(pstcEmbInit: *mut stc_emb_tmr4_init_t) -> i32;
pub fn EMB_TMR4_Init(EMBx: *mut CM_EMB_TypeDef, pstcEmbInit: *const stc_emb_tmr4_init_t)
-> i32;
pub fn EMB_TMR6_StructInit(pstcEmbInit: *mut stc_emb_tmr6_init_t) -> i32;
pub fn EMB_TMR6_Init(EMBx: *mut CM_EMB_TypeDef, pstcEmbInit: *const stc_emb_tmr6_init_t)
-> i32;
pub fn EMB_DeInit(EMBx: *mut CM_EMB_TypeDef);
pub fn EMB_IntCmd(
EMBx: *mut CM_EMB_TypeDef,
u32IntType: u32,
enNewState: en_functional_state_t,
);
pub fn EMB_ClearStatus(EMBx: *mut CM_EMB_TypeDef, u32Flag: u32);
pub fn EMB_GetStatus(EMBx: *const CM_EMB_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn EMB_SWBrake(EMBx: *mut CM_EMB_TypeDef, enNewState: en_functional_state_t);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup EP_Global_Functions\n @{"]
pub fn EP_DeInit();
pub fn EP_StructInit(pstcEventPortInit: *mut stc_ep_init_t) -> i32;
pub fn EP_Init(
u8EventPort: u8,
u16EventPin: u16,
pstcEventPortInit: *const stc_ep_init_t,
) -> i32;
pub fn EP_SetTriggerEdge(u8EventPort: u8, u16EventPin: u16, u32Edge: u32) -> i32;
pub fn EP_SetTriggerOps(u8EventPort: u8, u16EventPin: u16, u32Ops: u32) -> i32;
pub fn EP_ReadInputPins(u8EventPort: u8, u16EventPin: u16) -> en_ep_state_t;
pub fn EP_ReadInputPort(u8EventPort: u8) -> u16;
pub fn EP_ReadOutputPins(u8EventPort: u8, u16EventPin: u16) -> en_ep_state_t;
pub fn EP_ReadOutputPort(u8EventPort: u8) -> u16;
pub fn EP_SetPins(u8EventPort: u8, u16EventPin: u16);
pub fn EP_ResetPins(u8EventPort: u8, u16EventPin: u16);
pub fn EP_SetDir(u8EventPort: u8, u16EventPin: u16, u32Dir: u32);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup FCG_Global_Functions\n @{"]
pub fn FCG_Fcg0PeriphClockCmd(u32Fcg0Periph: u32, enNewState: en_functional_state_t);
pub fn FCG_Fcg1PeriphClockCmd(u32Fcg1Periph: u32, enNewState: en_functional_state_t);
pub fn FCG_Fcg2PeriphClockCmd(u32Fcg2Periph: u32, enNewState: en_functional_state_t);
pub fn FCG_Fcg3PeriphClockCmd(u32Fcg3Periph: u32, enNewState: en_functional_state_t);
pub fn FCM_Init(FCMx: *mut CM_FCM_TypeDef, pstcFcmInit: *const stc_fcm_init_t) -> i32;
pub fn FCM_StructInit(pstcFcmInit: *mut stc_fcm_init_t) -> i32;
pub fn FCM_DeInit(FCMx: *mut CM_FCM_TypeDef) -> i32;
pub fn FCM_GetCountValue(FCMx: *mut CM_FCM_TypeDef) -> u16;
pub fn FCM_SetTargetClock(FCMx: *mut CM_FCM_TypeDef, u32ClockSrc: u32, u32Div: u32);
pub fn FCM_SetRefClock(FCMx: *mut CM_FCM_TypeDef, u32ClockSrc: u32, u32Div: u32);
pub fn FCM_GetStatus(FCMx: *mut CM_FCM_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn FCM_ClearStatus(FCMx: *mut CM_FCM_TypeDef, u32Flag: u32);
pub fn FCM_ResetCmd(FCMx: *mut CM_FCM_TypeDef, enNewState: en_functional_state_t);
pub fn FCM_IntCmd(
FCMx: *mut CM_FCM_TypeDef,
u32IntType: u32,
enNewState: en_functional_state_t,
);
pub fn FCM_Cmd(FCMx: *mut CM_FCM_TypeDef, enNewState: en_functional_state_t);
pub fn GPIO_Init(u8Port: u8, u16Pin: u16, pstcGpioInit: *const stc_gpio_init_t) -> i32;
pub fn GPIO_DeInit();
pub fn GPIO_StructInit(pstcGpioInit: *mut stc_gpio_init_t) -> i32;
pub fn GPIO_SetDebugPort(u8DebugPort: u8, enNewState: en_functional_state_t);
pub fn GPIO_SetFunc(u8Port: u8, u16Pin: u16, u16Func: u16);
pub fn GPIO_SubFuncCmd(u8Port: u8, u16Pin: u16, enNewState: en_functional_state_t);
pub fn GPIO_SetSubFunc(u8Func: u8);
pub fn GPIO_SetReadWaitCycle(u16ReadWait: u16);
pub fn GPIO_InputMOSCmd(u8Port: u8, enNewState: en_functional_state_t);
pub fn GPIO_OutputCmd(u8Port: u8, u16Pin: u16, enNewState: en_functional_state_t);
pub fn GPIO_ReadInputPins(u8Port: u8, u16Pin: u16) -> en_pin_state_t;
pub fn GPIO_ReadInputPort(u8Port: u8) -> u16;
pub fn GPIO_ReadOutputPins(u8Port: u8, u16Pin: u16) -> en_pin_state_t;
pub fn GPIO_ReadOutputPort(u8Port: u8) -> u16;
pub fn GPIO_SetPins(u8Port: u8, u16Pin: u16);
pub fn GPIO_ResetPins(u8Port: u8, u16Pin: u16);
pub fn GPIO_WritePort(u8Port: u8, u16PortVal: u16);
pub fn GPIO_TogglePins(u8Port: u8, u16Pin: u16);
pub fn GPIO_ExtIntCmd(u8Port: u8, u16Pin: u16, enNewState: en_functional_state_t);
pub fn GPIO_AnalogCmd(u8Port: u8, u16Pin: u16, enNewState: en_functional_state_t);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup HASH_Global_Functions\n @{"]
pub fn HASH_DeInit() -> i32;
pub fn HASH_Calculate(pu8SrcData: *const u8, u32SrcDataSize: u32, pu8MsgDigest: *mut u8)
-> i32;
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup I2C_Global_Functions\n @{"]
pub fn I2C_StructInit(pstcI2cInit: *mut stc_i2c_init_t) -> i32;
pub fn I2C_BaudrateConfig(
I2Cx: *mut CM_I2C_TypeDef,
pstcI2cInit: *const stc_i2c_init_t,
pf32Error: *mut float32_t,
) -> i32;
pub fn I2C_DeInit(I2Cx: *mut CM_I2C_TypeDef) -> i32;
pub fn I2C_Init(
I2Cx: *mut CM_I2C_TypeDef,
pstcI2cInit: *const stc_i2c_init_t,
pf32Error: *mut float32_t,
) -> i32;
pub fn I2C_SlaveAddrConfig(
I2Cx: *mut CM_I2C_TypeDef,
u32AddrNum: u32,
u32AddrMode: u32,
u32Addr: u32,
);
pub fn I2C_SlaveAddrCmd(
I2Cx: *mut CM_I2C_TypeDef,
u32AddrNum: u32,
enNewState: en_functional_state_t,
);
pub fn I2C_Cmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
pub fn I2C_FastAckCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
pub fn I2C_BusWaitCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
pub fn I2C_SmbusConfig(
I2Cx: *mut CM_I2C_TypeDef,
u32SmbusConfig: u32,
enNewState: en_functional_state_t,
);
pub fn I2C_SmbusCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
pub fn I2C_DigitalFilterConfig(I2Cx: *mut CM_I2C_TypeDef, u32FilterClock: u32);
pub fn I2C_DigitalFilterCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
pub fn I2C_AnalogFilterCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
pub fn I2C_GeneralCallCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
pub fn I2C_SWResetCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
pub fn I2C_IntCmd(
I2Cx: *mut CM_I2C_TypeDef,
u32IntType: u32,
enNewState: en_functional_state_t,
);
pub fn I2C_GenerateStart(I2Cx: *mut CM_I2C_TypeDef);
pub fn I2C_GenerateRestart(I2Cx: *mut CM_I2C_TypeDef);
pub fn I2C_GenerateStop(I2Cx: *mut CM_I2C_TypeDef);
pub fn I2C_GetStatus(I2Cx: *const CM_I2C_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn I2C_ClearStatus(I2Cx: *mut CM_I2C_TypeDef, u32Flag: u32);
pub fn I2C_WriteData(I2Cx: *mut CM_I2C_TypeDef, u8Data: u8);
pub fn I2C_ReadData(I2Cx: *const CM_I2C_TypeDef) -> u8;
pub fn I2C_AckConfig(I2Cx: *mut CM_I2C_TypeDef, u32AckConfig: u32);
pub fn I2C_SCLHighTimeoutConfig(I2Cx: *mut CM_I2C_TypeDef, u16TimeoutH: u16);
pub fn I2C_SCLLowTimeoutConfig(I2Cx: *mut CM_I2C_TypeDef, u16TimeoutL: u16);
pub fn I2C_SCLHighTimeoutCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
pub fn I2C_SCLLowTimeoutCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
pub fn I2C_SCLTimeoutCmd(I2Cx: *mut CM_I2C_TypeDef, enNewState: en_functional_state_t);
pub fn I2C_Start(I2Cx: *mut CM_I2C_TypeDef, u32Timeout: u32) -> i32;
pub fn I2C_Restart(I2Cx: *mut CM_I2C_TypeDef, u32Timeout: u32) -> i32;
pub fn I2C_TransAddr(
I2Cx: *mut CM_I2C_TypeDef,
u16Addr: u16,
u8Dir: u8,
u32Timeout: u32,
) -> i32;
pub fn I2C_Trans10BitAddr(
I2Cx: *mut CM_I2C_TypeDef,
u16Addr: u16,
u8Dir: u8,
u32Timeout: u32,
) -> i32;
pub fn I2C_TransData(
I2Cx: *mut CM_I2C_TypeDef,
au8TxData: *const u8,
u32Size: u32,
u32Timeout: u32,
) -> i32;
pub fn I2C_ReceiveData(
I2Cx: *mut CM_I2C_TypeDef,
au8RxData: *mut u8,
u32Size: u32,
u32Timeout: u32,
) -> i32;
pub fn I2C_MasterReceiveDataAndStop(
I2Cx: *mut CM_I2C_TypeDef,
au8RxData: *mut u8,
u32Size: u32,
u32Timeout: u32,
) -> i32;
pub fn I2C_Stop(I2Cx: *mut CM_I2C_TypeDef, u32Timeout: u32) -> i32;
pub fn I2C_WaitStatus(
I2Cx: *const CM_I2C_TypeDef,
u32Flag: u32,
enStatus: en_flag_status_t,
u32Timeout: u32,
) -> i32;
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup I2S_Global_Functions\n @{"]
pub fn I2S_DeInit(I2Sx: *mut CM_I2S_TypeDef) -> i32;
pub fn I2S_Init(I2Sx: *mut CM_I2S_TypeDef, pstcI2sInit: *const stc_i2s_init_t) -> i32;
pub fn I2S_StructInit(pstcI2sInit: *mut stc_i2s_init_t) -> i32;
pub fn I2S_SWReset(I2Sx: *mut CM_I2S_TypeDef, u32Type: u32);
pub fn I2S_SetTransMode(I2Sx: *mut CM_I2S_TypeDef, u32Mode: u32);
pub fn I2S_SetTransFIFOLevel(I2Sx: *mut CM_I2S_TypeDef, u32Level: u32);
pub fn I2S_SetReceiveFIFOLevel(I2Sx: *mut CM_I2S_TypeDef, u32Level: u32);
pub fn I2S_SetProtocol(I2Sx: *mut CM_I2S_TypeDef, u32Protocol: u32);
pub fn I2S_SetAudioFreq(I2Sx: *mut CM_I2S_TypeDef, u32Freq: u32) -> i32;
pub fn I2S_MCKOutputCmd(I2Sx: *mut CM_I2S_TypeDef, enNewState: en_functional_state_t);
pub fn I2S_FuncCmd(I2Sx: *mut CM_I2S_TypeDef, u32Func: u32, enNewState: en_functional_state_t);
pub fn I2S_WriteData(I2Sx: *mut CM_I2S_TypeDef, u32Data: u32);
pub fn I2S_ReadData(I2Sx: *const CM_I2S_TypeDef) -> u32;
pub fn I2S_Trans(
I2Sx: *mut CM_I2S_TypeDef,
pvTxBuf: *const ::core::ffi::c_void,
u32Len: u32,
u32Timeout: u32,
) -> i32;
pub fn I2S_Receive(
I2Sx: *const CM_I2S_TypeDef,
pvRxBuf: *mut ::core::ffi::c_void,
u32Len: u32,
u32Timeout: u32,
) -> i32;
pub fn I2S_TransReceive(
I2Sx: *mut CM_I2S_TypeDef,
pvTxBuf: *const ::core::ffi::c_void,
pvRxBuf: *mut ::core::ffi::c_void,
u32Len: u32,
u32Timeout: u32,
) -> i32;
pub fn I2S_IntCmd(
I2Sx: *mut CM_I2S_TypeDef,
u32IntType: u32,
enNewState: en_functional_state_t,
);
pub fn I2S_GetStatus(I2Sx: *const CM_I2S_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn I2S_ClearStatus(I2Sx: *mut CM_I2S_TypeDef, u32Flag: u32);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup INTC_Global_Functions\n @{"]
pub fn INTC_IrqSignIn(pstcIrqSignConfig: *const stc_irq_signin_config_t) -> i32;
pub fn INTC_IrqSignOut(enIRQn: IRQn_Type) -> i32;
pub fn INTC_WakeupSrcCmd(u32WakeupSrc: u32, enNewState: en_functional_state_t);
pub fn INTC_EventCmd(u32Event: u32, enNewState: en_functional_state_t);
pub fn INTC_IntCmd(u32Int: u32, enNewState: en_functional_state_t);
pub fn INTC_SWIntInit(u32Ch: u32, pfnCallback: func_ptr_t, u32Priority: u32);
pub fn INTC_SWIntCmd(u32SWInt: u32, enNewState: en_functional_state_t);
pub fn NMI_Init(pstcNmiInit: *const stc_nmi_init_t) -> i32;
pub fn NMI_StructInit(pstcNmiInit: *mut stc_nmi_init_t) -> i32;
pub fn NMI_GetNmiStatus(u32Src: u32) -> en_flag_status_t;
pub fn NMI_NmiSrcCmd(u32Src: u32, enNewState: en_functional_state_t);
pub fn NMI_ClearNmiStatus(u32Src: u32);
pub fn EXTINT_Init(u32Ch: u32, pstcExtIntInit: *const stc_extint_init_t) -> i32;
pub fn EXTINT_StructInit(pstcExtIntInit: *mut stc_extint_init_t) -> i32;
pub fn EXTINT_GetExtIntStatus(u32ExtIntCh: u32) -> en_flag_status_t;
pub fn EXTINT_ClearExtIntStatus(u32ExtIntCh: u32);
pub fn IRQ000_Handler();
pub fn IRQ001_Handler();
pub fn IRQ002_Handler();
pub fn IRQ003_Handler();
pub fn IRQ004_Handler();
pub fn IRQ005_Handler();
pub fn IRQ006_Handler();
pub fn IRQ007_Handler();
pub fn IRQ008_Handler();
pub fn IRQ009_Handler();
pub fn IRQ010_Handler();
pub fn IRQ011_Handler();
pub fn IRQ012_Handler();
pub fn IRQ013_Handler();
pub fn IRQ014_Handler();
pub fn IRQ015_Handler();
pub fn IRQ016_Handler();
pub fn IRQ017_Handler();
pub fn IRQ018_Handler();
pub fn IRQ019_Handler();
pub fn IRQ020_Handler();
pub fn IRQ021_Handler();
pub fn IRQ022_Handler();
pub fn IRQ023_Handler();
pub fn IRQ024_Handler();
pub fn IRQ025_Handler();
pub fn IRQ026_Handler();
pub fn IRQ027_Handler();
pub fn IRQ028_Handler();
pub fn IRQ029_Handler();
pub fn IRQ030_Handler();
pub fn IRQ031_Handler();
pub fn IRQ032_Handler();
pub fn IRQ033_Handler();
pub fn IRQ034_Handler();
pub fn IRQ035_Handler();
pub fn IRQ036_Handler();
pub fn IRQ037_Handler();
pub fn IRQ038_Handler();
pub fn IRQ039_Handler();
pub fn IRQ040_Handler();
pub fn IRQ041_Handler();
pub fn IRQ042_Handler();
pub fn IRQ043_Handler();
pub fn IRQ044_Handler();
pub fn IRQ045_Handler();
pub fn IRQ046_Handler();
pub fn IRQ047_Handler();
pub fn IRQ048_Handler();
pub fn IRQ049_Handler();
pub fn IRQ050_Handler();
pub fn IRQ051_Handler();
pub fn IRQ052_Handler();
pub fn IRQ053_Handler();
pub fn IRQ054_Handler();
pub fn IRQ055_Handler();
pub fn IRQ056_Handler();
pub fn IRQ057_Handler();
pub fn IRQ058_Handler();
pub fn IRQ059_Handler();
pub fn IRQ060_Handler();
pub fn IRQ061_Handler();
pub fn IRQ062_Handler();
pub fn IRQ063_Handler();
pub fn IRQ064_Handler();
pub fn IRQ065_Handler();
pub fn IRQ066_Handler();
pub fn IRQ067_Handler();
pub fn IRQ068_Handler();
pub fn IRQ069_Handler();
pub fn IRQ070_Handler();
pub fn IRQ071_Handler();
pub fn IRQ072_Handler();
pub fn IRQ073_Handler();
pub fn IRQ074_Handler();
pub fn IRQ075_Handler();
pub fn IRQ076_Handler();
pub fn IRQ077_Handler();
pub fn IRQ078_Handler();
pub fn IRQ079_Handler();
pub fn IRQ080_Handler();
pub fn IRQ081_Handler();
pub fn IRQ082_Handler();
pub fn IRQ083_Handler();
pub fn IRQ084_Handler();
pub fn IRQ085_Handler();
pub fn IRQ086_Handler();
pub fn IRQ087_Handler();
pub fn IRQ088_Handler();
pub fn IRQ089_Handler();
pub fn IRQ090_Handler();
pub fn IRQ091_Handler();
pub fn IRQ092_Handler();
pub fn IRQ093_Handler();
pub fn IRQ094_Handler();
pub fn IRQ095_Handler();
pub fn IRQ096_Handler();
pub fn IRQ097_Handler();
pub fn IRQ098_Handler();
pub fn IRQ099_Handler();
pub fn IRQ100_Handler();
pub fn IRQ101_Handler();
pub fn IRQ102_Handler();
pub fn IRQ103_Handler();
pub fn IRQ104_Handler();
pub fn IRQ105_Handler();
pub fn IRQ106_Handler();
pub fn IRQ107_Handler();
pub fn IRQ108_Handler();
pub fn IRQ109_Handler();
pub fn IRQ110_Handler();
pub fn IRQ111_Handler();
pub fn IRQ112_Handler();
pub fn IRQ113_Handler();
pub fn IRQ114_Handler();
pub fn IRQ115_Handler();
pub fn IRQ116_Handler();
pub fn IRQ117_Handler();
pub fn IRQ118_Handler();
pub fn IRQ119_Handler();
pub fn IRQ120_Handler();
pub fn IRQ121_Handler();
pub fn IRQ122_Handler();
pub fn IRQ123_Handler();
pub fn IRQ124_Handler();
pub fn IRQ125_Handler();
pub fn IRQ126_Handler();
pub fn IRQ127_Handler();
pub fn KEYSCAN_StructInit(pstcKeyscanInit: *mut stc_keyscan_init_t) -> i32;
pub fn KEYSCAN_Init(pstcKeyscanInit: *const stc_keyscan_init_t) -> i32;
pub fn KEYSCAN_Cmd(enNewState: en_functional_state_t);
pub fn KEYSCAN_DeInit() -> i32;
pub fn MPU_DeInit();
pub fn MPU_Init(pstcMpuInit: *const stc_mpu_init_t) -> i32;
pub fn MPU_StructInit(pstcMpuInit: *mut stc_mpu_init_t) -> i32;
pub fn MPU_UnitInit(u32Unit: u32, pstcUnitInit: *mut stc_mpu_unit_init_t) -> i32;
pub fn MPU_UnitStructInit(pstcUnitInit: *mut stc_mpu_unit_init_t) -> i32;
pub fn MPU_SetExceptionType(u32Unit: u32, u32Type: u32);
pub fn MPU_BackgroundWriteCmd(u32Unit: u32, enNewState: en_functional_state_t);
pub fn MPU_BackgroundReadCmd(u32Unit: u32, enNewState: en_functional_state_t);
pub fn MPU_UnitCmd(u32Unit: u32, enNewState: en_functional_state_t);
pub fn MPU_GetStatus(u32Flag: u32) -> en_flag_status_t;
pub fn MPU_ClearStatus(u32Flag: u32);
pub fn MPU_RegionInit(u32Num: u32, pstcRegionInit: *const stc_mpu_region_init_t) -> i32;
pub fn MPU_RegionStructInit(pstcRegionInit: *mut stc_mpu_region_init_t) -> i32;
pub fn MPU_SetRegionBaseAddr(u32Num: u32, u32Addr: u32);
pub fn MPU_SetRegionSize(u32Num: u32, u32Size: u32);
pub fn MPU_RegionWriteCmd(u32Num: u32, u32Unit: u32, enNewState: en_functional_state_t);
pub fn MPU_RegionReadCmd(u32Num: u32, u32Unit: u32, enNewState: en_functional_state_t);
pub fn MPU_RegionCmd(u32Num: u32, u32Unit: u32, enNewState: en_functional_state_t);
pub fn MPU_IP_SetExceptionType(u32Type: u32);
pub fn MPU_IP_WriteCmd(u32Periph: u32, enNewState: en_functional_state_t);
pub fn MPU_IP_ReadCmd(u32Periph: u32, enNewState: en_functional_state_t);
pub fn OTS_Init(pstcOTSInit: *const stc_ots_init_t) -> i32;
pub fn OTS_StructInit(pstcOTSInit: *mut stc_ots_init_t) -> i32;
pub fn OTS_DeInit() -> i32;
pub fn OTS_Polling(pf32Temp: *mut float32_t, u32Timeout: u32) -> i32;
pub fn OTS_IntCmd(enNewState: en_functional_state_t);
pub fn OTS_ScalingExperiment(
pu16Dr1: *mut u16,
pu16Dr2: *mut u16,
pu16Ecr: *mut u16,
pf32A: *mut float32_t,
u32Timeout: u32,
) -> i32;
pub fn OTS_CalculateTemp() -> float32_t;
pub fn PWC_PD_Enter() -> i32;
pub fn PWC_PD_StructInit(pstcPDModeConfig: *mut stc_pwc_pd_mode_config_t) -> i32;
pub fn PWC_PD_Config(pstcPDModeConfig: *const stc_pwc_pd_mode_config_t) -> i32;
pub fn PWC_PD_SetIoState(u8IoState: u8);
pub fn PWC_PD_SetMode(u8PdMode: u8);
pub fn PWC_PD_WakeupCmd(u32Event: u32, enNewState: en_functional_state_t);
pub fn PWC_PD_SetWakeupTriggerEdge(u8Event: u8, u8TrigEdge: u8);
pub fn PWC_PD_GetWakeupStatus(u16Flag: u16) -> en_flag_status_t;
pub fn PWC_PD_ClearWakeupStatus(u16Flag: u16);
pub fn PWC_PD_PeriphRamCmd(u32PeriphRam: u32, enNewState: en_functional_state_t);
pub fn PWC_PD_VdrCmd(enNewState: en_functional_state_t);
pub fn PWC_WKT_Config(u16ClkSrc: u16, u16CmpVal: u16);
pub fn PWC_WKT_SetCompareValue(u16CmpVal: u16);
pub fn PWC_WKT_GetCompareValue() -> u16;
pub fn PWC_WKT_Cmd(enNewState: en_functional_state_t);
pub fn PWC_WKT_GetStatus() -> en_flag_status_t;
pub fn PWC_WKT_ClearStatus();
pub fn PWC_RamModeConfig(u16Mode: u16);
pub fn PWC_SLEEP_Enter(u8SleepType: u8);
pub fn PWC_STOP_Enter(u8StopType: u8);
pub fn PWC_STOP_StructInit(pstcStopConfig: *mut stc_pwc_stop_mode_config_t) -> i32;
pub fn PWC_STOP_Config(pstcStopConfig: *const stc_pwc_stop_mode_config_t) -> i32;
pub fn PWC_STOP_ClockSelect(u8Clock: u8);
pub fn PWC_STOP_NvicBackup();
pub fn PWC_STOP_NvicRecover();
pub fn PWC_STOP_ClockBackup();
pub fn PWC_STOP_ClockRecover();
pub fn PWC_STOP_IrqClockBackup();
pub fn PWC_STOP_IrqClockRecover();
pub fn PWC_STOP_SetDrv(u8StopDrv: u8);
pub fn PWC_STOP_FlashWaitCmd(enNewState: en_functional_state_t);
pub fn PWC_HighSpeedToLowSpeed() -> i32;
pub fn PWC_LowSpeedToHighSpeed() -> i32;
pub fn PWC_HighSpeedToHighPerformance() -> i32;
pub fn PWC_HighPerformanceToHighSpeed() -> i32;
pub fn PWC_LowSpeedToHighPerformance() -> i32;
pub fn PWC_HighPerformanceToLowSpeed() -> i32;
pub fn PWC_LDO_Cmd(u16Ldo: u16, enNewState: en_functional_state_t);
pub fn PWC_LVD_Init(u8Ch: u8, pstcLvdInit: *const stc_pwc_lvd_init_t) -> i32;
pub fn PWC_LVD_DeInit(u8Ch: u8);
pub fn PWC_LVD_StructInit(pstcLvdInit: *mut stc_pwc_lvd_init_t) -> i32;
pub fn PWC_LVD_Cmd(u8Ch: u8, enNewState: en_functional_state_t);
pub fn PWC_LVD_ExtInputCmd(enNewState: en_functional_state_t);
pub fn PWC_LVD_CompareOutputCmd(u8Ch: u8, enNewState: en_functional_state_t);
pub fn PWC_LVD_DigitalFilterCmd(u8Ch: u8, enNewState: en_functional_state_t);
pub fn PWC_LVD_SetFilterClock(u8Ch: u8, u32Clock: u32);
pub fn PWC_LVD_SetThresholdVoltage(u8Ch: u8, u32Voltage: u32);
pub fn PWC_LVD_ClearStatus(u8Flag: u8);
pub fn PWC_LVD_GetStatus(u8Flag: u8) -> en_flag_status_t;
pub fn PWC_PowerMonitorCmd(enNewState: en_functional_state_t);
pub fn PWC_XTAL32_PowerCmd(enNewState: en_functional_state_t);
pub fn PWC_RetSram_PowerCmd(enNewState: en_functional_state_t);
pub fn QSPI_DeInit() -> i32;
pub fn QSPI_Init(pstcQspiInit: *const stc_qspi_init_t) -> i32;
pub fn QSPI_StructInit(pstcQspiInit: *mut stc_qspi_init_t) -> i32;
pub fn QSPI_SetWpPinLevel(u32Level: u32);
pub fn QSPI_SetPrefetchMode(u32Mode: u32);
pub fn QSPI_SelectMemoryBlock(u8Block: u8);
pub fn QSPI_SetReadMode(u32Mode: u32);
pub fn QSPI_CustomReadConfig(pstcCustomMode: *const stc_qspi_custom_mode_t) -> i32;
pub fn QSPI_XipModeCmd(u8ModeCode: u8, enNewState: en_functional_state_t);
pub fn QSPI_EnterDirectCommMode();
pub fn QSPI_ExitDirectCommMode();
pub fn QSPI_GetPrefetchBufSize() -> u8;
pub fn QSPI_GetStatus(u32Flag: u32) -> en_flag_status_t;
pub fn QSPI_ClearStatus(u32Flag: u32);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup RMU_Global_Functions\n @{"]
pub fn RMU_GetStatus(u32RmuResetCause: u32) -> en_flag_status_t;
pub fn RMU_ClearStatus();
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup RTC_Global_Functions\n @{"]
pub fn RTC_DeInit() -> i32;
pub fn RTC_Init(pstcRtcInit: *const stc_rtc_init_t) -> i32;
pub fn RTC_StructInit(pstcRtcInit: *mut stc_rtc_init_t) -> i32;
pub fn RTC_EnterRwMode() -> i32;
pub fn RTC_ExitRwMode() -> i32;
pub fn RTC_ConfirmLPMCond() -> i32;
pub fn RTC_SetIntPeriod(u8Period: u8);
pub fn RTC_SetClockSrc(u8Src: u8);
pub fn RTC_SetClockCompenValue(u16Value: u16);
pub fn RTC_GetCounterState() -> en_functional_state_t;
pub fn RTC_Cmd(enNewState: en_functional_state_t);
pub fn RTC_LrcCmd(enNewState: en_functional_state_t);
pub fn RTC_OneHzOutputCmd(enNewState: en_functional_state_t);
pub fn RTC_ClockCompenCmd(enNewState: en_functional_state_t);
pub fn RTC_SetDate(u8Format: u8, pstcRtcDate: *mut stc_rtc_date_t) -> i32;
pub fn RTC_GetDate(u8Format: u8, pstcRtcDate: *mut stc_rtc_date_t) -> i32;
pub fn RTC_SetTime(u8Format: u8, pstcRtcTime: *mut stc_rtc_time_t) -> i32;
pub fn RTC_GetTime(u8Format: u8, pstcRtcTime: *mut stc_rtc_time_t) -> i32;
pub fn RTC_SetAlarm(u8Format: u8, pstcRtcAlarm: *mut stc_rtc_alarm_t) -> i32;
pub fn RTC_GetAlarm(u8Format: u8, pstcRtcAlarm: *mut stc_rtc_alarm_t) -> i32;
pub fn RTC_AlarmCmd(enNewState: en_functional_state_t);
pub fn RTC_IntCmd(u32IntType: u32, enNewState: en_functional_state_t);
pub fn RTC_GetStatus(u32Flag: u32) -> en_flag_status_t;
pub fn RTC_ClearStatus(u32Flag: u32);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup SDIOC_Global_Functions\n @{"]
pub fn SDIOC_DeInit(SDIOCx: *mut CM_SDIOC_TypeDef) -> i32;
pub fn SDIOC_Init(SDIOCx: *mut CM_SDIOC_TypeDef, pstcSdiocInit: *const stc_sdioc_init_t)
-> i32;
pub fn SDIOC_StructInit(pstcSdiocInit: *mut stc_sdioc_init_t) -> i32;
pub fn SDIOC_SWReset(SDIOCx: *mut CM_SDIOC_TypeDef, u8Type: u8) -> i32;
pub fn SDIOC_PowerCmd(SDIOCx: *mut CM_SDIOC_TypeDef, enNewState: en_functional_state_t);
pub fn SDIOC_GetPowerState(SDIOCx: *const CM_SDIOC_TypeDef) -> en_functional_state_t;
pub fn SDIOC_GetMode(SDIOCx: *const CM_SDIOC_TypeDef) -> u32;
pub fn SDIOC_ClockCmd(SDIOCx: *mut CM_SDIOC_TypeDef, enNewState: en_functional_state_t);
pub fn SDIOC_SetClockDiv(SDIOCx: *mut CM_SDIOC_TypeDef, u16Div: u16);
pub fn SDIOC_GetOptimumClockDiv(u32ClockFreq: u32, pu16Div: *mut u16) -> i32;
pub fn SDIOC_VerifyClockDiv(u32Mode: u32, u8SpeedMode: u8, u16ClockDiv: u16) -> i32;
pub fn SDIOC_GetInsertStatus(SDIOCx: *const CM_SDIOC_TypeDef) -> en_flag_status_t;
pub fn SDIOC_SetSpeedMode(SDIOCx: *mut CM_SDIOC_TypeDef, u8SpeedMode: u8);
pub fn SDIOC_SetBusWidth(SDIOCx: *mut CM_SDIOC_TypeDef, u8BusWidth: u8);
pub fn SDIOC_SetCardDetectSrc(SDIOCx: *mut CM_SDIOC_TypeDef, u8Src: u8);
pub fn SDIOC_SetCardDetectTestLevel(SDIOCx: *mut CM_SDIOC_TypeDef, u8Level: u8);
pub fn SDIOC_SendCommand(
SDIOCx: *mut CM_SDIOC_TypeDef,
pstcCmdConfig: *const stc_sdioc_cmd_config_t,
) -> i32;
pub fn SDIOC_CommandStructInit(pstcCmdConfig: *mut stc_sdioc_cmd_config_t) -> i32;
pub fn SDIOC_GetResponse(SDIOCx: *mut CM_SDIOC_TypeDef, u8Reg: u8, pu32Value: *mut u32) -> i32;
pub fn SDIOC_ConfigData(
SDIOCx: *mut CM_SDIOC_TypeDef,
pstcDataConfig: *const stc_sdioc_data_config_t,
) -> i32;
pub fn SDIOC_DataStructInit(pstcDataConfig: *mut stc_sdioc_data_config_t) -> i32;
pub fn SDIOC_ReadBuffer(SDIOCx: *mut CM_SDIOC_TypeDef, au8Data: *mut u8, u32Len: u32) -> i32;
pub fn SDIOC_WriteBuffer(SDIOCx: *mut CM_SDIOC_TypeDef, au8Data: *const u8, u32Len: u32)
-> i32;
pub fn SDIOC_BlockGapStopCmd(SDIOCx: *mut CM_SDIOC_TypeDef, enNewState: en_functional_state_t);
pub fn SDIOC_RestartTrans(SDIOCx: *mut CM_SDIOC_TypeDef);
pub fn SDIOC_ReadWaitCmd(SDIOCx: *mut CM_SDIOC_TypeDef, enNewState: en_functional_state_t);
pub fn SDIOC_BlockGapIntCmd(SDIOCx: *mut CM_SDIOC_TypeDef, enNewState: en_functional_state_t);
pub fn SDIOC_IntCmd(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32IntType: u32,
enNewState: en_functional_state_t,
);
pub fn SDIOC_GetIntEnableState(
SDIOCx: *const CM_SDIOC_TypeDef,
u32IntType: u32,
) -> en_functional_state_t;
pub fn SDIOC_IntStatusCmd(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32IntType: u32,
enNewState: en_functional_state_t,
);
pub fn SDIOC_GetIntStatus(SDIOCx: *const CM_SDIOC_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn SDIOC_ClearIntStatus(SDIOCx: *mut CM_SDIOC_TypeDef, u32Flag: u32);
pub fn SDIOC_GetHostStatus(SDIOCx: *const CM_SDIOC_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn SDIOC_GetAutoCmdErrorStatus(
SDIOCx: *const CM_SDIOC_TypeDef,
u16Flag: u16,
) -> en_flag_status_t;
pub fn SDIOC_ForceAutoCmdErrorEvent(SDIOCx: *mut CM_SDIOC_TypeDef, u16Event: u16);
pub fn SDIOC_ForceErrorIntEvent(SDIOCx: *mut CM_SDIOC_TypeDef, u16Event: u16);
pub fn SDMMC_CMD0_GoIdleState(SDIOCx: *mut CM_SDIOC_TypeDef, pu32ErrStatus: *mut u32) -> i32;
pub fn SDMMC_CMD2_AllSendCID(SDIOCx: *mut CM_SDIOC_TypeDef, pu32ErrStatus: *mut u32) -> i32;
pub fn SDMMC_CMD3_SendRelativeAddr(
SDIOCx: *mut CM_SDIOC_TypeDef,
pu16RCA: *mut u16,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD6_SwitchFunc(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32Argument: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD7_SelectDeselectCard(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32RCA: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD8_SendInterfaceCond(
SDIOCx: *mut CM_SDIOC_TypeDef,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD9_SendCSD(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32RCA: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD12_StopTrans(SDIOCx: *mut CM_SDIOC_TypeDef, pu32ErrStatus: *mut u32) -> i32;
pub fn SDMMC_CMD13_SendStatus(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32RCA: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD16_SetBlockLength(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32BlockLen: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD17_ReadSingleBlock(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32ReadAddr: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD18_ReadMultipleBlock(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32ReadAddr: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD24_WriteSingleBlock(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32WriteAddr: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD25_WriteMultipleBlock(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32WriteAddr: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD32_EraseBlockStartAddr(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32StartAddr: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD33_EraseBlockEndAddr(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32EndAddr: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD38_Erase(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32Argument: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD55_AppCmd(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32Argument: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_ACMD6_SetBusWidth(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32BusWidth: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_ACMD13_SendStatus(SDIOCx: *mut CM_SDIOC_TypeDef, pu32ErrStatus: *mut u32) -> i32;
pub fn SDMMC_ACMD41_SendOperateCond(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32Argument: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_ACMD51_SendSCR(SDIOCx: *mut CM_SDIOC_TypeDef, pu32ErrStatus: *mut u32) -> i32;
pub fn SDMMC_CMD1_SendOperateCond(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32Argument: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD35_EraseGroupStartAddr(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32StartAddr: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD36_EraseGroupEndAddr(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32EndAddr: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD5_IOSendOperateCond(
SDIOCx: *mut CM_SDIOC_TypeDef,
u32Argument: u32,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD52_IORwDirect(
SDIOCx: *mut CM_SDIOC_TypeDef,
pstcCmdArg: *const stc_sdio_cmd52_arg_t,
u8In: u8,
pu8Out: *mut u8,
pu32ErrStatus: *mut u32,
) -> i32;
pub fn SDMMC_CMD53_IORwExtended(
SDIOCx: *mut CM_SDIOC_TypeDef,
pstcCmdArg: *const stc_sdio_cmd53_arg_t,
pu32ErrStatus: *mut u32,
) -> i32;
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup SPI_Global_Functions\n @{"]
pub fn SPI_StructInit(pstcSpiInit: *mut stc_spi_init_t) -> i32;
pub fn SPI_Init(SPIx: *mut CM_SPI_TypeDef, pstcSpiInit: *const stc_spi_init_t) -> i32;
pub fn SPI_DeInit(SPIx: *mut CM_SPI_TypeDef) -> i32;
pub fn SPI_IntCmd(
SPIx: *mut CM_SPI_TypeDef,
u32IntType: u32,
enNewState: en_functional_state_t,
);
pub fn SPI_Cmd(SPIx: *mut CM_SPI_TypeDef, enNewState: en_functional_state_t);
pub fn SPI_WriteData(SPIx: *mut CM_SPI_TypeDef, u32Data: u32);
pub fn SPI_ReadData(SPIx: *const CM_SPI_TypeDef) -> u32;
pub fn SPI_GetStatus(SPIx: *const CM_SPI_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn SPI_ClearStatus(SPIx: *mut CM_SPI_TypeDef, u32Flag: u32);
pub fn SPI_SetLoopbackMode(SPIx: *mut CM_SPI_TypeDef, u32Mode: u32);
pub fn SPI_ParityCheckCmd(SPIx: *mut CM_SPI_TypeDef, enNewState: en_functional_state_t);
pub fn SPI_SetSSValidLevel(SPIx: *mut CM_SPI_TypeDef, u32SSPin: u32, u32SSLevel: u32);
pub fn SPI_SetSckPolarity(SPIx: *mut CM_SPI_TypeDef, u32Polarity: u32);
pub fn SPI_SetSckPhase(SPIx: *mut CM_SPI_TypeDef, u32Phase: u32);
pub fn SPI_DelayTimeConfig(
SPIx: *mut CM_SPI_TypeDef,
pstcDelayConfig: *const stc_spi_delay_t,
) -> i32;
pub fn SPI_SSPinSelect(SPIx: *mut CM_SPI_TypeDef, u32SSPin: u32);
pub fn SPI_SetReadBuf(SPIx: *mut CM_SPI_TypeDef, u32ReadBuf: u32);
pub fn SPI_DelayStructInit(pstcDelayConfig: *mut stc_spi_delay_t) -> i32;
pub fn SPI_Trans(
SPIx: *mut CM_SPI_TypeDef,
pvTxBuf: *const ::core::ffi::c_void,
u32TxLen: u32,
u32Timeout: u32,
) -> i32;
pub fn SPI_Receive(
SPIx: *mut CM_SPI_TypeDef,
pvRxBuf: *mut ::core::ffi::c_void,
u32RxLen: u32,
u32Timeout: u32,
) -> i32;
pub fn SPI_TransReceive(
SPIx: *mut CM_SPI_TypeDef,
pvTxBuf: *const ::core::ffi::c_void,
pvRxBuf: *mut ::core::ffi::c_void,
u32Len: u32,
u32Timeout: u32,
) -> i32;
pub fn SRAM_Init();
pub fn SRAM_DeInit();
pub fn SRAM_SetWaitCycle(u32SramSel: u32, u32WriteCycle: u32, u32ReadCycle: u32);
pub fn SRAM_SetEccMode(u32EccSram: u32, u32EccMode: u32);
pub fn SRAM_SetExceptionType(u32CheckSram: u32, u32ExceptionType: u32);
pub fn SRAM_GetStatus(u32Flag: u32) -> en_flag_status_t;
pub fn SRAM_ClearStatus(u32Flag: u32);
pub fn SWDT_FeedDog();
pub fn SWDT_GetStatus(u32Flag: u32) -> en_flag_status_t;
pub fn SWDT_ClearStatus(u32Flag: u32) -> i32;
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup TMR0_Global_Functions\n @{"]
pub fn TMR0_DeInit(TMR0x: *mut CM_TMR0_TypeDef) -> i32;
pub fn TMR0_Init(
TMR0x: *mut CM_TMR0_TypeDef,
u32Ch: u32,
pstcTmr0Init: *const stc_tmr0_init_t,
) -> i32;
pub fn TMR0_StructInit(pstcTmr0Init: *mut stc_tmr0_init_t) -> i32;
pub fn TMR0_Start(TMR0x: *mut CM_TMR0_TypeDef, u32Ch: u32);
pub fn TMR0_Stop(TMR0x: *mut CM_TMR0_TypeDef, u32Ch: u32);
pub fn TMR0_SetCountValue(TMR0x: *mut CM_TMR0_TypeDef, u32Ch: u32, u16Value: u16);
pub fn TMR0_GetCountValue(TMR0x: *const CM_TMR0_TypeDef, u32Ch: u32) -> u16;
pub fn TMR0_SetCompareValue(TMR0x: *mut CM_TMR0_TypeDef, u32Ch: u32, u16Value: u16);
pub fn TMR0_GetCompareValue(TMR0x: *const CM_TMR0_TypeDef, u32Ch: u32) -> u16;
pub fn TMR0_SetClockSrc(TMR0x: *mut CM_TMR0_TypeDef, u32Ch: u32, u32Src: u32);
pub fn TMR0_SetClockDiv(TMR0x: *mut CM_TMR0_TypeDef, u32Ch: u32, u32Div: u32);
pub fn TMR0_SetFunc(TMR0x: *mut CM_TMR0_TypeDef, u32Ch: u32, u32Func: u32);
pub fn TMR0_HWCaptureCondCmd(
TMR0x: *mut CM_TMR0_TypeDef,
u32Ch: u32,
enNewState: en_functional_state_t,
);
pub fn TMR0_HWStartCondCmd(
TMR0x: *mut CM_TMR0_TypeDef,
u32Ch: u32,
enNewState: en_functional_state_t,
);
pub fn TMR0_HWStopCondCmd(
TMR0x: *mut CM_TMR0_TypeDef,
u32Ch: u32,
enNewState: en_functional_state_t,
);
pub fn TMR0_HWClearCondCmd(
TMR0x: *mut CM_TMR0_TypeDef,
u32Ch: u32,
enNewState: en_functional_state_t,
);
pub fn TMR0_IntCmd(
TMR0x: *mut CM_TMR0_TypeDef,
u32IntType: u32,
enNewState: en_functional_state_t,
);
pub fn TMR0_GetStatus(TMR0x: *const CM_TMR0_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn TMR0_ClearStatus(TMR0x: *mut CM_TMR0_TypeDef, u32Flag: u32);
#[doc = " @addtogroup TMR4_Counter_Global_Functions\n @{"]
pub fn TMR4_StructInit(pstcTmr4Init: *mut stc_tmr4_init_t) -> i32;
pub fn TMR4_Init(TMR4x: *mut CM_TMR4_TypeDef, pstcTmr4Init: *const stc_tmr4_init_t) -> i32;
pub fn TMR4_DeInit(TMR4x: *mut CM_TMR4_TypeDef) -> i32;
pub fn TMR4_SetClockSrc(TMR4x: *mut CM_TMR4_TypeDef, u16Src: u16);
pub fn TMR4_SetClockDiv(TMR4x: *mut CM_TMR4_TypeDef, u16Div: u16);
pub fn TMR4_SetCountMode(TMR4x: *mut CM_TMR4_TypeDef, u16Mode: u16);
pub fn TMR4_GetPeriodValue(TMR4x: *const CM_TMR4_TypeDef) -> u16;
pub fn TMR4_SetPeriodValue(TMR4x: *mut CM_TMR4_TypeDef, u16Value: u16);
pub fn TMR4_GetCountValue(TMR4x: *const CM_TMR4_TypeDef) -> u16;
pub fn TMR4_SetCountValue(TMR4x: *mut CM_TMR4_TypeDef, u16Value: u16);
pub fn TMR4_ClearCountValue(TMR4x: *mut CM_TMR4_TypeDef);
pub fn TMR4_Start(TMR4x: *mut CM_TMR4_TypeDef);
pub fn TMR4_Stop(TMR4x: *mut CM_TMR4_TypeDef);
pub fn TMR4_ClearStatus(TMR4x: *mut CM_TMR4_TypeDef, u32Flag: u32);
pub fn TMR4_GetStatus(TMR4x: *const CM_TMR4_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn TMR4_IntCmd(
TMR4x: *mut CM_TMR4_TypeDef,
u32IntType: u32,
enNewState: en_functional_state_t,
);
pub fn TMR4_PeriodBufCmd(TMR4x: *mut CM_TMR4_TypeDef, enNewState: en_functional_state_t);
pub fn TMR4_GetCountIntMaskTime(TMR4x: *const CM_TMR4_TypeDef, u32IntType: u32) -> u16;
pub fn TMR4_SetCountIntMaskTime(TMR4x: *mut CM_TMR4_TypeDef, u32IntType: u32, u16MaskTime: u16);
pub fn TMR4_GetCurrentCountIntMaskTime(TMR4x: *const CM_TMR4_TypeDef, u32IntType: u32) -> u16;
#[doc = " @addtogroup TMR4_Output_Compare_Global_Functions\n @{"]
pub fn TMR4_OC_StructInit(pstcTmr4OcInit: *mut stc_tmr4_oc_init_t) -> i32;
pub fn TMR4_OC_Init(
TMR4x: *mut CM_TMR4_TypeDef,
u32Ch: u32,
pstcTmr4OcInit: *const stc_tmr4_oc_init_t,
) -> i32;
pub fn TMR4_OC_DeInit(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32);
pub fn TMR4_OC_GetCompareValue(TMR4x: *const CM_TMR4_TypeDef, u32Ch: u32) -> u16;
pub fn TMR4_OC_SetCompareValue(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32, u16Value: u16);
pub fn TMR4_OC_Cmd(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32, enNewState: en_functional_state_t);
pub fn TMR4_OC_ExtendControlCmd(
TMR4x: *mut CM_TMR4_TypeDef,
u32Ch: u32,
enNewState: en_functional_state_t,
);
pub fn TMR4_OC_BufIntervalResponseCmd(
TMR4x: *mut CM_TMR4_TypeDef,
u32Ch: u32,
u16Object: u16,
enNewState: en_functional_state_t,
);
pub fn TMR4_OC_GetPolarity(TMR4x: *const CM_TMR4_TypeDef, u32Ch: u32) -> u16;
pub fn TMR4_OC_SetOcInvalidPolarity(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32, u16Polarity: u16);
pub fn TMR4_OC_SetCompareBufCond(
TMR4x: *mut CM_TMR4_TypeDef,
u32Ch: u32,
u16Object: u16,
u16BufCond: u16,
);
pub fn TMR4_OC_GetHighChCompareMode(TMR4x: *const CM_TMR4_TypeDef, u32Ch: u32) -> u16;
pub fn TMR4_OC_SetHighChCompareMode(
TMR4x: *mut CM_TMR4_TypeDef,
u32Ch: u32,
unTmr4Ocmrh: un_tmr4_oc_ocmrh_t,
);
pub fn TMR4_OC_GetLowChCompareMode(TMR4x: *const CM_TMR4_TypeDef, u32Ch: u32) -> u32;
pub fn TMR4_OC_SetLowChCompareMode(
TMR4x: *mut CM_TMR4_TypeDef,
u32Ch: u32,
unTmr4Ocmrl: un_tmr4_oc_ocmrl_t,
);
#[doc = " @addtogroup TMR4_PWM_Global_Functions\n @{"]
pub fn TMR4_PWM_StructInit(pstcTmr4PwmInit: *mut stc_tmr4_pwm_init_t) -> i32;
pub fn TMR4_PWM_Init(
TMR4x: *mut CM_TMR4_TypeDef,
u32Ch: u32,
pstcTmr4PwmInit: *const stc_tmr4_pwm_init_t,
) -> i32;
pub fn TMR4_PWM_DeInit(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32);
pub fn TMR4_PWM_SetClockDiv(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32, u16Div: u16);
pub fn TMR4_PWM_SetPolarity(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32, u16Polarity: u16);
pub fn TMR4_PWM_StartReloadTimer(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32);
pub fn TMR4_PWM_StopReloadTimer(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32);
pub fn TMR4_PWM_SetFilterCountValue(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32, u16Value: u16);
pub fn TMR4_PWM_SetDeadTimeValue(
TMR4x: *mut CM_TMR4_TypeDef,
u32Ch: u32,
u32DeadTimeIndex: u32,
u16Value: u16,
);
pub fn TMR4_PWM_GetDeadTimeValue(
TMR4x: *const CM_TMR4_TypeDef,
u32Ch: u32,
u32DeadTimeIndex: u32,
) -> u16;
pub fn TMR4_PWM_SetAbnormalPinStatus(
TMR4x: *mut CM_TMR4_TypeDef,
u32PwmPin: u32,
u32PinStatus: u32,
);
#[doc = " @addtogroup TMR4_Event_Global_Functions\n @{"]
pub fn TMR4_EVT_StructInit(pstcTmr4EventInit: *mut stc_tmr4_evt_init_t) -> i32;
pub fn TMR4_EVT_Init(
TMR4x: *mut CM_TMR4_TypeDef,
u32Ch: u32,
pstcTmr4EventInit: *const stc_tmr4_evt_init_t,
) -> i32;
pub fn TMR4_EVT_DeInit(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32);
pub fn TMR4_EVT_SetDelayObject(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32, u16Object: u16);
pub fn TMR4_EVT_SetMaskTime(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32, u16MaskTime: u16);
pub fn TMR4_EVT_GetMaskTime(TMR4x: *const CM_TMR4_TypeDef, u32Ch: u32) -> u16;
pub fn TMR4_EVT_SetCompareValue(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32, u16Value: u16);
pub fn TMR4_EVT_GetCompareValue(TMR4x: *const CM_TMR4_TypeDef, u32Ch: u32) -> u16;
pub fn TMR4_EVT_SetOutputEvent(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32, u16Event: u16);
pub fn TMR4_EVT_SetCompareBufCond(TMR4x: *mut CM_TMR4_TypeDef, u32Ch: u32, u16BufCond: u16);
pub fn TMR4_EVT_BufIntervalResponseCmd(
TMR4x: *mut CM_TMR4_TypeDef,
u32Ch: u32,
enNewState: en_functional_state_t,
);
pub fn TMR4_EVT_EventIntervalResponseCmd(
TMR4x: *mut CM_TMR4_TypeDef,
u32Ch: u32,
u16MaskType: u16,
enNewState: en_functional_state_t,
);
pub fn TMR4_EVT_MatchCondCmd(
TMR4x: *mut CM_TMR4_TypeDef,
u32Ch: u32,
u16Cond: u16,
enNewState: en_functional_state_t,
);
pub fn TMR6_StructInit(pstcTmr6Init: *mut stc_tmr6_init_t) -> i32;
pub fn TMR6_Init(TMR6x: *mut CM_TMR6_TypeDef, pstcTmr6Init: *const stc_tmr6_init_t) -> i32;
pub fn TMR6_SetCountMode(TMR6x: *mut CM_TMR6_TypeDef, u32Mode: u32);
pub fn TMR6_SetCountDir(TMR6x: *mut CM_TMR6_TypeDef, u32Dir: u32);
pub fn TMR6_GetCountDir(TMR6x: *mut CM_TMR6_TypeDef) -> u32;
pub fn TMR6_SetClockDiv(TMR6x: *mut CM_TMR6_TypeDef, u32Div: u32);
pub fn TMR6_HWCountUpCondCmd(
TMR6x: *mut CM_TMR6_TypeDef,
u32Cond: u32,
enNewState: en_functional_state_t,
);
pub fn TMR6_HWCountDownCondCmd(
TMR6x: *mut CM_TMR6_TypeDef,
u32Cond: u32,
enNewState: en_functional_state_t,
);
pub fn TMR6_PWM_StructInit(pstcPwmInit: *mut stc_tmr6_pwm_init_t) -> i32;
pub fn TMR6_PWM_Init(
TMR6x: *mut CM_TMR6_TypeDef,
u32Ch: u32,
pstcPwmInit: *const stc_tmr6_pwm_init_t,
) -> i32;
pub fn TMR6_PWM_OutputCmd(
TMR6x: *mut CM_TMR6_TypeDef,
u32Ch: u32,
enNewState: en_functional_state_t,
);
pub fn TMR6_PWM_SetPolarity(
TMR6x: *mut CM_TMR6_TypeDef,
u32Ch: u32,
u32CountState: u32,
u32Polarity: u32,
);
pub fn TMR6_PWM_SetStartStopHold(TMR6x: *mut CM_TMR6_TypeDef, u32Ch: u32, u32HoldStatus: u32);
pub fn TMR6_HWCaptureCondCmd(
TMR6x: *mut CM_TMR6_TypeDef,
u32Ch: u32,
u32Cond: u32,
enNewState: en_functional_state_t,
);
pub fn TMR6_SetFilterClockDiv(TMR6x: *mut CM_TMR6_TypeDef, u32Pin: u32, u32Div: u32);
pub fn TMR6_FilterCmd(
TMR6x: *mut CM_TMR6_TypeDef,
u32Pin: u32,
enNewState: en_functional_state_t,
);
pub fn TMR6_SetFunc(TMR6x: *mut CM_TMR6_TypeDef, u32Ch: u32, u32Func: u32);
pub fn TMR6_IntCmd(
TMR6x: *mut CM_TMR6_TypeDef,
u32IntType: u32,
enNewState: en_functional_state_t,
);
pub fn TMR6_GetStatus(TMR6x: *const CM_TMR6_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn TMR6_ClearStatus(TMR6x: *mut CM_TMR6_TypeDef, u32Flag: u32);
pub fn TMR6_GetPeriodNum(TMR6x: *const CM_TMR6_TypeDef) -> u32;
pub fn TMR6_DeInit(TMR6x: *mut CM_TMR6_TypeDef);
pub fn TMR6_Start(TMR6x: *mut CM_TMR6_TypeDef);
pub fn TMR6_Stop(TMR6x: *mut CM_TMR6_TypeDef);
pub fn TMR6_SetCountValue(TMR6x: *mut CM_TMR6_TypeDef, u32Value: u32);
pub fn TMR6_SetPeriodValue(TMR6x: *mut CM_TMR6_TypeDef, u32Index: u32, u32Value: u32);
pub fn TMR6_SetCompareValue(TMR6x: *mut CM_TMR6_TypeDef, u32Index: u32, u32Value: u32);
pub fn TMR6_SetSpecialCompareValue(TMR6x: *mut CM_TMR6_TypeDef, u32Index: u32, u32Value: u32);
pub fn TMR6_SetDeadTimeValue(TMR6x: *mut CM_TMR6_TypeDef, u32Index: u32, u32Value: u32);
pub fn TMR6_GetCountValue(TMR6x: *const CM_TMR6_TypeDef) -> u32;
pub fn TMR6_GetPeriodValue(TMR6x: *const CM_TMR6_TypeDef, u32Index: u32) -> u32;
pub fn TMR6_GetCompareValue(TMR6x: *const CM_TMR6_TypeDef, u32Index: u32) -> u32;
pub fn TMR6_GetSpecialCompareValue(TMR6x: *const CM_TMR6_TypeDef, u32Index: u32) -> u32;
pub fn TMR6_GetDeadTimeValue(TMR6x: *const CM_TMR6_TypeDef, u32Index: u32) -> u32;
pub fn TMR6_SetGeneralBufNum(TMR6x: *mut CM_TMR6_TypeDef, u32Ch: u32, u32BufNum: u32);
pub fn TMR6_SetPeriodBufNum(TMR6x: *mut CM_TMR6_TypeDef, u32BufNum: u32);
pub fn TMR6_SpecialBufConfig(
TMR6x: *mut CM_TMR6_TypeDef,
u32Ch: u32,
pstcBufConfig: *const stc_tmr6_buf_config_t,
) -> i32;
pub fn TMR6_GeneralBufCmd(
TMR6x: *mut CM_TMR6_TypeDef,
u32Ch: u32,
enNewState: en_functional_state_t,
);
pub fn TMR6_SpecialBufCmd(
TMR6x: *mut CM_TMR6_TypeDef,
u32Ch: u32,
enNewState: en_functional_state_t,
);
pub fn TMR6_PeriodBufCmd(TMR6x: *mut CM_TMR6_TypeDef, enNewState: en_functional_state_t);
pub fn TMR6_ValidPeriodConfig(
TMR6x: *mut CM_TMR6_TypeDef,
pstcValidperiodConfig: *const stc_tmr6_valid_period_config_t,
) -> i32;
pub fn TMR6_ValidPeriodCmd(
TMR6x: *mut CM_TMR6_TypeDef,
u32Ch: u32,
enNewState: en_functional_state_t,
);
pub fn TMR6_DeadTimeFuncCmd(TMR6x: *mut CM_TMR6_TypeDef, enNewState: en_functional_state_t);
pub fn TMR6_DeadTimeConfig(
TMR6x: *mut CM_TMR6_TypeDef,
pstcDeadTimeConfig: *const stc_tmr6_deadtime_config_t,
) -> i32;
pub fn TMR6_ZMaskConfig(
TMR6x: *mut CM_TMR6_TypeDef,
pstcZMaskConfig: *const stc_tmr6_zmask_config_t,
) -> i32;
pub fn TMR6_EMBConfig(
TMR6x: *mut CM_TMR6_TypeDef,
u32Ch: u32,
pstcEmbConfig: *const stc_tmr6_emb_config_t,
) -> i32;
pub fn TMR6_BufFuncStructInit(pstcBufConfig: *mut stc_tmr6_buf_config_t) -> i32;
pub fn TMR6_ValidPeriodStructInit(
pstcValidperiodConfig: *mut stc_tmr6_valid_period_config_t,
) -> i32;
pub fn TMR6_EMBConfigStructInit(pstcEmbConfig: *mut stc_tmr6_emb_config_t) -> i32;
pub fn TMR6_DeadTimeStructInit(pstcDeadTimeConfig: *mut stc_tmr6_deadtime_config_t) -> i32;
pub fn TMR6_ZMaskConfigStructInit(pstcZMaskConfig: *mut stc_tmr6_zmask_config_t) -> i32;
pub fn TMR6_SWSyncStart(u32Unit: u32);
pub fn TMR6_SWSyncStop(u32Unit: u32);
pub fn TMR6_SWSyncClear(u32Unit: u32);
pub fn TMR6_HWStartCondCmd(
TMR6x: *mut CM_TMR6_TypeDef,
u32Cond: u32,
enNewState: en_functional_state_t,
);
pub fn TMR6_HWStartCmd(TMR6x: *mut CM_TMR6_TypeDef, enNewState: en_functional_state_t);
pub fn TMR6_HWStopCondCmd(
TMR6x: *mut CM_TMR6_TypeDef,
u32Cond: u32,
enNewState: en_functional_state_t,
);
pub fn TMR6_HWStopCmd(TMR6x: *mut CM_TMR6_TypeDef, enNewState: en_functional_state_t);
pub fn TMR6_HWClearCondCmd(
TMR6x: *mut CM_TMR6_TypeDef,
u32Cond: u32,
enNewState: en_functional_state_t,
);
pub fn TMR6_HWClearCmd(TMR6x: *mut CM_TMR6_TypeDef, enNewState: en_functional_state_t);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup TMRA_Global_Functions\n @{"]
pub fn TMRA_Init(TMRAx: *mut CM_TMRA_TypeDef, pstcTmraInit: *const stc_tmra_init_t) -> i32;
pub fn TMRA_StructInit(pstcTmraInit: *mut stc_tmra_init_t) -> i32;
pub fn TMRA_SetCountMode(TMRAx: *mut CM_TMRA_TypeDef, u8Mode: u8);
pub fn TMRA_SetCountDir(TMRAx: *mut CM_TMRA_TypeDef, u8Dir: u8);
pub fn TMRA_SetClockDiv(TMRAx: *mut CM_TMRA_TypeDef, u8Div: u8);
pub fn TMRA_HWCountUpCondCmd(
TMRAx: *mut CM_TMRA_TypeDef,
u16Cond: u16,
enNewState: en_functional_state_t,
);
pub fn TMRA_HWCountDownCondCmd(
TMRAx: *mut CM_TMRA_TypeDef,
u16Cond: u16,
enNewState: en_functional_state_t,
);
pub fn TMRA_SetFunc(TMRAx: *mut CM_TMRA_TypeDef, u32Ch: u32, u16Func: u16);
pub fn TMRA_PWM_Init(
TMRAx: *mut CM_TMRA_TypeDef,
u32Ch: u32,
pstcPwmInit: *const stc_tmra_pwm_init_t,
) -> i32;
pub fn TMRA_PWM_StructInit(pstcPwmInit: *mut stc_tmra_pwm_init_t) -> i32;
pub fn TMRA_PWM_OutputCmd(
TMRAx: *mut CM_TMRA_TypeDef,
u32Ch: u32,
enNewState: en_functional_state_t,
);
pub fn TMRA_PWM_SetPolarity(
TMRAx: *mut CM_TMRA_TypeDef,
u32Ch: u32,
u8CountState: u8,
u16Polarity: u16,
);
pub fn TMRA_PWM_SetForcePolarity(TMRAx: *mut CM_TMRA_TypeDef, u32Ch: u32, u16Polarity: u16);
pub fn TMRA_HWCaptureCondCmd(
TMRAx: *mut CM_TMRA_TypeDef,
u32Ch: u32,
u16Cond: u16,
enNewState: en_functional_state_t,
);
pub fn TMRA_HWStartCondCmd(
TMRAx: *mut CM_TMRA_TypeDef,
u16Cond: u16,
enNewState: en_functional_state_t,
);
pub fn TMRA_HWStopCondCmd(
TMRAx: *mut CM_TMRA_TypeDef,
u16Cond: u16,
enNewState: en_functional_state_t,
);
pub fn TMRA_HWClearCondCmd(
TMRAx: *mut CM_TMRA_TypeDef,
u16Cond: u16,
enNewState: en_functional_state_t,
);
pub fn TMRA_SetFilterClockDiv(TMRAx: *mut CM_TMRA_TypeDef, u32Pin: u32, u16Div: u16);
pub fn TMRA_FilterCmd(
TMRAx: *mut CM_TMRA_TypeDef,
u32Pin: u32,
enNewState: en_functional_state_t,
);
pub fn TMRA_DeInit(TMRAx: *mut CM_TMRA_TypeDef) -> i32;
pub fn TMRA_GetCountDir(TMRAx: *const CM_TMRA_TypeDef) -> u8;
pub fn TMRA_SetPeriodValue(TMRAx: *mut CM_TMRA_TypeDef, u32Value: u32);
pub fn TMRA_GetPeriodValue(TMRAx: *const CM_TMRA_TypeDef) -> u32;
pub fn TMRA_SetCountValue(TMRAx: *mut CM_TMRA_TypeDef, u32Value: u32);
pub fn TMRA_GetCountValue(TMRAx: *const CM_TMRA_TypeDef) -> u32;
pub fn TMRA_SetCompareValue(TMRAx: *mut CM_TMRA_TypeDef, u32Ch: u32, u32Value: u32);
pub fn TMRA_GetCompareValue(TMRAx: *const CM_TMRA_TypeDef, u32Ch: u32) -> u32;
pub fn TMRA_SyncStartCmd(TMRAx: *mut CM_TMRA_TypeDef, enNewState: en_functional_state_t);
pub fn TMRA_SetCompareBufCond(TMRAx: *mut CM_TMRA_TypeDef, u32Ch: u32, u16Cond: u16);
pub fn TMRA_CompareBufCmd(
TMRAx: *mut CM_TMRA_TypeDef,
u32Ch: u32,
enNewState: en_functional_state_t,
);
pub fn TMRA_GetStatus(TMRAx: *const CM_TMRA_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn TMRA_ClearStatus(TMRAx: *mut CM_TMRA_TypeDef, u32Flag: u32);
pub fn TMRA_IntCmd(
TMRAx: *mut CM_TMRA_TypeDef,
u32IntType: u32,
enNewState: en_functional_state_t,
);
pub fn TMRA_EventCmd(
TMRAx: *mut CM_TMRA_TypeDef,
u32EventType: u32,
enNewState: en_functional_state_t,
);
pub fn TMRA_Start(TMRAx: *mut CM_TMRA_TypeDef);
pub fn TMRA_Stop(TMRAx: *mut CM_TMRA_TypeDef);
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup TRNG_Global_Functions\n @{"]
pub fn TRNG_DeInit() -> i32;
pub fn TRNG_Init(u32ShiftCount: u32, u32ReloadInitValueEn: u32);
pub fn TRNG_GenerateRandom(pu32Random: *mut u32, u32RandomLen: u32) -> i32;
pub fn TRNG_Start();
pub fn TRNG_Cmd(enNewState: en_functional_state_t);
pub fn TRNG_GetRandom(pu32Random: *mut u32, u8RandomLen: u8) -> i32;
#[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup USART_Global_Functions\n @{"]
pub fn USART_ClockSync_StructInit(pstcClockSyncInit: *mut stc_usart_clocksync_init_t) -> i32;
pub fn USART_ClockSync_Init(
USARTx: *mut CM_USART_TypeDef,
pstcClockSyncInit: *const stc_usart_clocksync_init_t,
pf32Error: *mut float32_t,
) -> i32;
pub fn USART_MultiProcessor_StructInit(
pstcMultiProcessorInit: *mut stc_usart_multiprocessor_init_t,
) -> i32;
pub fn USART_MultiProcessor_Init(
USARTx: *mut CM_USART_TypeDef,
pstcMultiProcessorInit: *const stc_usart_multiprocessor_init_t,
pf32Error: *mut float32_t,
) -> i32;
pub fn USART_UART_StructInit(pstcUartInit: *mut stc_usart_uart_init_t) -> i32;
pub fn USART_UART_Init(
USARTx: *mut CM_USART_TypeDef,
pstcUartInit: *const stc_usart_uart_init_t,
pf32Error: *mut float32_t,
) -> i32;
pub fn USART_SmartCard_StructInit(pstcSmartCardInit: *mut stc_usart_smartcard_init_t) -> i32;
pub fn USART_SmartCard_Init(
USARTx: *mut CM_USART_TypeDef,
pstcSmartCardInit: *const stc_usart_smartcard_init_t,
pf32Error: *mut float32_t,
) -> i32;
pub fn USART_DeInit(USARTx: *mut CM_USART_TypeDef) -> i32;
pub fn USART_FuncCmd(
USARTx: *mut CM_USART_TypeDef,
u32Func: u32,
enNewState: en_functional_state_t,
);
pub fn USART_GetFuncState(USARTx: *mut CM_USART_TypeDef, u32Func: u32)
-> en_functional_state_t;
pub fn USART_GetStatus(USARTx: *const CM_USART_TypeDef, u32Flag: u32) -> en_flag_status_t;
pub fn USART_ClearStatus(USARTx: *mut CM_USART_TypeDef, u32Flag: u32);
pub fn USART_SetParity(USARTx: *mut CM_USART_TypeDef, u32Parity: u32);
pub fn USART_GetParity(USARTx: *mut CM_USART_TypeDef) -> u32;
pub fn USART_SetFirstBit(USARTx: *mut CM_USART_TypeDef, u32FirstBit: u32);
pub fn USART_SetStopBit(USARTx: *mut CM_USART_TypeDef, u32StopBit: u32);
pub fn USART_GetStopBit(USARTx: *mut CM_USART_TypeDef) -> u32;
pub fn USART_SetDataWidth(USARTx: *mut CM_USART_TypeDef, u32DataWidth: u32);
pub fn USART_GetDataWidth(USARTx: *mut CM_USART_TypeDef) -> u32;
pub fn USART_SetOverSampleBit(USARTx: *mut CM_USART_TypeDef, u32OverSampleBit: u32);
pub fn USART_SetStartBitPolarity(USARTx: *mut CM_USART_TypeDef, u32Polarity: u32);
pub fn USART_SetTransType(USARTx: *mut CM_USART_TypeDef, u16Type: u16);
pub fn USART_SetClockDiv(USARTx: *mut CM_USART_TypeDef, u32ClockDiv: u32);
pub fn USART_GetClockDiv(USARTx: *const CM_USART_TypeDef) -> u32;
pub fn USART_SetClockSrc(USARTx: *mut CM_USART_TypeDef, u32ClockSrc: u32);
pub fn USART_GetClockSrc(USARTx: *const CM_USART_TypeDef) -> u32;
pub fn USART_FilterCmd(USARTx: *mut CM_USART_TypeDef, enNewState: en_functional_state_t);
pub fn USART_SilenceCmd(USARTx: *mut CM_USART_TypeDef, enNewState: en_functional_state_t);
pub fn USART_SetHWFlowControl(USARTx: *mut CM_USART_TypeDef, u32HWFlowControl: u32);
pub fn USART_GetHWFlowControl(USARTx: *mut CM_USART_TypeDef) -> u32;
pub fn USART_ReadData(USARTx: *const CM_USART_TypeDef) -> u16;
pub fn USART_WriteData(USARTx: *mut CM_USART_TypeDef, u16Data: u16);
pub fn USART_WriteID(USARTx: *mut CM_USART_TypeDef, u16ID: u16);
pub fn USART_SetBaudrate(
USARTx: *mut CM_USART_TypeDef,
u32Baudrate: u32,
pf32Error: *mut float32_t,
) -> i32;
pub fn USART_SmartCard_SetEtuClock(USARTx: *mut CM_USART_TypeDef, u32EtuClock: u32);
pub fn USART_UART_Trans(
USARTx: *mut CM_USART_TypeDef,
pvBuf: *const ::core::ffi::c_void,
u32Len: u32,
u32Timeout: u32,
) -> i32;
pub fn USART_UART_Receive(
USARTx: *const CM_USART_TypeDef,
pvBuf: *mut ::core::ffi::c_void,
u32Len: u32,
u32Timeout: u32,
) -> i32;
pub fn USART_ClockSync_Trans(
USARTx: *mut CM_USART_TypeDef,
au8Buf: *const u8,
u32Len: u32,
u32Timeout: u32,
) -> i32;
pub fn USART_ClockSync_Receive(
USARTx: *mut CM_USART_TypeDef,
au8Buf: *mut u8,
u32Len: u32,
u32Timeout: u32,
) -> i32;
pub fn USART_ClockSync_TransReceive(
USARTx: *mut CM_USART_TypeDef,
au8TxBuf: *const u8,
au8RxBuf: *mut u8,
u32Len: u32,
u32Timeout: u32,
) -> i32;
#[doc = " Global function prototypes (definition in C source)\n/\n/**\n @addtogroup UTILITY_Global_Functions\n @{"]
pub fn DDL_DelayMS(u32Count: u32);
pub fn DDL_DelayUS(u32Count: u32);
pub fn SysTick_Init(u32Freq: u32) -> i32;
pub fn SysTick_Delay(u32Delay: u32);
pub fn SysTick_IncTick();
pub fn SysTick_GetTick() -> u32;
pub fn SysTick_Suspend();
pub fn SysTick_Resume();
pub fn WDT_Init(pstcWdtInit: *const stc_wdt_init_t) -> i32;
pub fn WDT_FeedDog();
pub fn WDT_GetStatus(u32Flag: u32) -> en_flag_status_t;
pub fn WDT_ClearStatus(u32Flag: u32) -> i32;
}