hardware 0.0.9

A no_std bare-metal hardware abstraction layer — all port I/O, memory and swap allocations are guarded at runtime. Do not consider this dependency stable before x.1.x
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# x86_64 Backend

Architecture-specific implementations for Intel/AMD x86_64 processors.

## Submodules

| File | Description |
|------|-------------|
| `cpuid.rs` | CPUID instruction wrapper, MMIO fallback |
| `io.rs` | I/O port access (`inb`/`outb`/`inl`/`outl`) |
| `msr.rs` | Model-Specific Register read/write |
| `mmio.rs` | Memory-mapped I/O via `read_volatile`/`write_volatile` |
| `register.rs` | General register file (32 `AtomicUsize`) |
| `init.rs` | Shim registration for x86_64 |
| `interrupt.rs` | x86_64-specific interrupt handling |
| `mmu.rs` | Memory management unit |
| `simd.rs` | SIMD (SSE/AVX) detection |
| `syscall.rs` | x86_64 syscall convention — native blob in `shim/syscall.rs` |
| `virtualization.rs` | Virtualization extensions |
| `cpu.rs` | CPU-specific utilities |
| `gpu.rs`, `tpu.rs`, `lpu.rs` | Accelerator stubs |
| `audio.rs`, `camera.rs`, `display.rs`, `input.rs` | Device stubs |
| `modem.rs`, `nfc.rs`, `sensor.rs`, `storage.rs`, `usb.rs` | Device stubs |

## CPUID

```rust
pub fn cpuid_count(leaf: u32, subleaf: u32) -> (u32, u32, u32, u32)
pub fn set_cpuid_mmio(addr: usize)
```

`native_cpuid()` executes the real `cpuid` instruction via `X86_64_CPUID_BLOB` — a 27-byte machine code blob embedded in the `.text` section. It uses `arch_cached()` (not `detect_arch()`) to avoid the recursion cycle: during the initial architecture probe the cache is empty so it returns `(0,0,0,0)`, but once the architecture is cached as X86_64, subsequent calls execute real CPUID. If CPUID MMIO base is configured, reads from that address instead.

## I/O ports

```rust
pub unsafe fn inl(port: u16) -> u32
pub unsafe fn outl(port: u16, val: u32)
pub unsafe fn inb(port: u16) -> u8
pub unsafe fn outb(port: u16, val: u8)
```

All gated by `HW_PRIVILEGE` check. Without privilege, reads return `0xFF`/`0xFFFFFFFF` and writes are no-ops. Uses `OnceCopy<fn(...)>` for the actual I/O functions.

## MSR

```rust
pub unsafe fn read_msr(msr: u32) -> u64
pub unsafe fn write_msr(msr: u32, val: u64)
pub fn set_msr_mmio_base(base: usize)
```

If MSR MMIO base is configured, reads/writes go through MMIO instead of the `rdmsr`/`wrmsr` instructions.

## MMIO

```rust
pub unsafe fn mmio_read32(addr: usize) -> u32
pub unsafe fn mmio_write32(addr: usize, val: u32)
```

Direct `read_volatile`/`write_volatile` at the given address. Address must be valid and 4-byte aligned.

## Initialization

`init_shim()` registers x86_64-specific implementations into the shim layer:
- CPUID function pointer
- TSC MMIO base
- CPUID MMIO base
- MSR MMIO base