hardware 0.0.7

A no_std bare-metal hardware abstraction layer — all port I/O, memory and swap allocations are guarded at runtime. Do not consider this dependency stable before x.1.x
Documentation 
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use super::inference::Inference;
use super::scheduler::LpuScheduler;
use crate::common::once::Once;
use core::sync::atomic::{AtomicUsize, Ordering};

static LPU_INFERENCE: Once<Inference> = Once::new();
static LPU_SCHEDULER: Once<LpuScheduler> = Once::new();

pub fn init() {
    match crate::arch::detect_arch() {
        crate::arch::Architecture::X86_64 => {
            if let Some(ctx) = crate::arch::x86_64::lpu::init_lpu(0, 0, 0) {
                static X86_LPU_SIG: AtomicUsize = AtomicUsize::new(0);
                X86_LPU_SIG.store(
                    ctx.bus as usize
                        ^ ctx.device as usize
                        ^ ctx.function as usize
                        ^ ctx.vendor_id as usize
                        ^ ctx.device_id as usize
                        ^ ctx.bar0_base
                        ^ ctx.bar0_size
                        ^ ctx.msi_vector as usize
                        ^ ctx.coherent_dma_base,
                    Ordering::Release,
                );
            }
            static X86_LPU_DIAG: AtomicUsize = AtomicUsize::new(0);
            X86_LPU_DIAG.store(
                crate::arch::x86_64::lpu::diagnostics(0, 0, 0),
                Ordering::Release,
            );
        }
        crate::arch::Architecture::AArch64 => {
            if let Some(ctx) = crate::arch::aarch64::lpu::init_lpu(0x4000_0000, 0x1_0000, 108) {
                static ARM_LPU_SIG: AtomicUsize = AtomicUsize::new(0);
                ARM_LPU_SIG.store(
                    ctx.mmio_base
                        ^ ctx.mmio_size
                        ^ ctx.device_id as usize
                        ^ ctx.spi_id as usize
                        ^ ctx.smmu_stream_id as usize
                        ^ ctx.dma_region,
                    Ordering::Release,
                );
            }
            static ARM_LPU_DIAG: AtomicUsize = AtomicUsize::new(0);
            ARM_LPU_DIAG.store(
                crate::arch::aarch64::lpu::diagnostics(0x4000_0000),
                Ordering::Release,
            );
        }
        _ => {}
    }

    crate::lpu::device::init();
    if LPU_INFERENCE.get().is_none() {
        let ok_infer = LPU_INFERENCE.set(Inference::new());
        if !ok_infer {}
    }
    if LPU_SCHEDULER.get().is_none() {
        let ok_sched = LPU_SCHEDULER.set(LpuScheduler::new());
        if !ok_sched {}
    }

    let base = 0x4000_0000usize;
    if let Some(accel) = super::drivers::generic::Accelerator::probe(base) {
        accel.init();
        accel.submit_workload(0x5000, 16);
        let ai = accel.is_initialized();
        let ver = accel.read_version();
        static LPU_ACCEL_SIG: AtomicUsize = AtomicUsize::new(0);
        LPU_ACCEL_SIG.store(
            accel.workload_count() ^ (ai as usize) ^ (ver as usize),
            Ordering::Release,
        );
    }
}

pub fn inference() -> Option<&'static Inference> {
    LPU_INFERENCE.get()
}

pub fn scheduler() -> Option<&'static LpuScheduler> {
    LPU_SCHEDULER.get()
}