hardware 0.0.7

A no_std bare-metal hardware abstraction layer — all port I/O, memory and swap allocations are guarded at runtime. Do not consider this dependency stable before x.1.x
Documentation 
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use crate::arch::shim::{
    set_cpuid_fn, set_mmio_read32_fn, set_mmio_write32_fn, set_read_aarch64_midr_fn,
    set_read_msr_fn,
};

pub fn init_shim() {
    set_cpuid_fn(|leaf, subleaf| {
        static CPUID_SHIM_SIG: core::sync::atomic::AtomicUsize =
            core::sync::atomic::AtomicUsize::new(0);
        CPUID_SHIM_SIG.store(
            (leaf as usize).wrapping_add(subleaf as usize),
            core::sync::atomic::Ordering::Release,
        );
        None
    });
    set_read_msr_fn(|msr| {
        static READ_MSR_SHIM_SIG: core::sync::atomic::AtomicUsize =
            core::sync::atomic::AtomicUsize::new(0);
        READ_MSR_SHIM_SIG.store(msr as usize, core::sync::atomic::Ordering::Release);
        None
    });

    set_mmio_read32_fn(|addr| unsafe { Some(crate::arch::aarch64::mmio::mmio_read32(addr)) });
    set_mmio_write32_fn(|addr, val| unsafe {
        crate::arch::aarch64::mmio::mmio_write32(addr, val);
        true
    });

    set_read_aarch64_midr_fn(|| unsafe { Some(crate::arch::aarch64::sysreg::read_midr_el1()) });

    crate::arch::aarch64::cpu::registers::set_cpu_reg_base(0);
    crate::arch::aarch64::cpu::features::set_feature_reg_base(0);
    crate::arch::aarch64::cpu::system_regs::set_sysreg_base(0);
    crate::arch::aarch64::interrupt::gic::set_gic_cpu_base(0);
    crate::arch::aarch64::simd::detect::set_sve_vl_mmio(0);
    crate::arch::aarch64::virtualization::hyp::set_hyp_reg_base(0);
    crate::arch::aarch64::sysreg::set_midr_mmio(0);
}