hardware_rust_crypto/lib.rs
1//! Hardware-only AES-256-GCM and key/nonce generation.
2//!
3//! Every AES round and every GF(2^128) multiply executes as a CPU instruction
4//! (`AES-NI`/`PCLMULQDQ` on `x86_64`, `ARMv8` AES/`PMULL` on `aarch64`); no
5//! software cipher is compiled in. If the required hardware is absent,
6//! construction fails with a typed error rather than degrading to table-based
7//! AES.
8//!
9//! The crate exposes two modules:
10//!
11//! - [`aes_gcm`]: AES-256-GCM. [`aes_gcm::HardwareAes256Gcm`] owns boxed key
12//! state; [`aes_gcm::HardwareAes256GcmKeyState`] owns allocation-free inline
13//! key state; [`aes_gcm::HardwareAes256GcmIn`] places the key state in
14//! caller-provided memory so the caller controls where keys and key-equivalent
15//! state live (use [`aes_gcm::HardwareAes256Gcm::key_state_layout`] to size
16//! and align the storage, [`aes_gcm::UninitKeyStateSlot`] to hand it over).
17//! All zeroize the key state on drop.
18//! - [`random`]: a hardware AES-256-CTR key and nonce generator
19//! ([`random::AesCtrKeyGenerator`]) with fork detection and CPU hardware-RNG
20//! (`RDSEED`/`RNDRRS`) reseeding.
21//!
22//! Implementation details (the AES, GHASH, CTR, and fork-detection internals)
23//! are private; only the high-level types above are part of the public API.
24
25pub mod aes_gcm;
26pub mod random;