�
��fe� � � � d dl Z d dlZd dlZd dlmZ ej
j
e� Ze G d� d� � Z G d� de j � Z y)� N)� dataclassc �h � e Zd ZU ej ed< ej ed< ej ed< y)�BinaryGateTestData�inputA�inputB�outputN)�__name__�
__module__� __qualname__�gsim�
LogicState�__annotations__� � �;D:\Visual Studio Projekte\gsim\python_tests\yosys_import.pyr r s � � �O�O�� �O�O�� �O�O�r r c � � e Zd Zd� Zy)�YosysImportTestsc � � t t j j � t j j � t j j � � t t j j � t j j � t j j � � t t j j � t j j � t j j � � t t j j � t j j
� t j j � � t t j j � t j j � t j j � � t t j j � t j j � t j j � � t t j j � t j j � t j j � � t t j j � t j j
� t j j � � t t j j � t j j � t j j � � t t j j � t j j � t j j � � t t j j � t j j � t j j � � t t j j � t j j
� t j j � � t t j j
� t j j � t j j � � t t j j
� t j j � t j j � � t t j j
� t j j � t j j � � t t j j
� t j j
� t j j
� � t t j d� t j d� t j d� � t t j d� t j d� t j d� � t t j d� t j d� t j d� � g}t j � }|j t j j t d� � \ }}|d }|d }|d }|j � }|D ]� } |j || j � |j || j � |j# d� |j% |� }
| j' |
j) | j* d � � �� y )
N� �U r z*../import_tests/yosys/simple_and_gate.json�a�b�o� � )r r r
�high_z� undefined�logic_0�logic_1�SimulatorBuilder�import_yosys_module�os�path�join� scriptDir�build�set_wire_driver r �run_sim�get_wire_state�
assertTrue�eqr ) �self�testData�builder�inputs�outputsr r r �sim�data� out_states r �test_simple_and_gatez%YosysImportTests.test_simple_and_gate s� � � �t��� 5� 5� 7�� � �9O�9O�9Q�SW�Sb�Sb�Sl�Sl�Sn� o� �t��� 5� 5� 7�� � �9R�9R�9T�VZ�Ve�Ve�Vo�Vo�Vq� r� �t��� 5� 5� 7�� � �9P�9P�9R�TX�Tc�Tc�Tk�Tk�Tm� n� �t��� 5� 5� 7�� � �9P�9P�9R�TX�Tc�Tc�Tm�Tm�To� p� �t��� 8� 8� :�D�O�O�<R�<R�<T�VZ�Ve�Ve�Vo�Vo�Vq� r� �t��� 8� 8� :�D�O�O�<U�<U�<W�Y]�Yh�Yh�Yr�Yr�Yt� u� �t��� 8� 8� :�D�O�O�<S�<S�<U�W[�Wf�Wf�Wn�Wn�Wp� q� �t��� 8� 8� :�D�O�O�<S�<S�<U�W[�Wf�Wf�Wp�Wp�Wr� s� �t��� 6� 6� 8�$�/�/�:P�:P�:R�TX�Tc�Tc�Tk�Tk�Tm� n� �t��� 6� 6� 8�$�/�/�:S�:S�:U�W[�Wf�Wf�Wn�Wn�Wp� q� �t��� 6� 6� 8�$�/�/�:Q�:Q�:S�UY�Ud�Ud�Ul�Ul�Un� o� �t��� 6� 6� 8�$�/�/�:Q�:Q�:S�UY�Ud�Ud�Ul�Ul�Un� o� �t��� 6� 6� 8�$�/�/�:P�:P�:R�TX�Tc�Tc�Tm�Tm�To� p� �t��� 6� 6� 8�$�/�/�:S�:S�:U�W[�Wf�Wf�Wp�Wp�Wr� s� �t��� 6� 6� 8�$�/�/�:Q�:Q�:S�UY�Ud�Ud�Ul�Ul�Un� o� �t��� 6� 6� 8�$�/�/�:Q�:Q�:S�UY�Ud�Ud�Ul�Ul�Un� o� �t���t� 4�d�o�o�d�6K�T�_�_�]a�Mb� c� �t���t� 4�d�o�o�d�6K�T�_�_�]a�Mb� c� �t���t� 4�d�o�o�d�6K�T�_�_�]a�Mb� c�/
��4 �'�'�)�� #� 7� 7���� � �Y�P|�8}� ~�������������� ���m�m�o�� � :�D� � � �v�t�{�{� 3� � � �v�t�{�{� 3� �K�K��N��*�*�6�2�I� �O�O�I�L�L����a� 8� 9� :r N)r r
r r4 r r r r r s � �':r r ) �unittestr" r � dataclassesr r# �dirname�__file__r% r �TestCaser r r r �<module>r: sL �� � � � !� �G�G�O�O�H� %� �
� � � � �
(:�x�(�(� (:r