gpcas_forwardcom 0.2.0

ForwardCom instruction set architecture (ISA) properties for use with the General Purpose Core Architecture Simulator (GPCAS).
Documentation 
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// Filename: constants.rs
// Author:	 Kai Rese
// Version:	 0.11
// Date:	 30-01-2023 (DD-MM-YYYY)
// Library:  gpcas_forwardcom
//
// Copyright (c) 2022 Kai Rese
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as
// published by the Free Software Foundation, either version 3 of the
// License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this program. If not, see
// <https://www.gnu.org/licenses/>.

//! A collection of almost all constants inside the emulator, grouped by the type they refer to.

/// Values that are used if fields aren't present in the format template of an instruction.
pub mod default_values {
    /// The instruction mask. A value of 7 means no mask.
    pub const MASK: u8 = 7;
    /// An memory operand index value of 31 means no index.
    pub const INDEX: u32 = 31;
    /// A length register pointing to the stack pointer means a scalar.
    pub const LENGTH: u32 = 31;
    /// The fallback register index if an instruction is predicated. A value of 31 means the fallback is
    /// zero.
    pub const FALLBACK_REGISTER: usize = 31;
    /// A standard value for the `NUMCONTR` register. The predicate bit for every element of every size
    /// is set.
    pub const NUMCONTR: u64 = 0x0101_0101_0101_0101;
}

/// Defines indices for accessing elements of the [`OperandStorage`](gpcas_isa::OperandStorage)
/// struct.
///
/// Unused operands are allowed to contain arbitrary data and therefore shouldn't be read.
pub mod operand_indices {
    /// Predicates execution for the instruction or for certain elements in a vector.
    pub const MASK: usize = 0;
    /// The value that is set for predicated elements instead of execution.
    pub const FALLBACK: usize = 1;
    /// The output value, either for a register or for a memory store operation.
    pub const OUTPUT: usize = 2;
    /// The first input of the instruction.
    pub const INPUT1: usize = 3;
    /// The second input of the instruction.
    pub const INPUT2: usize = 4;
    /// The third input of the instruction.
    pub const INPUT3: usize = 5;
}

/// Constants to isolate specific fields in an instruction word or a mask.
pub mod parse_masks {
    /// The instruction length.
    ///
    /// 0 => 1 word (multi format),
    /// 1 => 1 word (single format),
    /// 2 => 2 words,
    /// 3 => 3 words.
    pub const IL: u32 = 0xC000_0000;
    /// The instruction mode. This selects the format as well as the instruction list.
    pub const MODE: u32 = 0x3800_0000;
    /// Opcode. Selects an instruction out of the list.
    pub const OP1: u32 = 0x07E0_0000;
    /// Register index D. The register is mostly used as destination.
    pub const RD: u32 = 0x001F_0000;
    /// M bit. Extends either [`MODE`] or [`OT`].
    pub const M: u32 = 0x0000_8000;
    /// Operand type.
    pub const OT: u32 = 0x0000_6000;
    /// Register index S.
    pub const RS: u32 = 0x0000_1F00;
    /// Mask index for the instruction.
    pub const MASK: u32 = 0x0000_00E0;
    /// Register index T.
    pub const RT: u32 = 0x0000_001F;
    /// Second mode field of the E templates.
    pub const MODE2: u32 = 0xE000_0000;
    /// Register U of E templates.
    pub const RU: u32 = 0x1F00_0000;
    /// Additional opcode bits for instructions with E template.
    pub const OP2: u32 = 0x00D0_0000;
    /// Lowest 8 bits in the B and C templates.
    pub const IM1: u32 = 0x0000_00FF;
    /// Bit 8-15 in the C templates.
    pub const IM2: u32 = 0x0000_FF00;
    /// Lowest 24 bits in the D template.
    pub const IM3: u32 = 0x00FF_FFFF;
    /// Lowest 16 bits in the second word of the E templates.
    pub const IM4: u32 = 0x0000_FFFF;
    /// Bits 16-21 in the second word of the E templates.
    pub const IM5: u32 = 0x003F_0000;
    /// Second word of multi-word A, B and C templates.
    pub const IM6: u32 = 0xFFFF_FFFF;
    /// Third word of all three-word templates.
    pub const IM7: u32 = 0xFFFF_FFFF;
}

/// Constants to shift isolated fields so their values can be used naturally.
pub mod parse_shifts {
    /// The instruction length.
    ///
    /// 0 => 1 word (multi format),
    /// 1 => 1 word (single format),
    /// 2 => 2 words,
    /// 3 => 3 words.
    pub const IL: u32 = 30;
    /// The instruction mode. This selects the format as well as the instruction list.
    pub const MODE: u32 = 27;
    /// Opcode. Selects an instruction out of the list.
    pub const OP1: u32 = 21;
    /// Register D. The register is mostly used as destination.
    pub const RD: u32 = 16;
    /// The M bit when extending the `OT` field.
    pub const M_OT: u32 = 13;
    /// The M bit when extending the `MODE` field.
    pub const M_MODE: u32 = 12;
    /// Operand type.
    pub const OT: u32 = 13;
    /// Register S.
    pub const RS: u32 = 8;
    /// Mask index for the instruction.
    pub const MASK: u32 = 5;
    /// Register T.
    pub const RT: u32 = 0;
    /// Second mode field of E templates.
    pub const MODE2: u32 = 29;
    /// Register U.
    pub const RU: u32 = 24;
    /// Opcode 2 for multi-word E templates.
    pub const OP2: u32 = 22;
    /// Lowest 8 bits in the B and C templates.
    pub const IM1: u32 = 0;
    /// Bits 8-15 in the C templates.
    pub const IM2: u32 = 8;
    /// Lowest 24 bits in the D template.
    pub const IM3: u32 = 0;
    /// Lowest 16 bits in the second word of the E templates.
    pub const IM4: u32 = 0;
    /// Bits 16-21 in the second word of the E templates.
    pub const IM5: u32 = 16;
    /// Second word in the multi-word A, B and C templates.
    pub const IM6: u32 = 0;
    /// Third word in all three-word templates.
    pub const IM7: u32 = 0;
}

/// The indices of registers with special functions.
pub mod register_indices {
    /// The address of the thread local data pointer.
    pub const THREADP: usize = 28;
    /// The address of the global data pointer.
    pub const DATAP: usize = 29;
    /// The address of the following instruction.
    pub const IP: usize = 30;
    /// Options for trapping, base for mask registers and used if there is no mask.
    pub const NUMCONTR: usize = 0;
    /// Address of the last added element on the stack.
    pub const STACK_POINTER: usize = 31;
}