[][src]Enum gdbstub::arch::riscv::reg::RiscvRegId

pub enum RiscvRegId {
    Gpr(u8),
    Fpr(u8),
    Pc,
    Csr(u16),
    Priv,
}

RISC-V Register identifier.

Variants

Gpr(u8)

General Purpose Register (x0-x31).

Fpr(u8)

Floating Point Register (f0-f31).

Pc

Program Counter.

Csr(u16)

Control and Status Register.

Priv

Privilege level.

Trait Implementations

impl Clone for RiscvRegId[src]

impl Debug for RiscvRegId[src]

impl RegId for RiscvRegId[src]

Auto Trait Implementations

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T> ToOwned for T where
    T: Clone
[src]

type Owned = T

The resulting type after obtaining ownership.

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.