gd32f4pac 0.9.2

Device support crate for GD32F4 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217

#[doc = "Register `INTEN` reader"]
pub type R = crate::R<IntenSpec>;
#[doc = "Register `INTEN` writer"]
pub type W = crate::W<IntenSpec>;
#[doc = "Field `TMEIE` reader - Transmit mailbox empty interrupt enable"]
pub type TmeieR = crate::BitReader;
#[doc = "Field `TMEIE` writer - Transmit mailbox empty interrupt enable"]
pub type TmeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RFNEIE0` reader - Receive FIFO0 not empty interrupt enable"]
pub type Rfneie0R = crate::BitReader;
#[doc = "Field `RFNEIE0` writer - Receive FIFO0 not empty interrupt enable"]
pub type Rfneie0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RFFIE0` reader - Receive FIFO0 full interrupt enable"]
pub type Rffie0R = crate::BitReader;
#[doc = "Field `RFFIE0` writer - Receive FIFO0 full interrupt enable"]
pub type Rffie0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RFOIE0` reader - Receive FIFO0 overfull interrupt enable"]
pub type Rfoie0R = crate::BitReader;
#[doc = "Field `RFOIE0` writer - Receive FIFO0 overfull interrupt enable"]
pub type Rfoie0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RFNEIE1` reader - Receive FIFO1 not empty interrupt enable"]
pub type Rfneie1R = crate::BitReader;
#[doc = "Field `RFNEIE1` writer - Receive FIFO1 not empty interrupt enable"]
pub type Rfneie1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RFFIE1` reader - Receive FIFO1 full interrupt enable"]
pub type Rffie1R = crate::BitReader;
#[doc = "Field `RFFIE1` writer - Receive FIFO1 full interrupt enable"]
pub type Rffie1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RFOIE1` reader - Receive FIFO1 overfull interrupt enable"]
pub type Rfoie1R = crate::BitReader;
#[doc = "Field `RFOIE1` writer - Receive FIFO1 overfull interrupt enable"]
pub type Rfoie1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WERRIE` reader - Warning error interrupt enable"]
pub type WerrieR = crate::BitReader;
#[doc = "Field `WERRIE` writer - Warning error interrupt enable"]
pub type WerrieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PERRIE` reader - Passive error interrupt enable"]
pub type PerrieR = crate::BitReader;
#[doc = "Field `PERRIE` writer - Passive error interrupt enable"]
pub type PerrieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BOIE` reader - Bus-off interrupt enable"]
pub type BoieR = crate::BitReader;
#[doc = "Field `BOIE` writer - Bus-off interrupt enable"]
pub type BoieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ERRNIE` reader - Error number interrupt enable"]
pub type ErrnieR = crate::BitReader;
#[doc = "Field `ERRNIE` writer - Error number interrupt enable"]
pub type ErrnieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ERRIE` reader - Error interrupt enable"]
pub type ErrieR = crate::BitReader;
#[doc = "Field `ERRIE` writer - Error interrupt enable"]
pub type ErrieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WIE` reader - Wakeup interrupt enable"]
pub type WieR = crate::BitReader;
#[doc = "Field `WIE` writer - Wakeup interrupt enable"]
pub type WieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SLPWIE` reader - Sleep working interrupt enable"]
pub type SlpwieR = crate::BitReader;
#[doc = "Field `SLPWIE` writer - Sleep working interrupt enable"]
pub type SlpwieW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 0 - Transmit mailbox empty interrupt enable"]
    #[inline(always)]
    pub fn tmeie(&self) -> TmeieR {
        TmeieR::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - Receive FIFO0 not empty interrupt enable"]
    #[inline(always)]
    pub fn rfneie0(&self) -> Rfneie0R {
        Rfneie0R::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - Receive FIFO0 full interrupt enable"]
    #[inline(always)]
    pub fn rffie0(&self) -> Rffie0R {
        Rffie0R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - Receive FIFO0 overfull interrupt enable"]
    #[inline(always)]
    pub fn rfoie0(&self) -> Rfoie0R {
        Rfoie0R::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4 - Receive FIFO1 not empty interrupt enable"]
    #[inline(always)]
    pub fn rfneie1(&self) -> Rfneie1R {
        Rfneie1R::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5 - Receive FIFO1 full interrupt enable"]
    #[inline(always)]
    pub fn rffie1(&self) -> Rffie1R {
        Rffie1R::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 6 - Receive FIFO1 overfull interrupt enable"]
    #[inline(always)]
    pub fn rfoie1(&self) -> Rfoie1R {
        Rfoie1R::new(((self.bits >> 6) & 1) != 0)
    }
    #[doc = "Bit 8 - Warning error interrupt enable"]
    #[inline(always)]
    pub fn werrie(&self) -> WerrieR {
        WerrieR::new(((self.bits >> 8) & 1) != 0)
    }
    #[doc = "Bit 9 - Passive error interrupt enable"]
    #[inline(always)]
    pub fn perrie(&self) -> PerrieR {
        PerrieR::new(((self.bits >> 9) & 1) != 0)
    }
    #[doc = "Bit 10 - Bus-off interrupt enable"]
    #[inline(always)]
    pub fn boie(&self) -> BoieR {
        BoieR::new(((self.bits >> 10) & 1) != 0)
    }
    #[doc = "Bit 11 - Error number interrupt enable"]
    #[inline(always)]
    pub fn errnie(&self) -> ErrnieR {
        ErrnieR::new(((self.bits >> 11) & 1) != 0)
    }
    #[doc = "Bit 15 - Error interrupt enable"]
    #[inline(always)]
    pub fn errie(&self) -> ErrieR {
        ErrieR::new(((self.bits >> 15) & 1) != 0)
    }
    #[doc = "Bit 16 - Wakeup interrupt enable"]
    #[inline(always)]
    pub fn wie(&self) -> WieR {
        WieR::new(((self.bits >> 16) & 1) != 0)
    }
    #[doc = "Bit 17 - Sleep working interrupt enable"]
    #[inline(always)]
    pub fn slpwie(&self) -> SlpwieR {
        SlpwieR::new(((self.bits >> 17) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - Transmit mailbox empty interrupt enable"]
    #[inline(always)]
    pub fn tmeie(&mut self) -> TmeieW<IntenSpec> {
        TmeieW::new(self, 0)
    }
    #[doc = "Bit 1 - Receive FIFO0 not empty interrupt enable"]
    #[inline(always)]
    pub fn rfneie0(&mut self) -> Rfneie0W<IntenSpec> {
        Rfneie0W::new(self, 1)
    }
    #[doc = "Bit 2 - Receive FIFO0 full interrupt enable"]
    #[inline(always)]
    pub fn rffie0(&mut self) -> Rffie0W<IntenSpec> {
        Rffie0W::new(self, 2)
    }
    #[doc = "Bit 3 - Receive FIFO0 overfull interrupt enable"]
    #[inline(always)]
    pub fn rfoie0(&mut self) -> Rfoie0W<IntenSpec> {
        Rfoie0W::new(self, 3)
    }
    #[doc = "Bit 4 - Receive FIFO1 not empty interrupt enable"]
    #[inline(always)]
    pub fn rfneie1(&mut self) -> Rfneie1W<IntenSpec> {
        Rfneie1W::new(self, 4)
    }
    #[doc = "Bit 5 - Receive FIFO1 full interrupt enable"]
    #[inline(always)]
    pub fn rffie1(&mut self) -> Rffie1W<IntenSpec> {
        Rffie1W::new(self, 5)
    }
    #[doc = "Bit 6 - Receive FIFO1 overfull interrupt enable"]
    #[inline(always)]
    pub fn rfoie1(&mut self) -> Rfoie1W<IntenSpec> {
        Rfoie1W::new(self, 6)
    }
    #[doc = "Bit 8 - Warning error interrupt enable"]
    #[inline(always)]
    pub fn werrie(&mut self) -> WerrieW<IntenSpec> {
        WerrieW::new(self, 8)
    }
    #[doc = "Bit 9 - Passive error interrupt enable"]
    #[inline(always)]
    pub fn perrie(&mut self) -> PerrieW<IntenSpec> {
        PerrieW::new(self, 9)
    }
    #[doc = "Bit 10 - Bus-off interrupt enable"]
    #[inline(always)]
    pub fn boie(&mut self) -> BoieW<IntenSpec> {
        BoieW::new(self, 10)
    }
    #[doc = "Bit 11 - Error number interrupt enable"]
    #[inline(always)]
    pub fn errnie(&mut self) -> ErrnieW<IntenSpec> {
        ErrnieW::new(self, 11)
    }
    #[doc = "Bit 15 - Error interrupt enable"]
    #[inline(always)]
    pub fn errie(&mut self) -> ErrieW<IntenSpec> {
        ErrieW::new(self, 15)
    }
    #[doc = "Bit 16 - Wakeup interrupt enable"]
    #[inline(always)]
    pub fn wie(&mut self) -> WieW<IntenSpec> {
        WieW::new(self, 16)
    }
    #[doc = "Bit 17 - Sleep working interrupt enable"]
    #[inline(always)]
    pub fn slpwie(&mut self) -> SlpwieW<IntenSpec> {
        SlpwieW::new(self, 17)
    }
}
#[doc = "Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntenSpec;
impl crate::RegisterSpec for IntenSpec {
    type Ux = u32;
}
#[doc = "`read()` method returns [`inten::R`](R) reader structure"]
impl crate::Readable for IntenSpec {}
#[doc = "`write(|w| ..)` method takes [`inten::W`](W) writer structure"]
impl crate::Writable for IntenSpec {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets INTEN to value 0"]
impl crate::Resettable for IntenSpec {}