#[doc = "Register `CTL` reader"]
pub struct R(crate::R<CTL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CTL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CTL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CTL` writer"]
pub struct W(crate::W<CTL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CTL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CTL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL15_A = CTL0_A;
#[doc = "Field `CTL15` reader - Port x configuration bits (y = 0..15)"]
pub type CTL15_R = CTL0_R;
#[doc = "Field `CTL15` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL15_W<'a> {
w: &'a mut W,
}
impl<'a> CTL15_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL15_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL15_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL15_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL15_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL15_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 30)) | ((value as u32 & 0x03) << 30);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL14_A = CTL0_A;
#[doc = "Field `CTL14` reader - Port x configuration bits (y = 0..15)"]
pub type CTL14_R = CTL0_R;
#[doc = "Field `CTL14` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL14_W<'a> {
w: &'a mut W,
}
impl<'a> CTL14_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL14_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL14_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL14_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL14_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL14_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL13_A = CTL0_A;
#[doc = "Field `CTL13` reader - Port x configuration bits (y = 0..15)"]
pub type CTL13_R = CTL0_R;
#[doc = "Field `CTL13` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL13_W<'a> {
w: &'a mut W,
}
impl<'a> CTL13_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL13_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL13_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL13_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL13_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL13_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 26)) | ((value as u32 & 0x03) << 26);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL12_A = CTL0_A;
#[doc = "Field `CTL12` reader - Port x configuration bits (y = 0..15)"]
pub type CTL12_R = CTL0_R;
#[doc = "Field `CTL12` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL12_W<'a> {
w: &'a mut W,
}
impl<'a> CTL12_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL12_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL12_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL12_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL12_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL12_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL11_A = CTL0_A;
#[doc = "Field `CTL11` reader - Port x configuration bits (y = 0..15)"]
pub type CTL11_R = CTL0_R;
#[doc = "Field `CTL11` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL11_W<'a> {
w: &'a mut W,
}
impl<'a> CTL11_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL11_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL11_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL11_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL11_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL11_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL10_A = CTL0_A;
#[doc = "Field `CTL10` reader - Port x configuration bits (y = 0..15)"]
pub type CTL10_R = CTL0_R;
#[doc = "Field `CTL10` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL10_W<'a> {
w: &'a mut W,
}
impl<'a> CTL10_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL10_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL10_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL10_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL10_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL10_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL9_A = CTL0_A;
#[doc = "Field `CTL9` reader - Port x configuration bits (y = 0..15)"]
pub type CTL9_R = CTL0_R;
#[doc = "Field `CTL9` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL9_W<'a> {
w: &'a mut W,
}
impl<'a> CTL9_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL9_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL9_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL9_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL9_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL9_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 18)) | ((value as u32 & 0x03) << 18);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL8_A = CTL0_A;
#[doc = "Field `CTL8` reader - Port x configuration bits (y = 0..15)"]
pub type CTL8_R = CTL0_R;
#[doc = "Field `CTL8` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL8_W<'a> {
w: &'a mut W,
}
impl<'a> CTL8_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL8_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL8_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL8_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL8_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL8_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL7_A = CTL0_A;
#[doc = "Field `CTL7` reader - Port x configuration bits (y = 0..15)"]
pub type CTL7_R = CTL0_R;
#[doc = "Field `CTL7` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL7_W<'a> {
w: &'a mut W,
}
impl<'a> CTL7_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL7_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL7_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL7_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL7_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL7_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL6_A = CTL0_A;
#[doc = "Field `CTL6` reader - Port x configuration bits (y = 0..15)"]
pub type CTL6_R = CTL0_R;
#[doc = "Field `CTL6` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL6_W<'a> {
w: &'a mut W,
}
impl<'a> CTL6_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL6_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL6_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL6_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL6_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL6_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL5_A = CTL0_A;
#[doc = "Field `CTL5` reader - Port x configuration bits (y = 0..15)"]
pub type CTL5_R = CTL0_R;
#[doc = "Field `CTL5` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL5_W<'a> {
w: &'a mut W,
}
impl<'a> CTL5_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL5_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL5_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL5_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL5_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL5_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL4_A = CTL0_A;
#[doc = "Field `CTL4` reader - Port x configuration bits (y = 0..15)"]
pub type CTL4_R = CTL0_R;
#[doc = "Field `CTL4` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL4_W<'a> {
w: &'a mut W,
}
impl<'a> CTL4_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL4_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL4_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL4_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL4_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL4_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL3_A = CTL0_A;
#[doc = "Field `CTL3` reader - Port x configuration bits (y = 0..15)"]
pub type CTL3_R = CTL0_R;
#[doc = "Field `CTL3` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL3_W<'a> {
w: &'a mut W,
}
impl<'a> CTL3_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL3_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL3_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL3_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL3_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL3_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL2_A = CTL0_A;
#[doc = "Field `CTL2` reader - Port x configuration bits (y = 0..15)"]
pub type CTL2_R = CTL0_R;
#[doc = "Field `CTL2` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL2_W<'a> {
w: &'a mut W,
}
impl<'a> CTL2_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL2_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL2_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL2_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL2_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL2_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)"]
pub type CTL1_A = CTL0_A;
#[doc = "Field `CTL1` reader - Port x configuration bits (y = 0..15)"]
pub type CTL1_R = CTL0_R;
#[doc = "Field `CTL1` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL1_W<'a> {
w: &'a mut W,
}
impl<'a> CTL1_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL1_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL1_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL1_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL1_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL1_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2);
self.w
}
}
#[doc = "Port x configuration bits (y = 0..15)\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum CTL0_A {
#[doc = "0: Input mode (reset state)"]
INPUT = 0,
#[doc = "1: General purpose output mode"]
OUTPUT = 1,
#[doc = "2: Alternate function mode"]
ALTERNATE = 2,
#[doc = "3: Analog mode"]
ANALOG = 3,
}
impl From<CTL0_A> for u8 {
#[inline(always)]
fn from(variant: CTL0_A) -> Self {
variant as _
}
}
#[doc = "Field `CTL0` reader - Port x configuration bits (y = 0..15)"]
pub struct CTL0_R(crate::FieldReader<u8, CTL0_A>);
impl CTL0_R {
pub(crate) fn new(bits: u8) -> Self {
CTL0_R(crate::FieldReader::new(bits))
}
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> CTL0_A {
match self.bits {
0 => CTL0_A::INPUT,
1 => CTL0_A::OUTPUT,
2 => CTL0_A::ALTERNATE,
3 => CTL0_A::ANALOG,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `INPUT`"]
#[inline(always)]
pub fn is_input(&self) -> bool {
**self == CTL0_A::INPUT
}
#[doc = "Checks if the value of the field is `OUTPUT`"]
#[inline(always)]
pub fn is_output(&self) -> bool {
**self == CTL0_A::OUTPUT
}
#[doc = "Checks if the value of the field is `ALTERNATE`"]
#[inline(always)]
pub fn is_alternate(&self) -> bool {
**self == CTL0_A::ALTERNATE
}
#[doc = "Checks if the value of the field is `ANALOG`"]
#[inline(always)]
pub fn is_analog(&self) -> bool {
**self == CTL0_A::ANALOG
}
}
impl core::ops::Deref for CTL0_R {
type Target = crate::FieldReader<u8, CTL0_A>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `CTL0` writer - Port x configuration bits (y = 0..15)"]
pub struct CTL0_W<'a> {
w: &'a mut W,
}
impl<'a> CTL0_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CTL0_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Input mode (reset state)"]
#[inline(always)]
pub fn input(self) -> &'a mut W {
self.variant(CTL0_A::INPUT)
}
#[doc = "General purpose output mode"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CTL0_A::OUTPUT)
}
#[doc = "Alternate function mode"]
#[inline(always)]
pub fn alternate(self) -> &'a mut W {
self.variant(CTL0_A::ALTERNATE)
}
#[doc = "Analog mode"]
#[inline(always)]
pub fn analog(self) -> &'a mut W {
self.variant(CTL0_A::ANALOG)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03);
self.w
}
}
impl R {
#[doc = "Bits 30:31 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl15(&self) -> CTL15_R {
CTL15_R::new(((self.bits >> 30) & 0x03) as u8)
}
#[doc = "Bits 28:29 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl14(&self) -> CTL14_R {
CTL14_R::new(((self.bits >> 28) & 0x03) as u8)
}
#[doc = "Bits 26:27 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl13(&self) -> CTL13_R {
CTL13_R::new(((self.bits >> 26) & 0x03) as u8)
}
#[doc = "Bits 24:25 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl12(&self) -> CTL12_R {
CTL12_R::new(((self.bits >> 24) & 0x03) as u8)
}
#[doc = "Bits 22:23 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl11(&self) -> CTL11_R {
CTL11_R::new(((self.bits >> 22) & 0x03) as u8)
}
#[doc = "Bits 20:21 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl10(&self) -> CTL10_R {
CTL10_R::new(((self.bits >> 20) & 0x03) as u8)
}
#[doc = "Bits 18:19 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl9(&self) -> CTL9_R {
CTL9_R::new(((self.bits >> 18) & 0x03) as u8)
}
#[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl8(&self) -> CTL8_R {
CTL8_R::new(((self.bits >> 16) & 0x03) as u8)
}
#[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl7(&self) -> CTL7_R {
CTL7_R::new(((self.bits >> 14) & 0x03) as u8)
}
#[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl6(&self) -> CTL6_R {
CTL6_R::new(((self.bits >> 12) & 0x03) as u8)
}
#[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl5(&self) -> CTL5_R {
CTL5_R::new(((self.bits >> 10) & 0x03) as u8)
}
#[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl4(&self) -> CTL4_R {
CTL4_R::new(((self.bits >> 8) & 0x03) as u8)
}
#[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl3(&self) -> CTL3_R {
CTL3_R::new(((self.bits >> 6) & 0x03) as u8)
}
#[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl2(&self) -> CTL2_R {
CTL2_R::new(((self.bits >> 4) & 0x03) as u8)
}
#[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl1(&self) -> CTL1_R {
CTL1_R::new(((self.bits >> 2) & 0x03) as u8)
}
#[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl0(&self) -> CTL0_R {
CTL0_R::new((self.bits & 0x03) as u8)
}
}
impl W {
#[doc = "Bits 30:31 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl15(&mut self) -> CTL15_W {
CTL15_W { w: self }
}
#[doc = "Bits 28:29 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl14(&mut self) -> CTL14_W {
CTL14_W { w: self }
}
#[doc = "Bits 26:27 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl13(&mut self) -> CTL13_W {
CTL13_W { w: self }
}
#[doc = "Bits 24:25 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl12(&mut self) -> CTL12_W {
CTL12_W { w: self }
}
#[doc = "Bits 22:23 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl11(&mut self) -> CTL11_W {
CTL11_W { w: self }
}
#[doc = "Bits 20:21 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl10(&mut self) -> CTL10_W {
CTL10_W { w: self }
}
#[doc = "Bits 18:19 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl9(&mut self) -> CTL9_W {
CTL9_W { w: self }
}
#[doc = "Bits 16:17 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl8(&mut self) -> CTL8_W {
CTL8_W { w: self }
}
#[doc = "Bits 14:15 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl7(&mut self) -> CTL7_W {
CTL7_W { w: self }
}
#[doc = "Bits 12:13 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl6(&mut self) -> CTL6_W {
CTL6_W { w: self }
}
#[doc = "Bits 10:11 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl5(&mut self) -> CTL5_W {
CTL5_W { w: self }
}
#[doc = "Bits 8:9 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl4(&mut self) -> CTL4_W {
CTL4_W { w: self }
}
#[doc = "Bits 6:7 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl3(&mut self) -> CTL3_W {
CTL3_W { w: self }
}
#[doc = "Bits 4:5 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl2(&mut self) -> CTL2_W {
CTL2_W { w: self }
}
#[doc = "Bits 2:3 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl1(&mut self) -> CTL1_W {
CTL1_W { w: self }
}
#[doc = "Bits 0:1 - Port x configuration bits (y = 0..15)"]
#[inline(always)]
pub fn ctl0(&mut self) -> CTL0_W {
CTL0_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "GPIO port control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](index.html) module"]
pub struct CTL_SPEC;
impl crate::RegisterSpec for CTL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ctl::R](R) reader structure"]
impl crate::Readable for CTL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ctl::W](W) writer structure"]
impl crate::Writable for CTL_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets CTL to value 0"]
impl crate::Resettable for CTL_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}