gd32f1 0.2.0

Device support crate for GD32F1 devices
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#[doc = "Register `G4CYCN` reader"]
pub struct R(crate::R<G4CYCN_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<G4CYCN_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<G4CYCN_SPEC>> for R {
    fn from(reader: crate::R<G4CYCN_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Field `CYCN` reader - Cycle number"]
pub struct CYCN_R(crate::FieldReader<u16, u16>);
impl CYCN_R {
    pub(crate) fn new(bits: u16) -> Self {
        CYCN_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for CYCN_R {
    type Target = crate::FieldReader<u16, u16>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl R {
    #[doc = "Bits 0:13 - Cycle number"]
    #[inline(always)]
    pub fn cycn(&self) -> CYCN_R {
        CYCN_R::new((self.bits & 0x3fff) as u16)
    }
}
#[doc = "I/O group x cycle number register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [g4cycn](index.html) module"]
pub struct G4CYCN_SPEC;
impl crate::RegisterSpec for G4CYCN_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [g4cycn::R](R) reader structure"]
impl crate::Readable for G4CYCN_SPEC {
    type Reader = R;
}
#[doc = "`reset()` method sets G4CYCN to value 0"]
impl crate::Resettable for G4CYCN_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}