gd32e5/gd32e503/timer2/
ctl0.rs

1#[doc = "Register `CTL0` reader"]
2pub type R = crate::R<Ctl0Spec>;
3#[doc = "Register `CTL0` writer"]
4pub type W = crate::W<Ctl0Spec>;
5#[doc = "Counter enable"]
6pub use crate::gd32e503::timer0::ctl0::Cen;
7#[doc = "Field `CEN` reader - Counter enable"]
8pub use crate::gd32e503::timer0::ctl0::CenR;
9#[doc = "Field `CEN` writer - Counter enable"]
10pub use crate::gd32e503::timer0::ctl0::CenW;
11#[doc = "Update disable"]
12pub use crate::gd32e503::timer0::ctl0::Updis;
13#[doc = "Field `UPDIS` reader - Update disable"]
14pub use crate::gd32e503::timer0::ctl0::UpdisR;
15#[doc = "Field `UPDIS` writer - Update disable"]
16pub use crate::gd32e503::timer0::ctl0::UpdisW;
17#[doc = "Update source"]
18pub use crate::gd32e503::timer0::ctl0::Ups;
19#[doc = "Field `UPS` reader - Update source"]
20pub use crate::gd32e503::timer0::ctl0::UpsR;
21#[doc = "Field `UPS` writer - Update source"]
22pub use crate::gd32e503::timer0::ctl0::UpsW;
23#[doc = "Single pulse mode\n\nValue on reset: 0"]
24#[derive(Clone, Copy, Debug, PartialEq, Eq)]
25pub enum Spm {
26    #[doc = "0: Counter is not stopped at update event"]
27    Disabled = 0,
28    #[doc = "1: Counter stops counting at the next update event (clearing the CEN bit)"]
29    Enabled = 1,
30}
31impl From<Spm> for bool {
32    #[inline(always)]
33    fn from(variant: Spm) -> Self {
34        variant as u8 != 0
35    }
36}
37#[doc = "Field `SPM` reader - Single pulse mode"]
38pub type SpmR = crate::BitReader<Spm>;
39impl SpmR {
40    #[doc = "Get enumerated values variant"]
41    #[inline(always)]
42    pub const fn variant(&self) -> Spm {
43        match self.bits {
44            false => Spm::Disabled,
45            true => Spm::Enabled,
46        }
47    }
48    #[doc = "Counter is not stopped at update event"]
49    #[inline(always)]
50    pub fn is_disabled(&self) -> bool {
51        *self == Spm::Disabled
52    }
53    #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
54    #[inline(always)]
55    pub fn is_enabled(&self) -> bool {
56        *self == Spm::Enabled
57    }
58}
59#[doc = "Field `SPM` writer - Single pulse mode"]
60pub type SpmW<'a, REG> = crate::BitWriter<'a, REG, Spm>;
61impl<'a, REG> SpmW<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64{
65    #[doc = "Counter is not stopped at update event"]
66    #[inline(always)]
67    pub fn disabled(self) -> &'a mut crate::W<REG> {
68        self.variant(Spm::Disabled)
69    }
70    #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
71    #[inline(always)]
72    pub fn enabled(self) -> &'a mut crate::W<REG> {
73        self.variant(Spm::Enabled)
74    }
75}
76#[doc = "Auto-reload shadow enable"]
77pub use crate::gd32e503::timer0::ctl0::Arse;
78#[doc = "Field `ARSE` reader - Auto-reload shadow enable"]
79pub use crate::gd32e503::timer0::ctl0::ArseR;
80#[doc = "Field `ARSE` writer - Auto-reload shadow enable"]
81pub use crate::gd32e503::timer0::ctl0::ArseW;
82#[doc = "Counter aligns mode selection"]
83pub use crate::gd32e503::timer0::ctl0::Cam;
84#[doc = "Field `CAM` reader - Counter aligns mode selection"]
85pub use crate::gd32e503::timer0::ctl0::CamR;
86#[doc = "Field `CAM` writer - Counter aligns mode selection"]
87pub use crate::gd32e503::timer0::ctl0::CamW;
88#[doc = "Clock division"]
89pub use crate::gd32e503::timer0::ctl0::Ckdiv;
90#[doc = "Field `CKDIV` reader - Clock division"]
91pub use crate::gd32e503::timer0::ctl0::CkdivR;
92#[doc = "Field `CKDIV` writer - Clock division"]
93pub use crate::gd32e503::timer0::ctl0::CkdivW;
94#[doc = "Direction"]
95pub use crate::gd32e503::timer0::ctl0::Dir;
96#[doc = "Field `DIR` reader - Direction"]
97pub use crate::gd32e503::timer0::ctl0::DirR;
98#[doc = "Field `DIR` writer - Direction"]
99pub use crate::gd32e503::timer0::ctl0::DirW;
100impl R {
101    #[doc = "Bit 0 - Counter enable"]
102    #[inline(always)]
103    pub fn cen(&self) -> CenR {
104        CenR::new((self.bits & 1) != 0)
105    }
106    #[doc = "Bit 1 - Update disable"]
107    #[inline(always)]
108    pub fn updis(&self) -> UpdisR {
109        UpdisR::new(((self.bits >> 1) & 1) != 0)
110    }
111    #[doc = "Bit 2 - Update source"]
112    #[inline(always)]
113    pub fn ups(&self) -> UpsR {
114        UpsR::new(((self.bits >> 2) & 1) != 0)
115    }
116    #[doc = "Bit 3 - Single pulse mode"]
117    #[inline(always)]
118    pub fn spm(&self) -> SpmR {
119        SpmR::new(((self.bits >> 3) & 1) != 0)
120    }
121    #[doc = "Bit 4 - Direction"]
122    #[inline(always)]
123    pub fn dir(&self) -> DirR {
124        DirR::new(((self.bits >> 4) & 1) != 0)
125    }
126    #[doc = "Bits 5:6 - Counter aligns mode selection"]
127    #[inline(always)]
128    pub fn cam(&self) -> CamR {
129        CamR::new(((self.bits >> 5) & 3) as u8)
130    }
131    #[doc = "Bit 7 - Auto-reload shadow enable"]
132    #[inline(always)]
133    pub fn arse(&self) -> ArseR {
134        ArseR::new(((self.bits >> 7) & 1) != 0)
135    }
136    #[doc = "Bits 8:9 - Clock division"]
137    #[inline(always)]
138    pub fn ckdiv(&self) -> CkdivR {
139        CkdivR::new(((self.bits >> 8) & 3) as u8)
140    }
141}
142impl W {
143    #[doc = "Bit 0 - Counter enable"]
144    #[inline(always)]
145    #[must_use]
146    pub fn cen(&mut self) -> CenW<Ctl0Spec> {
147        CenW::new(self, 0)
148    }
149    #[doc = "Bit 1 - Update disable"]
150    #[inline(always)]
151    #[must_use]
152    pub fn updis(&mut self) -> UpdisW<Ctl0Spec> {
153        UpdisW::new(self, 1)
154    }
155    #[doc = "Bit 2 - Update source"]
156    #[inline(always)]
157    #[must_use]
158    pub fn ups(&mut self) -> UpsW<Ctl0Spec> {
159        UpsW::new(self, 2)
160    }
161    #[doc = "Bit 3 - Single pulse mode"]
162    #[inline(always)]
163    #[must_use]
164    pub fn spm(&mut self) -> SpmW<Ctl0Spec> {
165        SpmW::new(self, 3)
166    }
167    #[doc = "Bit 4 - Direction"]
168    #[inline(always)]
169    #[must_use]
170    pub fn dir(&mut self) -> DirW<Ctl0Spec> {
171        DirW::new(self, 4)
172    }
173    #[doc = "Bits 5:6 - Counter aligns mode selection"]
174    #[inline(always)]
175    #[must_use]
176    pub fn cam(&mut self) -> CamW<Ctl0Spec> {
177        CamW::new(self, 5)
178    }
179    #[doc = "Bit 7 - Auto-reload shadow enable"]
180    #[inline(always)]
181    #[must_use]
182    pub fn arse(&mut self) -> ArseW<Ctl0Spec> {
183        ArseW::new(self, 7)
184    }
185    #[doc = "Bits 8:9 - Clock division"]
186    #[inline(always)]
187    #[must_use]
188    pub fn ckdiv(&mut self) -> CkdivW<Ctl0Spec> {
189        CkdivW::new(self, 8)
190    }
191}
192#[doc = "control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
193pub struct Ctl0Spec;
194impl crate::RegisterSpec for Ctl0Spec {
195    type Ux = u32;
196}
197#[doc = "`read()` method returns [`ctl0::R`](R) reader structure"]
198impl crate::Readable for Ctl0Spec {}
199#[doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"]
200impl crate::Writable for Ctl0Spec {
201    type Safety = crate::Unsafe;
202    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
203    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
204}
205#[doc = "`reset()` method sets CTL0 to value 0"]
206impl crate::Resettable for Ctl0Spec {
207    const RESET_VALUE: u32 = 0;
208}
gd32e5/gd32e503/timer2/ctl0.rs

gd32e5/gd32e503/timer2/
ctl0.rs
