gd32e5/gd32e508/timer13/
chctl2.rs

1#[doc = "Register `CHCTL2` reader"]
2pub type R = crate::R<Chctl2Spec>;
3#[doc = "Register `CHCTL2` writer"]
4pub type W = crate::W<Chctl2Spec>;
5#[doc = "Channel 0 capture/compare function enable"]
6pub use crate::gd32e508::timer0::chctl2::Ch0en;
7#[doc = "Field `CH0EN` reader - Channel 0 capture/compare function enable"]
8pub use crate::gd32e508::timer0::chctl2::Ch0enR;
9#[doc = "Field `CH0EN` writer - Channel 0 capture/compare function enable"]
10pub use crate::gd32e508::timer0::chctl2::Ch0enW;
11#[doc = "Channel 0 capture/compare polarity"]
12pub use crate::gd32e508::timer0::chctl2::Ch0p;
13#[doc = "Field `CH0P` reader - Channel 0 capture/compare polarity"]
14pub use crate::gd32e508::timer0::chctl2::Ch0pR;
15#[doc = "Field `CH0NP` reader - Channel 0 complementary output polarity"]
16pub use crate::gd32e508::timer0::chctl2::Ch0pR as Ch0npR;
17#[doc = "Field `CH0P` writer - Channel 0 capture/compare polarity"]
18pub use crate::gd32e508::timer0::chctl2::Ch0pW;
19#[doc = "Field `CH0NP` writer - Channel 0 complementary output polarity"]
20pub use crate::gd32e508::timer0::chctl2::Ch0pW as Ch0npW;
21impl R {
22    #[doc = "Bit 0 - Channel 0 capture/compare function enable"]
23    #[inline(always)]
24    pub fn ch0en(&self) -> Ch0enR {
25        Ch0enR::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - Channel 0 capture/compare polarity"]
28    #[inline(always)]
29    pub fn ch0p(&self) -> Ch0pR {
30        Ch0pR::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 3 - Channel 0 complementary output polarity"]
33    #[inline(always)]
34    pub fn ch0np(&self) -> Ch0npR {
35        Ch0npR::new(((self.bits >> 3) & 1) != 0)
36    }
37}
38impl W {
39    #[doc = "Bit 0 - Channel 0 capture/compare function enable"]
40    #[inline(always)]
41    #[must_use]
42    pub fn ch0en(&mut self) -> Ch0enW<Chctl2Spec> {
43        Ch0enW::new(self, 0)
44    }
45    #[doc = "Bit 1 - Channel 0 capture/compare polarity"]
46    #[inline(always)]
47    #[must_use]
48    pub fn ch0p(&mut self) -> Ch0pW<Chctl2Spec> {
49        Ch0pW::new(self, 1)
50    }
51    #[doc = "Bit 3 - Channel 0 complementary output polarity"]
52    #[inline(always)]
53    #[must_use]
54    pub fn ch0np(&mut self) -> Ch0npW<Chctl2Spec> {
55        Ch0npW::new(self, 3)
56    }
57}
58#[doc = "Channel control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctl2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
59pub struct Chctl2Spec;
60impl crate::RegisterSpec for Chctl2Spec {
61    type Ux = u32;
62}
63#[doc = "`read()` method returns [`chctl2::R`](R) reader structure"]
64impl crate::Readable for Chctl2Spec {}
65#[doc = "`write(|w| ..)` method takes [`chctl2::W`](W) writer structure"]
66impl crate::Writable for Chctl2Spec {
67    type Safety = crate::Unsafe;
68    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
69    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
70}
71#[doc = "`reset()` method sets CHCTL2 to value 0"]
72impl crate::Resettable for Chctl2Spec {
73    const RESET_VALUE: u32 = 0;
74}
gd32e5/gd32e508/timer13/chctl2.rs

gd32e5/gd32e508/timer13/
chctl2.rs
