gd32e5/gd32e503/timer2/
dmainten.rs

1#[doc = "Register `DMAINTEN` reader"]
2pub type R = crate::R<DmaintenSpec>;
3#[doc = "Register `DMAINTEN` writer"]
4pub type W = crate::W<DmaintenSpec>;
5#[doc = "Channel 0 capture/compare interrupt enable"]
6pub use crate::gd32e503::timer0::dmainten::Ch0ie;
7#[doc = "Field `CH0IE` reader - Channel 0 capture/compare interrupt enable"]
8pub use crate::gd32e503::timer0::dmainten::Ch0ieR;
9#[doc = "Field `CH1IE` reader - Channel 1 capture/compare interrupt enable"]
10pub use crate::gd32e503::timer0::dmainten::Ch0ieR as Ch1ieR;
11#[doc = "Field `CH2IE` reader - Channel 2 capture/compare interrupt enable"]
12pub use crate::gd32e503::timer0::dmainten::Ch0ieR as Ch2ieR;
13#[doc = "Field `CH3IE` reader - Channel 3 capture/compare interrupt enable"]
14pub use crate::gd32e503::timer0::dmainten::Ch0ieR as Ch3ieR;
15#[doc = "Field `CH0IE` writer - Channel 0 capture/compare interrupt enable"]
16pub use crate::gd32e503::timer0::dmainten::Ch0ieW;
17#[doc = "Field `CH1IE` writer - Channel 1 capture/compare interrupt enable"]
18pub use crate::gd32e503::timer0::dmainten::Ch0ieW as Ch1ieW;
19#[doc = "Field `CH2IE` writer - Channel 2 capture/compare interrupt enable"]
20pub use crate::gd32e503::timer0::dmainten::Ch0ieW as Ch2ieW;
21#[doc = "Field `CH3IE` writer - Channel 3 capture/compare interrupt enable"]
22pub use crate::gd32e503::timer0::dmainten::Ch0ieW as Ch3ieW;
23#[doc = "Update interrupt enable"]
24pub use crate::gd32e503::timer0::dmainten::Upie;
25#[doc = "Field `UPIE` reader - Update interrupt enable"]
26pub use crate::gd32e503::timer0::dmainten::UpieR;
27#[doc = "Field `UPIE` writer - Update interrupt enable"]
28pub use crate::gd32e503::timer0::dmainten::UpieW;
29#[doc = "Trigger interrupt enable\n\nValue on reset: 0"]
30#[derive(Clone, Copy, Debug, PartialEq, Eq)]
31pub enum Trgie {
32    #[doc = "0: Trigger interrupt disabled"]
33    Disabled = 0,
34    #[doc = "1: Trigger interrupt enabled"]
35    Enabled = 1,
36}
37impl From<Trgie> for bool {
38    #[inline(always)]
39    fn from(variant: Trgie) -> Self {
40        variant as u8 != 0
41    }
42}
43#[doc = "Field `TRGIE` reader - Trigger interrupt enable"]
44pub type TrgieR = crate::BitReader<Trgie>;
45impl TrgieR {
46    #[doc = "Get enumerated values variant"]
47    #[inline(always)]
48    pub const fn variant(&self) -> Trgie {
49        match self.bits {
50            false => Trgie::Disabled,
51            true => Trgie::Enabled,
52        }
53    }
54    #[doc = "Trigger interrupt disabled"]
55    #[inline(always)]
56    pub fn is_disabled(&self) -> bool {
57        *self == Trgie::Disabled
58    }
59    #[doc = "Trigger interrupt enabled"]
60    #[inline(always)]
61    pub fn is_enabled(&self) -> bool {
62        *self == Trgie::Enabled
63    }
64}
65#[doc = "Field `TRGIE` writer - Trigger interrupt enable"]
66pub type TrgieW<'a, REG> = crate::BitWriter<'a, REG, Trgie>;
67impl<'a, REG> TrgieW<'a, REG>
68where
69    REG: crate::Writable + crate::RegisterSpec,
70{
71    #[doc = "Trigger interrupt disabled"]
72    #[inline(always)]
73    pub fn disabled(self) -> &'a mut crate::W<REG> {
74        self.variant(Trgie::Disabled)
75    }
76    #[doc = "Trigger interrupt enabled"]
77    #[inline(always)]
78    pub fn enabled(self) -> &'a mut crate::W<REG> {
79        self.variant(Trgie::Enabled)
80    }
81}
82#[doc = "Update DMA request enable\n\nValue on reset: 0"]
83#[derive(Clone, Copy, Debug, PartialEq, Eq)]
84pub enum Upden {
85    #[doc = "0: Update DMA request disabled"]
86    Disabled = 0,
87    #[doc = "1: Update DMA request enabled"]
88    Enabled = 1,
89}
90impl From<Upden> for bool {
91    #[inline(always)]
92    fn from(variant: Upden) -> Self {
93        variant as u8 != 0
94    }
95}
96#[doc = "Field `UPDEN` reader - Update DMA request enable"]
97pub type UpdenR = crate::BitReader<Upden>;
98impl UpdenR {
99    #[doc = "Get enumerated values variant"]
100    #[inline(always)]
101    pub const fn variant(&self) -> Upden {
102        match self.bits {
103            false => Upden::Disabled,
104            true => Upden::Enabled,
105        }
106    }
107    #[doc = "Update DMA request disabled"]
108    #[inline(always)]
109    pub fn is_disabled(&self) -> bool {
110        *self == Upden::Disabled
111    }
112    #[doc = "Update DMA request enabled"]
113    #[inline(always)]
114    pub fn is_enabled(&self) -> bool {
115        *self == Upden::Enabled
116    }
117}
118#[doc = "Field `UPDEN` writer - Update DMA request enable"]
119pub type UpdenW<'a, REG> = crate::BitWriter<'a, REG, Upden>;
120impl<'a, REG> UpdenW<'a, REG>
121where
122    REG: crate::Writable + crate::RegisterSpec,
123{
124    #[doc = "Update DMA request disabled"]
125    #[inline(always)]
126    pub fn disabled(self) -> &'a mut crate::W<REG> {
127        self.variant(Upden::Disabled)
128    }
129    #[doc = "Update DMA request enabled"]
130    #[inline(always)]
131    pub fn enabled(self) -> &'a mut crate::W<REG> {
132        self.variant(Upden::Enabled)
133    }
134}
135#[doc = "Channel 0 capture/compare DMA request enable\n\nValue on reset: 0"]
136#[derive(Clone, Copy, Debug, PartialEq, Eq)]
137pub enum Ch0den {
138    #[doc = "0: Capture/compare DMA request disabled"]
139    Disabled = 0,
140    #[doc = "1: Capture/compare DMA request enabled"]
141    Enabled = 1,
142}
143impl From<Ch0den> for bool {
144    #[inline(always)]
145    fn from(variant: Ch0den) -> Self {
146        variant as u8 != 0
147    }
148}
149#[doc = "Field `CH0DEN` reader - Channel 0 capture/compare DMA request enable"]
150pub type Ch0denR = crate::BitReader<Ch0den>;
151impl Ch0denR {
152    #[doc = "Get enumerated values variant"]
153    #[inline(always)]
154    pub const fn variant(&self) -> Ch0den {
155        match self.bits {
156            false => Ch0den::Disabled,
157            true => Ch0den::Enabled,
158        }
159    }
160    #[doc = "Capture/compare DMA request disabled"]
161    #[inline(always)]
162    pub fn is_disabled(&self) -> bool {
163        *self == Ch0den::Disabled
164    }
165    #[doc = "Capture/compare DMA request enabled"]
166    #[inline(always)]
167    pub fn is_enabled(&self) -> bool {
168        *self == Ch0den::Enabled
169    }
170}
171#[doc = "Field `CH0DEN` writer - Channel 0 capture/compare DMA request enable"]
172pub type Ch0denW<'a, REG> = crate::BitWriter<'a, REG, Ch0den>;
173impl<'a, REG> Ch0denW<'a, REG>
174where
175    REG: crate::Writable + crate::RegisterSpec,
176{
177    #[doc = "Capture/compare DMA request disabled"]
178    #[inline(always)]
179    pub fn disabled(self) -> &'a mut crate::W<REG> {
180        self.variant(Ch0den::Disabled)
181    }
182    #[doc = "Capture/compare DMA request enabled"]
183    #[inline(always)]
184    pub fn enabled(self) -> &'a mut crate::W<REG> {
185        self.variant(Ch0den::Enabled)
186    }
187}
188#[doc = "Field `CH1DEN` reader - Channel 1 capture/compare DMA request enable"]
189pub use Ch0denR as Ch1denR;
190#[doc = "Field `CH2DEN` reader - Channel 2 capture/compare DMA request enable"]
191pub use Ch0denR as Ch2denR;
192#[doc = "Field `CH3DEN` reader - Channel 3 capture/compare DMA request enable"]
193pub use Ch0denR as Ch3denR;
194#[doc = "Field `CH1DEN` writer - Channel 1 capture/compare DMA request enable"]
195pub use Ch0denW as Ch1denW;
196#[doc = "Field `CH2DEN` writer - Channel 2 capture/compare DMA request enable"]
197pub use Ch0denW as Ch2denW;
198#[doc = "Field `CH3DEN` writer - Channel 3 capture/compare DMA request enable"]
199pub use Ch0denW as Ch3denW;
200#[doc = "Trigger DMA request enable\n\nValue on reset: 0"]
201#[derive(Clone, Copy, Debug, PartialEq, Eq)]
202pub enum Trgden {
203    #[doc = "0: Trigger DMA request disabled"]
204    Disabled = 0,
205    #[doc = "1: Trigger DMA request enabled"]
206    Enabled = 1,
207}
208impl From<Trgden> for bool {
209    #[inline(always)]
210    fn from(variant: Trgden) -> Self {
211        variant as u8 != 0
212    }
213}
214#[doc = "Field `TRGDEN` reader - Trigger DMA request enable"]
215pub type TrgdenR = crate::BitReader<Trgden>;
216impl TrgdenR {
217    #[doc = "Get enumerated values variant"]
218    #[inline(always)]
219    pub const fn variant(&self) -> Trgden {
220        match self.bits {
221            false => Trgden::Disabled,
222            true => Trgden::Enabled,
223        }
224    }
225    #[doc = "Trigger DMA request disabled"]
226    #[inline(always)]
227    pub fn is_disabled(&self) -> bool {
228        *self == Trgden::Disabled
229    }
230    #[doc = "Trigger DMA request enabled"]
231    #[inline(always)]
232    pub fn is_enabled(&self) -> bool {
233        *self == Trgden::Enabled
234    }
235}
236#[doc = "Field `TRGDEN` writer - Trigger DMA request enable"]
237pub type TrgdenW<'a, REG> = crate::BitWriter<'a, REG, Trgden>;
238impl<'a, REG> TrgdenW<'a, REG>
239where
240    REG: crate::Writable + crate::RegisterSpec,
241{
242    #[doc = "Trigger DMA request disabled"]
243    #[inline(always)]
244    pub fn disabled(self) -> &'a mut crate::W<REG> {
245        self.variant(Trgden::Disabled)
246    }
247    #[doc = "Trigger DMA request enabled"]
248    #[inline(always)]
249    pub fn enabled(self) -> &'a mut crate::W<REG> {
250        self.variant(Trgden::Enabled)
251    }
252}
253impl R {
254    #[doc = "Bit 0 - Update interrupt enable"]
255    #[inline(always)]
256    pub fn upie(&self) -> UpieR {
257        UpieR::new((self.bits & 1) != 0)
258    }
259    #[doc = "Bit 1 - Channel 0 capture/compare interrupt enable"]
260    #[inline(always)]
261    pub fn ch0ie(&self) -> Ch0ieR {
262        Ch0ieR::new(((self.bits >> 1) & 1) != 0)
263    }
264    #[doc = "Bit 2 - Channel 1 capture/compare interrupt enable"]
265    #[inline(always)]
266    pub fn ch1ie(&self) -> Ch1ieR {
267        Ch1ieR::new(((self.bits >> 2) & 1) != 0)
268    }
269    #[doc = "Bit 3 - Channel 2 capture/compare interrupt enable"]
270    #[inline(always)]
271    pub fn ch2ie(&self) -> Ch2ieR {
272        Ch2ieR::new(((self.bits >> 3) & 1) != 0)
273    }
274    #[doc = "Bit 4 - Channel 3 capture/compare interrupt enable"]
275    #[inline(always)]
276    pub fn ch3ie(&self) -> Ch3ieR {
277        Ch3ieR::new(((self.bits >> 4) & 1) != 0)
278    }
279    #[doc = "Bit 6 - Trigger interrupt enable"]
280    #[inline(always)]
281    pub fn trgie(&self) -> TrgieR {
282        TrgieR::new(((self.bits >> 6) & 1) != 0)
283    }
284    #[doc = "Bit 8 - Update DMA request enable"]
285    #[inline(always)]
286    pub fn upden(&self) -> UpdenR {
287        UpdenR::new(((self.bits >> 8) & 1) != 0)
288    }
289    #[doc = "Bit 9 - Channel 0 capture/compare DMA request enable"]
290    #[inline(always)]
291    pub fn ch0den(&self) -> Ch0denR {
292        Ch0denR::new(((self.bits >> 9) & 1) != 0)
293    }
294    #[doc = "Bit 10 - Channel 1 capture/compare DMA request enable"]
295    #[inline(always)]
296    pub fn ch1den(&self) -> Ch1denR {
297        Ch1denR::new(((self.bits >> 10) & 1) != 0)
298    }
299    #[doc = "Bit 11 - Channel 2 capture/compare DMA request enable"]
300    #[inline(always)]
301    pub fn ch2den(&self) -> Ch2denR {
302        Ch2denR::new(((self.bits >> 11) & 1) != 0)
303    }
304    #[doc = "Bit 12 - Channel 3 capture/compare DMA request enable"]
305    #[inline(always)]
306    pub fn ch3den(&self) -> Ch3denR {
307        Ch3denR::new(((self.bits >> 12) & 1) != 0)
308    }
309    #[doc = "Bit 14 - Trigger DMA request enable"]
310    #[inline(always)]
311    pub fn trgden(&self) -> TrgdenR {
312        TrgdenR::new(((self.bits >> 14) & 1) != 0)
313    }
314}
315impl W {
316    #[doc = "Bit 0 - Update interrupt enable"]
317    #[inline(always)]
318    #[must_use]
319    pub fn upie(&mut self) -> UpieW<DmaintenSpec> {
320        UpieW::new(self, 0)
321    }
322    #[doc = "Bit 1 - Channel 0 capture/compare interrupt enable"]
323    #[inline(always)]
324    #[must_use]
325    pub fn ch0ie(&mut self) -> Ch0ieW<DmaintenSpec> {
326        Ch0ieW::new(self, 1)
327    }
328    #[doc = "Bit 2 - Channel 1 capture/compare interrupt enable"]
329    #[inline(always)]
330    #[must_use]
331    pub fn ch1ie(&mut self) -> Ch1ieW<DmaintenSpec> {
332        Ch1ieW::new(self, 2)
333    }
334    #[doc = "Bit 3 - Channel 2 capture/compare interrupt enable"]
335    #[inline(always)]
336    #[must_use]
337    pub fn ch2ie(&mut self) -> Ch2ieW<DmaintenSpec> {
338        Ch2ieW::new(self, 3)
339    }
340    #[doc = "Bit 4 - Channel 3 capture/compare interrupt enable"]
341    #[inline(always)]
342    #[must_use]
343    pub fn ch3ie(&mut self) -> Ch3ieW<DmaintenSpec> {
344        Ch3ieW::new(self, 4)
345    }
346    #[doc = "Bit 6 - Trigger interrupt enable"]
347    #[inline(always)]
348    #[must_use]
349    pub fn trgie(&mut self) -> TrgieW<DmaintenSpec> {
350        TrgieW::new(self, 6)
351    }
352    #[doc = "Bit 8 - Update DMA request enable"]
353    #[inline(always)]
354    #[must_use]
355    pub fn upden(&mut self) -> UpdenW<DmaintenSpec> {
356        UpdenW::new(self, 8)
357    }
358    #[doc = "Bit 9 - Channel 0 capture/compare DMA request enable"]
359    #[inline(always)]
360    #[must_use]
361    pub fn ch0den(&mut self) -> Ch0denW<DmaintenSpec> {
362        Ch0denW::new(self, 9)
363    }
364    #[doc = "Bit 10 - Channel 1 capture/compare DMA request enable"]
365    #[inline(always)]
366    #[must_use]
367    pub fn ch1den(&mut self) -> Ch1denW<DmaintenSpec> {
368        Ch1denW::new(self, 10)
369    }
370    #[doc = "Bit 11 - Channel 2 capture/compare DMA request enable"]
371    #[inline(always)]
372    #[must_use]
373    pub fn ch2den(&mut self) -> Ch2denW<DmaintenSpec> {
374        Ch2denW::new(self, 11)
375    }
376    #[doc = "Bit 12 - Channel 3 capture/compare DMA request enable"]
377    #[inline(always)]
378    #[must_use]
379    pub fn ch3den(&mut self) -> Ch3denW<DmaintenSpec> {
380        Ch3denW::new(self, 12)
381    }
382    #[doc = "Bit 14 - Trigger DMA request enable"]
383    #[inline(always)]
384    #[must_use]
385    pub fn trgden(&mut self) -> TrgdenW<DmaintenSpec> {
386        TrgdenW::new(self, 14)
387    }
388}
389#[doc = "DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmainten::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmainten::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
390pub struct DmaintenSpec;
391impl crate::RegisterSpec for DmaintenSpec {
392    type Ux = u32;
393}
394#[doc = "`read()` method returns [`dmainten::R`](R) reader structure"]
395impl crate::Readable for DmaintenSpec {}
396#[doc = "`write(|w| ..)` method takes [`dmainten::W`](W) writer structure"]
397impl crate::Writable for DmaintenSpec {
398    type Safety = crate::Unsafe;
399    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
400    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
401}
402#[doc = "`reset()` method sets DMAINTEN to value 0"]
403impl crate::Resettable for DmaintenSpec {
404    const RESET_VALUE: u32 = 0;
405}
gd32e5/gd32e503/timer2/dmainten.rs

gd32e5/gd32e503/timer2/
dmainten.rs
