gd32e5/gd32e503/i2c0/
stat0.rs

1#[doc = "Register `STAT0` reader"]
2pub type R = crate::R<Stat0Spec>;
3#[doc = "Register `STAT0` writer"]
4pub type W = crate::W<Stat0Spec>;
5#[doc = "Field `SBSEND` reader - START condition sent out in master mode"]
6pub type SbsendR = crate::BitReader;
7#[doc = "Field `ADDSEND` reader - Address is sent in master mode or received and matches in slave mode"]
8pub type AddsendR = crate::BitReader;
9#[doc = "Field `BTC` reader - Byte transmission completed"]
10pub type BtcR = crate::BitReader;
11#[doc = "Field `ADD10SEND` reader - Header of 10-bit address is sent in master mode"]
12pub type Add10sendR = crate::BitReader;
13#[doc = "Field `STPDET` reader - STOP condition detected in slave mode"]
14pub type StpdetR = crate::BitReader;
15#[doc = "Field `RBNE` reader - I2C_DATA is not Empty during receiving"]
16pub type RbneR = crate::BitReader;
17#[doc = "Field `TBE` reader - I2C_DATA is Empty during transmitting"]
18pub type TbeR = crate::BitReader;
19#[doc = "Field `BERR` reader - A bus error occurs indication a unexpected START or STOP condition on I2C bus"]
20pub type BerrR = crate::BitReader;
21#[doc = "Field `BERR` writer - A bus error occurs indication a unexpected START or STOP condition on I2C bus"]
22pub type BerrW<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `LOSTARB` reader - Arbitration Lost in master mode"]
24pub type LostarbR = crate::BitReader;
25#[doc = "Field `LOSTARB` writer - Arbitration Lost in master mode"]
26pub type LostarbW<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `AERR` reader - Acknowledge error"]
28pub type AerrR = crate::BitReader;
29#[doc = "Field `AERR` writer - Acknowledge error"]
30pub type AerrW<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `OUERR` reader - Over-run or under-run situation occurs in slave mode"]
32pub type OuerrR = crate::BitReader;
33#[doc = "Field `OUERR` writer - Over-run or under-run situation occurs in slave mode"]
34pub type OuerrW<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `PECERR` reader - PEC error when receiving data"]
36pub type PecerrR = crate::BitReader;
37#[doc = "Field `PECERR` writer - PEC error when receiving data"]
38pub type PecerrW<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `SMBTO` reader - Timeout signal in SMBus mode"]
40pub type SmbtoR = crate::BitReader;
41#[doc = "Field `SMBTO` writer - Timeout signal in SMBus mode"]
42pub type SmbtoW<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `SMBALT` reader - SMBus Alert status"]
44pub type SmbaltR = crate::BitReader;
45#[doc = "Field `SMBALT` writer - SMBus Alert status"]
46pub type SmbaltW<'a, REG> = crate::BitWriter<'a, REG>;
47impl R {
48    #[doc = "Bit 0 - START condition sent out in master mode"]
49    #[inline(always)]
50    pub fn sbsend(&self) -> SbsendR {
51        SbsendR::new((self.bits & 1) != 0)
52    }
53    #[doc = "Bit 1 - Address is sent in master mode or received and matches in slave mode"]
54    #[inline(always)]
55    pub fn addsend(&self) -> AddsendR {
56        AddsendR::new(((self.bits >> 1) & 1) != 0)
57    }
58    #[doc = "Bit 2 - Byte transmission completed"]
59    #[inline(always)]
60    pub fn btc(&self) -> BtcR {
61        BtcR::new(((self.bits >> 2) & 1) != 0)
62    }
63    #[doc = "Bit 3 - Header of 10-bit address is sent in master mode"]
64    #[inline(always)]
65    pub fn add10send(&self) -> Add10sendR {
66        Add10sendR::new(((self.bits >> 3) & 1) != 0)
67    }
68    #[doc = "Bit 4 - STOP condition detected in slave mode"]
69    #[inline(always)]
70    pub fn stpdet(&self) -> StpdetR {
71        StpdetR::new(((self.bits >> 4) & 1) != 0)
72    }
73    #[doc = "Bit 6 - I2C_DATA is not Empty during receiving"]
74    #[inline(always)]
75    pub fn rbne(&self) -> RbneR {
76        RbneR::new(((self.bits >> 6) & 1) != 0)
77    }
78    #[doc = "Bit 7 - I2C_DATA is Empty during transmitting"]
79    #[inline(always)]
80    pub fn tbe(&self) -> TbeR {
81        TbeR::new(((self.bits >> 7) & 1) != 0)
82    }
83    #[doc = "Bit 8 - A bus error occurs indication a unexpected START or STOP condition on I2C bus"]
84    #[inline(always)]
85    pub fn berr(&self) -> BerrR {
86        BerrR::new(((self.bits >> 8) & 1) != 0)
87    }
88    #[doc = "Bit 9 - Arbitration Lost in master mode"]
89    #[inline(always)]
90    pub fn lostarb(&self) -> LostarbR {
91        LostarbR::new(((self.bits >> 9) & 1) != 0)
92    }
93    #[doc = "Bit 10 - Acknowledge error"]
94    #[inline(always)]
95    pub fn aerr(&self) -> AerrR {
96        AerrR::new(((self.bits >> 10) & 1) != 0)
97    }
98    #[doc = "Bit 11 - Over-run or under-run situation occurs in slave mode"]
99    #[inline(always)]
100    pub fn ouerr(&self) -> OuerrR {
101        OuerrR::new(((self.bits >> 11) & 1) != 0)
102    }
103    #[doc = "Bit 12 - PEC error when receiving data"]
104    #[inline(always)]
105    pub fn pecerr(&self) -> PecerrR {
106        PecerrR::new(((self.bits >> 12) & 1) != 0)
107    }
108    #[doc = "Bit 14 - Timeout signal in SMBus mode"]
109    #[inline(always)]
110    pub fn smbto(&self) -> SmbtoR {
111        SmbtoR::new(((self.bits >> 14) & 1) != 0)
112    }
113    #[doc = "Bit 15 - SMBus Alert status"]
114    #[inline(always)]
115    pub fn smbalt(&self) -> SmbaltR {
116        SmbaltR::new(((self.bits >> 15) & 1) != 0)
117    }
118}
119impl W {
120    #[doc = "Bit 8 - A bus error occurs indication a unexpected START or STOP condition on I2C bus"]
121    #[inline(always)]
122    #[must_use]
123    pub fn berr(&mut self) -> BerrW<Stat0Spec> {
124        BerrW::new(self, 8)
125    }
126    #[doc = "Bit 9 - Arbitration Lost in master mode"]
127    #[inline(always)]
128    #[must_use]
129    pub fn lostarb(&mut self) -> LostarbW<Stat0Spec> {
130        LostarbW::new(self, 9)
131    }
132    #[doc = "Bit 10 - Acknowledge error"]
133    #[inline(always)]
134    #[must_use]
135    pub fn aerr(&mut self) -> AerrW<Stat0Spec> {
136        AerrW::new(self, 10)
137    }
138    #[doc = "Bit 11 - Over-run or under-run situation occurs in slave mode"]
139    #[inline(always)]
140    #[must_use]
141    pub fn ouerr(&mut self) -> OuerrW<Stat0Spec> {
142        OuerrW::new(self, 11)
143    }
144    #[doc = "Bit 12 - PEC error when receiving data"]
145    #[inline(always)]
146    #[must_use]
147    pub fn pecerr(&mut self) -> PecerrW<Stat0Spec> {
148        PecerrW::new(self, 12)
149    }
150    #[doc = "Bit 14 - Timeout signal in SMBus mode"]
151    #[inline(always)]
152    #[must_use]
153    pub fn smbto(&mut self) -> SmbtoW<Stat0Spec> {
154        SmbtoW::new(self, 14)
155    }
156    #[doc = "Bit 15 - SMBus Alert status"]
157    #[inline(always)]
158    #[must_use]
159    pub fn smbalt(&mut self) -> SmbaltW<Stat0Spec> {
160        SmbaltW::new(self, 15)
161    }
162}
163#[doc = "Transfer status register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
164pub struct Stat0Spec;
165impl crate::RegisterSpec for Stat0Spec {
166    type Ux = u32;
167}
168#[doc = "`read()` method returns [`stat0::R`](R) reader structure"]
169impl crate::Readable for Stat0Spec {}
170#[doc = "`write(|w| ..)` method takes [`stat0::W`](W) writer structure"]
171impl crate::Writable for Stat0Spec {
172    type Safety = crate::Unsafe;
173    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
174    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
175}
176#[doc = "`reset()` method sets STAT0 to value 0"]
177impl crate::Resettable for Stat0Spec {
178    const RESET_VALUE: u32 = 0;
179}
gd32e5/gd32e503/i2c0/stat0.rs

gd32e5/gd32e503/i2c0/
stat0.rs
