gd32e5/gd32e503/timer8/
chctl0_input.rs

1#[doc = "Register `CHCTL0_Input` reader"]
2pub type R = crate::R<Chctl0InputSpec>;
3#[doc = "Register `CHCTL0_Input` writer"]
4pub type W = crate::W<Chctl0InputSpec>;
5#[doc = "Field `CH0MS` reader - Channel 0 mode selection"]
6pub type Ch0msR = crate::FieldReader;
7#[doc = "Field `CH0MS` writer - Channel 0 mode selection"]
8pub type Ch0msW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `CH0CAPPSC` reader - Channel 0 input capture prescaler"]
10pub type Ch0cappscR = crate::FieldReader;
11#[doc = "Field `CH0CAPPSC` writer - Channel 0 input capture prescaler"]
12pub type Ch0cappscW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `CH0CAPFLT` reader - Channel 0 input capture filter control"]
14pub type Ch0capfltR = crate::FieldReader;
15#[doc = "Field `CH0CAPFLT` writer - Channel 0 input capture filter control"]
16pub type Ch0capfltW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17#[doc = "Field `CH1MS` reader - Channel 1 mode selection"]
18pub type Ch1msR = crate::FieldReader;
19#[doc = "Field `CH1MS` writer - Channel 1 mode selection"]
20pub type Ch1msW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `CH1CAPPSC` reader - Channel 1 input capture prescaler"]
22pub type Ch1cappscR = crate::FieldReader;
23#[doc = "Field `CH1CAPPSC` writer - Channel 1 input capture prescaler"]
24pub type Ch1cappscW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `CH1CAPFLT` reader - Channel 1 input capture filter control"]
26pub type Ch1capfltR = crate::FieldReader;
27#[doc = "Field `CH1CAPFLT` writer - Channel 1 input capture filter control"]
28pub type Ch1capfltW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29impl R {
30    #[doc = "Bits 0:1 - Channel 0 mode selection"]
31    #[inline(always)]
32    pub fn ch0ms(&self) -> Ch0msR {
33        Ch0msR::new((self.bits & 3) as u8)
34    }
35    #[doc = "Bits 2:3 - Channel 0 input capture prescaler"]
36    #[inline(always)]
37    pub fn ch0cappsc(&self) -> Ch0cappscR {
38        Ch0cappscR::new(((self.bits >> 2) & 3) as u8)
39    }
40    #[doc = "Bits 4:7 - Channel 0 input capture filter control"]
41    #[inline(always)]
42    pub fn ch0capflt(&self) -> Ch0capfltR {
43        Ch0capfltR::new(((self.bits >> 4) & 0x0f) as u8)
44    }
45    #[doc = "Bits 8:9 - Channel 1 mode selection"]
46    #[inline(always)]
47    pub fn ch1ms(&self) -> Ch1msR {
48        Ch1msR::new(((self.bits >> 8) & 3) as u8)
49    }
50    #[doc = "Bits 10:11 - Channel 1 input capture prescaler"]
51    #[inline(always)]
52    pub fn ch1cappsc(&self) -> Ch1cappscR {
53        Ch1cappscR::new(((self.bits >> 10) & 3) as u8)
54    }
55    #[doc = "Bits 12:15 - Channel 1 input capture filter control"]
56    #[inline(always)]
57    pub fn ch1capflt(&self) -> Ch1capfltR {
58        Ch1capfltR::new(((self.bits >> 12) & 0x0f) as u8)
59    }
60}
61impl W {
62    #[doc = "Bits 0:1 - Channel 0 mode selection"]
63    #[inline(always)]
64    #[must_use]
65    pub fn ch0ms(&mut self) -> Ch0msW<Chctl0InputSpec> {
66        Ch0msW::new(self, 0)
67    }
68    #[doc = "Bits 2:3 - Channel 0 input capture prescaler"]
69    #[inline(always)]
70    #[must_use]
71    pub fn ch0cappsc(&mut self) -> Ch0cappscW<Chctl0InputSpec> {
72        Ch0cappscW::new(self, 2)
73    }
74    #[doc = "Bits 4:7 - Channel 0 input capture filter control"]
75    #[inline(always)]
76    #[must_use]
77    pub fn ch0capflt(&mut self) -> Ch0capfltW<Chctl0InputSpec> {
78        Ch0capfltW::new(self, 4)
79    }
80    #[doc = "Bits 8:9 - Channel 1 mode selection"]
81    #[inline(always)]
82    #[must_use]
83    pub fn ch1ms(&mut self) -> Ch1msW<Chctl0InputSpec> {
84        Ch1msW::new(self, 8)
85    }
86    #[doc = "Bits 10:11 - Channel 1 input capture prescaler"]
87    #[inline(always)]
88    #[must_use]
89    pub fn ch1cappsc(&mut self) -> Ch1cappscW<Chctl0InputSpec> {
90        Ch1cappscW::new(self, 10)
91    }
92    #[doc = "Bits 12:15 - Channel 1 input capture filter control"]
93    #[inline(always)]
94    #[must_use]
95    pub fn ch1capflt(&mut self) -> Ch1capfltW<Chctl0InputSpec> {
96        Ch1capfltW::new(self, 12)
97    }
98}
99#[doc = "Channel control register 0 (input mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chctl0_input::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chctl0_input::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
100pub struct Chctl0InputSpec;
101impl crate::RegisterSpec for Chctl0InputSpec {
102    type Ux = u32;
103}
104#[doc = "`read()` method returns [`chctl0_input::R`](R) reader structure"]
105impl crate::Readable for Chctl0InputSpec {}
106#[doc = "`write(|w| ..)` method takes [`chctl0_input::W`](W) writer structure"]
107impl crate::Writable for Chctl0InputSpec {
108    type Safety = crate::Unsafe;
109    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
110    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
111}
112#[doc = "`reset()` method sets CHCTL0_Input to value 0"]
113impl crate::Resettable for Chctl0InputSpec {
114    const RESET_VALUE: u32 = 0;
115}
gd32e5/gd32e503/timer8/chctl0_input.rs

gd32e5/gd32e503/timer8/
chctl0_input.rs
