gd32e2-hal 0.26.0

HAL for the GD32E23x series (Cortex-M23), currently the GD32E230
Documentation 
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//! Hardware abstraction layer for the `GD32E23x` series (Cortex-M23), built on top
//! of the [`gd32e2`](https://crates.io/crates/gd32e2) peripheral access crate.
//! Only the GD32E230 is implemented so far; the crate is named for the family it
//! is meant to grow into.
//!
//! The API leans on the type system: a method that makes no sense for the
//! hardware fails to compile.
//!
//! # Chip variants
//!
//! One feature names the part being built for, and exactly one must be enabled.
//!
//! A feature is the part number with an `x` in each field the code cannot see, so
//! `gd32e230g8xx` is every G8 part: the letter is the bonded pin count (F 20, E 24,
//! G 28, K 32, C 48), the digit the flash code (4 = 16K flash and 4K SRAM, 6 = 32K
//! and 6K, 8 = 64K and 8K), and the last `x` the temperature grade. Only the 32-pin
//! parts spell their package out — a QFN32 (`gd32e230k8ux`) carries VSS on its
//! thermal pad and gives the two freed pins to `PB2` and `PB8`, an LQFP32
//! (`gd32e230k8tx`) does not.
//!
//! # Getting started
//!
//! Clocks come first: freezing the tree is what produces the [`Rcu`](rcu::Rcu)
//! every other module takes, and it enables each peripheral's clock as that
//! peripheral is constructed.
//!
//! ```ignore
//! let dp = pac::Peripherals::take().unwrap();
//! let mut fmc = dp.fmc.constrain();
//! let config = ClockConfig::default().sysclk(SysClk::Pll(PllFreq::Mhz48));
//! let mut rcu = dp.rcu.constrain().freeze(&mut fmc, config);
//! let parts = dp.gpioa.split(&mut rcu);
//! let mut led = parts.pa5.into_output();
//! led.set_high().unwrap();
//! ```

#![no_std]
// --- Warnings ---
#![warn(missing_docs)]
// --- Cargo warnings ---
#![warn(clippy::cargo)]
#![allow(clippy::multiple_crate_versions)]
// --- Pedantic warnings ---
#![warn(clippy::pedantic)]
#![allow(clippy::struct_field_names)]
#![allow(clippy::cast_possible_truncation)]
#![allow(clippy::cast_lossless)]
#![allow(clippy::must_use_candidate)]
// --- Unsafe warnings ---
#![warn(clippy::undocumented_unsafe_blocks)]

// Both halves of the choice are checked in build.rs, which counts the enabled
// features and knows their names. This guards the source against being compiled
// with no build script at all — the flags below are what every gate reads.
#[cfg(not(any(chip_x4, chip_x6, chip_x8)))]
compile_error!("select a chip: enable exactly one of the `gd32e230*` features");

/// Re-export of the peripheral access crate this HAL is built on. Referring to
/// it as `pac` keeps the door open to other parts of the family behind a single
/// alias, instead of naming a specific chip module throughout.
#[doc(no_inline)]
pub use gd32e2::gd32e230 as pac;

pub mod adc;
pub mod cmp;
pub mod crc;
pub mod dma;
pub mod exti;
pub mod fmc;
pub mod gpio;
pub mod i2c;
pub mod prelude;
pub mod rcu;
pub mod spi;
pub mod syscfg;
pub mod time;
pub mod timer;
pub mod usart;
pub mod watchdog;