1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
//! Hardware abstraction layer for the GD32E23x series (Cortex-M23), built on top
//! of the [`gd32e2`] peripheral access crate. Only the GD32E230 is implemented so
//! far; the crate is named for the family it is meant to grow into.
//!
//! The API leans on the type system: a pin's port, number and mode live in its
//! type, so an invalid alternate function or a method that makes no sense for the
//! current mode fails to compile rather than misbehaving on the board.
//!
//! # Chip variants
//!
//! The alternate-function map differs across the GD32E230x series — the same pin
//! at the same AF number can reach a different peripheral depending on the part
//! (`PA2` AF1 is `USART0_TX` on x4 but `USART1_TX` on x8). Exactly one of the
//! `gd32e230x4` / `gd32e230x6` / `gd32e230x8` features must be enabled; zero or
//! several is a compile error rather than a silently wrong pin map. The default
//! is `gd32e230x8`, matching the GD32E230K8U6 this HAL is developed against.
//!
//! # Getting started
//!
//! Clocks come first: [`rcu`] hands out a [`Clocks`](rcu::Clocks) value that the
//! other modules need, and enables each peripheral's clock as it is constructed.
//!
//! ```ignore
//! let mut dp = pac::Peripherals::take().unwrap();
//! let mut rcu = dp.rcu.constrain();
//! let clocks = CFGR::default()
//! .sysclk(PllFreq::Mhz48)
//! .freeze(&mut rcu, &mut dp.fmc);
//! let parts = dp.gpioa.split(&mut rcu);
//! let mut led = parts.pa5.into_output();
//! led.set_high().unwrap();
//! ```
compile_error!;
compile_error!;
/// Re-export of the peripheral access crate this HAL is built on. Referring to
/// it as `pac` keeps the door open to other parts of the family behind a single
/// alias, instead of naming a specific chip module throughout.
pub use gd32e230 as pac;