gaffe_xilinx/xc7/
registers.rs

1use ::packed_struct::prelude::*;
2use super::RegisterAddress;
3
4pub trait Register {
5    fn register_address(&self) -> RegisterAddress;
6}
7
8#[derive(Debug, PackedStruct)]
9#[packed_struct(size_bytes="4", bit_numbering="lsb0", endian="msb")]
10pub struct CrcRegister{
11    #[packed_field(bits="31:0")]
12    pub crc: u32,
13}
14
15impl Register for CrcRegister {
16    fn register_address(&self) -> RegisterAddress {
17        RegisterAddress::CRC
18    }
19}
20
21pub use super::frame_address::FrameAddress as FrameAddressRegister;
22
23impl Register for FrameAddressRegister {
24    fn register_address(&self) -> RegisterAddress {
25        RegisterAddress::FAR
26    }
27}
28
29#[derive(Debug, Clone, Copy, PartialEq, PrimitiveEnum, SmartDefault)]
30pub enum Command {
31    #[default]
32    Null = 0b00000,
33    WriteConfigData = 0b00001,
34    MultipleFrameWrite = 0b00010,
35    LastFrame = 0b00011,
36    ReadConfigData = 0b00100,
37    Start = 0b00101,
38    ResetCapture = 0b00110,
39    ResetCrc = 0b00111,
40    AssertGhigh = 0b01000,
41    Switch = 0b01001,
42    PulseGrestore = 0b01010,
43    Shutdown = 0b01011,
44    PulseGcapture = 0b01100,
45    Desync = 0b01101,
46    InternalProg = 0b01111,
47    CrcCalculate = 0b10000,
48    ReloadWatchdog = 0b10001,
49    BspiRead = 0b10010,
50    FallEdge = 0b10011,
51}
52
53#[derive(Debug, Default, PackedStruct)]
54#[packed_struct(size_bytes="4", bit_numbering="lsb0", endian="msb")]
55pub struct CommandRegister {
56    #[packed_field(bits="4:0", ty="enum")]
57    pub command: Command,
58}
59
60impl Register for CommandRegister {
61    fn register_address(&self) -> RegisterAddress {
62        RegisterAddress::CMD
63    }
64}
65
66#[derive(Debug, Default, PackedStruct)]
67#[packed_struct(size_bytes="4", bit_numbering="lsb0", endian="msb")]
68pub struct ControlRegister0 {
69    #[packed_field(bits="31")]
70    pub efuse_key: bool,
71
72    #[packed_field(bits="30")]
73    pub icap_select: bool,
74
75    #[packed_field(bits="12")]
76    pub over_temp_power_down: bool,
77
78    #[packed_field(bits="10")]
79    pub config_fallback: bool,
80
81    #[packed_field(bits="8")]
82    pub glutmask_b: bool,
83
84    #[packed_field(bits="7")]
85    pub farsrc: bool,
86
87    #[packed_field(bits="6")]
88    pub dec: bool,
89
90    /// When set, both reads and writes are disabled when encrypted bitstreams are used.
91    #[packed_field(bits="5")]
92    pub writes_disabled: bool,
93
94    #[packed_field(bits="4")]
95    pub reads_disabled: bool,
96
97    #[packed_field(bits="3")]
98    pub persist: bool,
99
100    #[packed_field(bits="0")]
101    pub gts_usr_b: bool
102}
103
104impl Register for ControlRegister0 {
105    fn register_address(&self) -> RegisterAddress {
106        RegisterAddress::CTL0
107    }
108}
109
110#[derive(Debug, Clone, Copy, PrimitiveEnum, SmartDefault)]
111#[allow(non_camel_case_types)]
112pub enum BusWidth {
113    #[default]
114    x1 = 0b00,
115    x8 = 0b01,
116    x16 = 0b10,
117    x32 = 0b11,
118}
119
120#[derive(Debug, Clone, Copy, PrimitiveEnum, SmartDefault)]
121pub enum StartupPhaseStatus {
122    #[default]
123    Phase0 = 0b000,
124    Phase1 = 0b001,
125    Phase2 = 0b011,
126    Phase3 = 0b010,
127    Phase4 = 0b110,
128    Phase5 = 0b111,
129    Phase6 = 0b101,
130    Phase7 = 0b100,
131}
132
133#[derive(Debug, Default, PackedStruct)]
134#[packed_struct(size_bytes="4", bit_numbering="lsb0", endian="msb")]
135pub struct StatusRegister {
136    #[packed_field(bits="26:25", ty="enum")]
137    pub bus_width: BusWidth,
138
139    #[packed_field(bits="20:18", ty="enum")]
140    pub startup_state: StartupPhaseStatus,
141
142    #[packed_field(bits="16")]
143    pub dec_error: bool,
144
145    #[packed_field(bits="15")]
146    pub id_error: bool,
147
148    #[packed_field(bits="14")]
149    pub done: bool,
150
151    #[packed_field(bits="13")]
152    pub release_done: bool,
153
154    #[packed_field(bits="12")]
155    pub init_b: bool,
156
157    #[packed_field(bits="11")]
158    pub init_complete: bool,
159
160    #[packed_field(bits="10:8")]
161    pub mode: Integer<u8, packed_bits::Bits3>,
162
163    #[packed_field(bits="7")]
164    pub ghigh_b: bool,
165
166    #[packed_field(bits="6")]
167    pub gwe: bool,
168
169    #[packed_field(bits="5")]
170    pub gts_cfg_b: bool,
171
172    #[packed_field(bits="4")]
173    pub eos: bool,
174
175    #[packed_field(bits="3")]
176    pub dci_match: bool,
177
178    #[packed_field(bits="2")]
179    pub mmcm_lock: bool,
180
181    #[packed_field(bits="1")]
182    pub part_secured: bool,
183
184    #[packed_field(bits="0")]
185    pub crc_error: bool,
186}
187
188impl Register for StatusRegister {
189    fn register_address(&self) -> RegisterAddress {
190        RegisterAddress::STAT
191    }
192}
193
194#[derive(Debug, Default, PackedStruct)]
195#[packed_struct(size_bytes="4", bit_numbering="lsb0", endian="msb")]
196pub struct LoutRegister{
197    #[packed_field(bits="31:0")]
198    pub value: u32,
199}
200
201impl Register for LoutRegister {
202    fn register_address(&self) -> RegisterAddress {
203        RegisterAddress::LOUT
204    }
205}
206
207#[derive(Debug, Clone, Copy, PrimitiveEnum, SmartDefault)]
208pub enum StartupPhaseKeep {
209    #[default]
210    Phase0 = 0b000,
211    Phase1 = 0b001,
212    Phase2 = 0b010,
213    Phase3 = 0b011,
214    Phase4 = 0b100,
215    Phase5 = 0b101,
216    Phase6 = 0b110,
217    Keep = 0b111,
218}
219
220#[derive(Debug, Clone, Copy, PrimitiveEnum, SmartDefault)]
221pub enum StartupPhaseNoWait {
222    #[default]
223    Phase0 = 0b000,
224    Phase1 = 0b001,
225    Phase2 = 0b010,
226    Phase3 = 0b011,
227    Phase4 = 0b100,
228    Phase5 = 0b101,
229    Phase6 = 0b110,
230    NoWait = 0b111,
231}
232
233#[derive(Debug, Clone, Copy, PrimitiveEnum, SmartDefault)]
234pub enum StartupPhaseTracksDone {
235    #[default]
236    Phase1 = 0b000,
237    Phase2 = 0b001,
238    Phase3 = 0b010,
239    Phase4 = 0b011,
240    Phase5 = 0b100,
241    Phase6 = 0b101,
242    TracksDone = 0b110,
243    Keep = 0b111,
244}
245
246#[derive(Debug, Default, PackedStruct)]
247#[packed_struct(size_bytes="4", bit_numbering="lsb0", endian="msb")]
248pub struct ConfigurationOptionsRegister0 {
249    #[packed_field(bits="27")]
250    pub pwrdwn_stat: bool,
251
252    #[packed_field(bits="25")]
253    pub done_pipe: bool,
254
255    #[packed_field(bits="24")]
256    pub drive_done: bool,
257
258    #[packed_field(bits="23")]
259    pub single: bool,
260
261    #[packed_field(bits="22:17")]
262    pub oscfsel: Integer<u8, packed_bits::Bits6>,
263
264    /// Use JTAG clock during startup-sequence.  When set, ssclksrc_user is ignored.
265    #[packed_field(bits="16")]
266    pub ssclksrc_jtag: bool,
267
268    /// Use user clock during startup-sequence.  When both this and
269    /// ssclksrc_jtag are unset, CCLK is used.
270    #[packed_field(bits="15")]
271    pub ssclksrc_user: bool,
272
273    #[packed_field(bits="14:12", ty="enum")]
274    pub done_cycle: StartupPhaseKeep,
275
276    #[packed_field(bits="11:9", ty="enum")]
277    pub match_cycle: StartupPhaseNoWait,
278
279    #[packed_field(bits="8:6", ty="enum")]
280    pub lock_cycle: StartupPhaseNoWait,
281
282    #[packed_field(bits="5:3", ty="enum")]
283    pub gts_cycle: StartupPhaseTracksDone,
284
285    #[packed_field(bits="2:0", ty="enum")]
286    pub gwe_cycle: StartupPhaseTracksDone,
287}
288
289impl Register for ConfigurationOptionsRegister0 {
290    fn register_address(&self) -> RegisterAddress {
291        RegisterAddress::COR0
292    }
293}
294
295#[derive(Debug, Default, PackedStruct)]
296#[packed_struct(size_bytes="4", bit_numbering="lsb0", endian="msb")]
297pub struct CbcRegister{
298    #[packed_field(bits="31:0")]
299    pub value: u32,
300}
301
302impl Register for CbcRegister {
303    fn register_address(&self) -> RegisterAddress {
304        RegisterAddress::CBC
305    }
306}
307
308pub use super::IdCode as IdCodeRegister;
309
310impl Register for IdCodeRegister {
311    fn register_address(&self) -> RegisterAddress {
312        RegisterAddress::IDCODE
313    }
314}
315
316#[derive(Debug, Clone, Copy, PrimitiveEnum, SmartDefault)]
317pub enum RbCrcAction {
318    #[default]
319    Continue = 0b00,
320    Halt = 0b01,
321    CorrectAndContinue = 0b10,
322    CorrectAndHalt = 0b11,
323}
324
325#[derive(Debug, Clone, Copy, PrimitiveEnum, SmartDefault)]
326pub enum BpiPageSize {
327    #[default]
328    OneBytePerWord = 0b00,
329    FourBytesPerWord = 0b01,
330    EightBytesPerWord = 0b10,
331}
332
333#[derive(Debug, Default, PackedStruct)]
334#[packed_struct(size_bytes="4", bit_numbering="lsb0", endian="msb")]
335pub struct ConfigurationOptionsRegister1 {
336    #[packed_field(bits="17")]
337    pub persist_deassert_at_desync: bool,
338
339    #[packed_field(bits="16:15", ty="enum")]
340    pub rb_crc_action: RbCrcAction,
341
342    #[packed_field(bits="9")]
343    pub rb_crc_no_pin: bool,
344
345    #[packed_field(bits="8")]
346    pub rb_crc_en: bool,
347
348    /// First read cycle is register value plus one.
349    #[packed_field(bits="3:2")]
350    pub bpi_first_read_cycle: Integer<u8, packed_bits::Bits2>,
351
352    #[packed_field(bits="1:0", ty="enum")]
353    pub bpi_page_size: BpiPageSize,
354}
355
356impl Register for ConfigurationOptionsRegister1 {
357    fn register_address(&self) -> RegisterAddress {
358        RegisterAddress::COR1
359    }
360}
361
362#[derive(Debug, Default, PackedStruct)]
363#[packed_struct(size_bytes="4", bit_numbering="lsb0", endian="msb")]
364pub struct WarmBootStartAddressRegister {
365    #[packed_field(bits="31:30")]
366    pub rs: Integer<u8, packed_bits::Bits2>,
367
368    #[packed_field(bits="29")]
369    pub rs_ts_b: bool,
370
371    #[packed_field(bits="28:0")]
372    pub start_addr: Integer<u32, packed_bits::Bits29>,
373}
374
375impl Register for WarmBootStartAddressRegister {
376    fn register_address(&self) -> RegisterAddress {
377        RegisterAddress::WBSTAR
378    }
379}
380
381#[derive(Debug, Default, PackedStruct)]
382#[packed_struct(size_bytes="4", bit_numbering="lsb0", endian="msb")]
383pub struct WatchdogTimerRegister {
384    #[packed_field(bits="31")]
385    pub timer_user_mon: bool,
386
387    #[packed_field(bits="30")]
388    pub timer_cfg_mon: bool,
389
390    #[packed_field(bits="29:0")]
391    pub timer_val: Integer<u32, packed_bits::Bits30>,
392}
393
394impl Register for WatchdogTimerRegister {
395    fn register_address(&self) -> RegisterAddress {
396        RegisterAddress::TIMER
397    }
398}
399
400#[derive(Debug, Default, PackedStruct)]
401#[packed_struct(size_bytes="4", bit_numbering="lsb0", endian="msb")]
402pub struct BootHistoryStatusRegister {
403    #[packed_field(bits="15")]
404    pub hmac_error_1: bool,
405
406    #[packed_field(bits="14")]
407    pub wrap_error_1: bool,
408    
409    #[packed_field(bits="13")]
410    pub crc_error_1: bool,
411    
412    #[packed_field(bits="12")]
413    pub id_error_1: bool,
414    
415    #[packed_field(bits="11")]
416    pub wto_error_1: bool,
417    
418    #[packed_field(bits="10")]
419    pub iprog_1: bool,
420    
421    #[packed_field(bits="9")]
422    pub fallback_1: bool,
423    
424    #[packed_field(bits="8")]
425    pub valid_1: bool,
426    
427    #[packed_field(bits="7")]
428    pub hmac_error_0: bool,
429    
430    #[packed_field(bits="6")]
431    pub wrap_error_0: bool,
432    
433    #[packed_field(bits="5")]
434    pub crc_error_0: bool,
435    
436    #[packed_field(bits="4")]
437    pub id_error_0: bool,
438    
439    #[packed_field(bits="3")]
440    pub wto_error_0: bool,
441    
442    #[packed_field(bits="2")]
443    pub iprog_0: bool,
444    
445    #[packed_field(bits="1")]
446    pub fallback_0: bool,
447    
448    #[packed_field(bits="0")]
449    pub valid_0: bool,
450}
451
452impl Register for BootHistoryStatusRegister {
453    fn register_address(&self) -> RegisterAddress {
454        RegisterAddress::BOOTSTS
455    }
456}
457
458#[derive(Debug, Default, PackedStruct)]
459#[packed_struct(size_bytes="4", bit_numbering="lsb0", endian="msb")]
460pub struct ControlRegister1{
461    #[packed_field(bits="21")]
462    pub inhibit_cmd_reexec_on_far_write: bool,
463}
464
465impl Register for ControlRegister1 {
466    fn register_address(&self) -> RegisterAddress {
467        RegisterAddress::CTL1
468    }
469}
470
471#[derive(Debug, Default, PackedStruct)]
472#[packed_struct(size_bytes="4", bit_numbering="lsb0", endian="msb")]
473pub struct BpiSpiConfigurationOptionsRegister{
474    #[packed_field(bits="31:0")]
475    pub value: u32,
476}
477
478impl Register for BpiSpiConfigurationOptionsRegister {
479    fn register_address(&self) -> RegisterAddress {
480        RegisterAddress::BSPI
481    }
482}
483
484#[derive(Debug, Default, PackedStruct)]
485#[packed_struct(size_bytes="4", bit_numbering="lsb0", endian="msb")]
486pub struct MaskRegister{
487    #[packed_field(bits="31:0")]
488    pub value: u32,
489}
490
491impl Register for MaskRegister {
492    fn register_address(&self) -> RegisterAddress {
493        RegisterAddress::MASK
494    }
495}
gaffe_xilinx/xc7/registers.rs

gaffe_xilinx/xc7/
registers.rs
