forj
A suite of tools for interacting with (System)Verilog hardware designs, fully compliant with 1800-2023
This project is currently under initial development - stay tuned!
Packages
Forj is composed of many children projects to separate complexity and use cases
forj-parser
A complete preprocessor and parser for SystemVerilog source text, forming an CST as defined by forj-syntax
forj-python
Python bindings for the forj SystemVerilog tools
forj-syntax
An object definition of a SystemVerilog CST
