fayalite 0.2.0

Hardware Description Language embedded in Rust, using FIRRTL's semantics
Documentation 
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// SPDX-License-Identifier: LGPL-3.0-or-later
// See Notices.txt for copyright information
pub use crate::{
    annotations::{
        BlackBoxInlineAnnotation, BlackBoxPathAnnotation, CustomFirrtlAnnotation,
        DocStringAnnotation, DontTouchAnnotation, SVAttributeAnnotation,
    },
    array::{Array, ArrayType},
    bundle::Bundle,
    cli::Cli,
    clock::{Clock, ClockDomain, ToClock},
    enum_::{Enum, HdlNone, HdlOption, HdlSome},
    expr::{
        repeat, CastBitsTo, CastTo, CastToBits, Expr, HdlPartialEq, HdlPartialOrd, MakeUninitExpr,
        ReduceBits, ToExpr,
    },
    formal::{
        all_const, all_seq, any_const, any_seq, formal_global_clock, formal_reset, hdl_assert,
        hdl_assert_with_enable, hdl_assume, hdl_assume_with_enable, hdl_cover,
        hdl_cover_with_enable, MakeFormalExpr,
    },
    hdl, hdl_module,
    int::{Bool, DynSize, KnownSize, SInt, SIntType, Size, UInt, UIntType},
    memory::{Mem, MemBuilder, ReadUnderWrite},
    module::{
        annotate, connect, connect_any, incomplete_wire, instance, memory, memory_array,
        memory_with_init, reg_builder, wire, Instance, Module, ModuleBuilder,
    },
    reg::Reg,
    reset::{AsyncReset, Reset, SyncReset, ToAsyncReset, ToReset, ToSyncReset},
    source_location::SourceLocation,
    ty::{AsMask, CanonicalType, Type},
    util::{ConstUsize, GenericConstUsize},
    wire::Wire,
    __,
};