fayalite 0.2.0

Hardware Description Language embedded in Rust, using FIRRTL's semantics
Documentation 
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// SPDX-License-Identifier: LGPL-3.0-or-later
// See Notices.txt for copyright information
//! These are for when you want to use modules written in
//! some other language, such as Verilog.
//!
//! You create an extern module by using an [`#[hdl_module(extern)]`][crate::hdl_module] attribute
//! on your module function. You then create [inputs/outputs] like for normal modules, then you
//! can set the verilog name and parameters using [`ModuleBuilder`] methods:
//!
//!  * [`verilog_name()`][`ModuleBuilder::verilog_name`]
//!  * [`parameter_int()`][`ModuleBuilder::parameter_int`]
//!  * [`parameter_str()`][`ModuleBuilder::parameter_str`]
//!  * [`parameter_raw_verilog()`][`ModuleBuilder::parameter_raw_verilog`]
//!  * [`parameter()`][`ModuleBuilder::parameter`]
//!
//! [inputs/outputs]: crate::_docs::modules::module_bodies::hdl_let_statements::inputs_outputs

#[allow(unused)]
use crate::module::ModuleBuilder;