fayalite 0.2.0

Hardware Description Language embedded in Rust, using FIRRTL's semantics
Documentation 
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// SPDX-License-Identifier: LGPL-3.0-or-later
// See Notices.txt for copyright information
use clap::Parser;
use fayalite::{cli, prelude::*};

#[hdl_module]
fn blinky(clock_frequency: u64) {
    #[hdl]
    let clk: Clock = m.input();
    #[hdl]
    let rst: SyncReset = m.input();
    let cd = #[hdl]
    ClockDomain {
        clk,
        rst: rst.to_reset(),
    };
    let max_value = clock_frequency / 2 - 1;
    let int_ty = UInt::range_inclusive(0..=max_value);
    #[hdl]
    let counter_reg: UInt = reg_builder().clock_domain(cd).reset(0u8.cast_to(int_ty));
    #[hdl]
    let output_reg: Bool = reg_builder().clock_domain(cd).reset(false);
    #[hdl]
    if counter_reg.cmp_eq(max_value) {
        connect_any(counter_reg, 0u8);
        connect(output_reg, !output_reg);
    } else {
        connect_any(counter_reg, counter_reg + 1_hdl_u1);
    }
    #[hdl]
    let led: Bool = m.output();
    connect(led, output_reg);
}

#[derive(Parser)]
struct Cli {
    /// clock frequency in hertz
    #[arg(long, default_value = "1000000", value_parser = clap::value_parser!(u64).range(2..))]
    clock_frequency: u64,
    #[command(subcommand)]
    cli: cli::Cli,
}

fn main() -> cli::Result {
    let cli = Cli::parse();
    cli.cli.run(blinky(cli.clock_frequency))
}