fabbula

A digital dream, to polygons cast, Through rigorous grids, made ready to last. A mark in the metal, a tale to be told, Your art in the silicon, permanent, bold.

Getting Started · Examples · How It Works · Supported PDKs · Performance · Prompt Guide · Roadmap

What is fabbula?

fabbula is a Rust toolchain that converts raster images into DRC-clean GDSII layout data - ready to be fabricated as artwork on the top-metal layer of your chip.

The name comes from fab (as in semiconductor fabrication) + fabula (Latin for story, tale, fable). Every chip carries a story - of the team that designed it, the problem it solves, the late nights and breakthroughs. fabbula lets you etch that story into silicon, literally.

In the open-source chip community, there's a long tradition of hiding art on the die: logos, mascots, inside jokes, dedications. Until now, getting art onto your tapeout meant cobbling together Python scripts, ImageMagick, Inkscape, KLayout macros, and a lot of manual DRC cleanup. fabbula replaces all of that with a single Rust binary. One command. Zero runtime dependencies.

prompt → AI image → fabbula → GDSII → tapeout → your art lives in silicon forever

Examples

Interactive HTML previews with pan and zoom - powered by fabbula's built-in viewer.

Why fabbula?

Existing image-to-GDSII tools are fragmented, single-PDK, and produce naive pixel-mapped rectangles that fail DRC. fabbula is different:

• End-to-end pipeline - PNG from ChatGPT/Gemini goes in, fab-ready GDSII comes out
• Pure Rust - bitmap processing, polygon merging, GDSII writer (gds21). No Python, no Inkscape, no potrace, no ImageMagick. Just cargo install fabbula
• Multi-PDK - ships with 6 built-in PDKs (SKY130, IHP SG13G2, GF180MCU, FreePDK45, ASAP7, fabbula2). Add your own with a 30-line TOML file
• DRC-clean by construction - polygon sizing and grid snapping derived from actual PDK design rules
• Blazing fast - packed bitset bitmap, parallel DRC via rayon, streaming I/O. Processes a 2048x2048 image in ~12ms and validates 100k rectangles in ~15ms. See Performance
• Built-in DRC checker - validates output before you waste a shuttle run

Getting Started

# Install
cargo install fabbula

# Generate chip art from an AI-generated image
fabbula generate -i mascot.png -o mascot.gds -p sky130 --svg preview.svg

# See what your PDK expects
fabbula show-pdk ihp_sg13g2

# Merge artwork into your chip layout
fabbula merge -i mascot.png --chip my_chip.gds -o my_chip_art.gds -p gf180mcu

# Generate artwork at a specific physical size (2mm x 2mm)
fabbula generate -i dalle_output.png -o art.gds -p sky130 \
    --size-um 2000x2000 --check-drc

How It Works

fabbula operates as a three-stage pipeline, each stage implemented in pure Rust:

┌──────────────┐    ┌──────────────┐    ┌──────────────┐
│    Image     │───>│  Bitmap to   │───>│  Polygons    │
│  (PNG/JPEG)  │    │  Rectangles  │    │  to GDSII    │
└──────────────┘    └──────────────┘    └──────────────┘
   Threshold to      Merge adjacent      Write GdsBoundary
   binary bitmap     pixels into rects   on artwork layer
   (Otsu/luma)       with DRC sizing     (gds21)

Stage 1 - Threshold. The input image is converted to a packed binary bitmap. Otsu's automatic thresholding handles varied image inputs. Supports luminance and alpha channel modes.

Stage 2 - Polygon Generation. Bitmap pixels are mapped to DRC-clean rectangles. Each pixel becomes a min_width x min_width square, spaced at min_width + min_spacing pitch. This guarantees width and spacing rules by construction. Three merging strategies (pixel-rects, row-merge, greedy-merge) trade off between polygon count and simplicity.

Stage 3 - GDSII Output. Polygons are written as GdsBoundary elements on the correct top-metal layer via the gds21 crate. Supports both standalone GDS files and merging into existing chip layouts (with hierarchy flattening and exclusion zones).

Supported PDKs

Adding a new PDK takes about 30 lines of TOML:

[pdk]
name = "my_process"
node_nm = 65
db_units_per_um = 1000

[artwork_layer]
name = "met9"
gds_layer = 145
gds_datatype = 0

[drc]
min_width = 0.4
min_spacing = 0.4

[grid]
manufacturing_grid_um = 0.001

fabbula generate -i logo.png -o logo.gds -p my_process.toml

Prompt Guide

The best chip art starts with the right AI prompt. Since top-metal artwork is monochrome (metal or no metal), you want images with hard black/white contrast and no gradients.

Prompt template for ChatGPT / DALL-E:

Create a black and white stencil design of [your subject].
Pure black shapes on white background, no gradients, no gray tones.
Style: linocut print / woodcut illustration.
Bold clean shapes suitable for metal etching.
Square format, 1024x1024.

Styles that vectorize well: linocut, woodcut, stencil art, silhouette, paper cutout, Japanese mon, heraldic crest, tribal art, art deco geometric, pixel art.

Styles to avoid: photorealistic, watercolor, pencil sketch, anything with gradients or soft edges.

Inspiration / Comparison

fabbula was born from a simple idea: reimplement image-to-GDSII artwork generation in Rust - as a single, self-contained binary with zero runtime dependencies. The chip art community has produced excellent work over the years, and fabbula builds on that foundation.

Prior art

Several open-source tools tackle the image-to-GDSII problem. Each one contributed something valuable to the space:

• ArtistIC (PULP Platform, 2025) - The most complete existing pipeline. Its tetromino-based polygon generation produces genuinely DRC-clean artwork by flowing shapes around existing top-metal structures. Also includes gigapixel-scale tiled rendering via KLayout and DEF-based annotation. Python, requires KLayout + ImageMagick + Potrace. IHP SG13G2 focused.
• logo-to-gds2 (Matt Venn, ~2020) - Converts PNG/SVG to GDS2 + LEF for top-metal artwork, built for the Zero to ASIC / SKY130 / OpenLane / Caravel ecosystem. Python + Magic VLSI. No automatic DRC compliance.
• chip_art (jazvw) - Maps grayscale pixel values to different metal layers (metals 1-4) for multi-layer artwork. Python + Magic VLSI + Docker. SKY130 focused.
• png2gds (ralight) - Lightweight C tool mapping indexed-palette PNG colors to GDS layers. One square polygon per pixel. Designed to make adding logos to chip designs straightforward.
• svg2GDS (andestro) - Converts SVG path objects directly to GDSII boundaries. Python.
• KLayout image-to-GDS scripts - Ruby and Python macros by Matthias Koefferlein and others for converting images to GDS rectangles inside KLayout.

There are also several other converters (gdsGEN, image2gds, picture-to-gds, KLayout-PyMacros) and a curated list of GDSII tools at GDSII-Links.

Where fabbula fits

All existing tools are Python or C, most require external dependencies (Magic VLSI, KLayout, ImageMagick, Docker), and none except ArtistIC address DRC compliance automatically. fabbula's contribution is bringing this to Rust: a single cargo install, no runtime dependencies, with DRC-clean output by construction via grid-snapped polygon sizing.

Performance

fabbula is designed to be fast enough that artwork generation never becomes a bottleneck in your tapeout flow - even at large image sizes. All benchmarks run on a single machine using cargo bench (criterion).

Polygon generation

Bitmap-to-rectangle conversion at ~80% metal density (matching typical PDK density targets):

DRC validation

Full DRC check (min width, max width, min spacing, wide-metal spacing, min area, density) on clean rect grids:

What makes it fast

• Packed bitset bitmap - Vec<u64> instead of Vec<bool> cuts memory 8x, and count_ones() makes density computation nearly free
• Parallel DRC - width/area and spacing checks run across cores via rayon, giving ~58% speedup on multi-core machines
• R-tree spatial index - spacing checks are O(n log n) instead of O(n^2), making 100k-rect layouts practical
• Streaming I/O - HTML/SVG previews write directly through a BufWriter instead of building multi-MB intermediate strings

Roadmap

• Multi-PDK configuration system
• Bitmap → polygon generation with DRC-aware sizing
• Three polygon merging strategies
• GDSII read/write/merge
• Built-in DRC validation
• SVG preview output
• Built-in vtracer vectorization (PNG → SVG → GDS in one binary)
• usvg-based SVG path import (hand-drawn vector art)
• Exclusion zones (avoid existing top-metal structures)
• Density-aware artwork generation
• LEF output for OpenLane/OpenROAD integration
• Grayscale dithering for multi-density artwork
• OASIS output support
• WASM build for browser-based preview

Contributing

Contributions are welcome. Whether it's a new PDK config, a bug fix, a better polygon merging algorithm, or prompt templates that produce great AI art - open a PR.

See CONTRIBUTING.md for guidelines.

Acknowledgments

fabbula builds on excellent open-source work:

• gds21 / Layout21 - Rust GDSII library by Dan Fritchman
• ArtistIC - PULP Platform's pioneering work on DRC-aware ASIC artwork tooling
• logo-to-gds2 - Matt Venn's original image-to-GDS tool for the Zero to ASIC community
• The open-source PDK community: SkyWater, IHP, GlobalFoundries

With inspiration from the Integrated Information Processing (IIS) group at ETH Zurich and the PULP Platform open-source ecosystem.

License

Licensed under the Apache License, Version 2.0 - see LICENSE.

Every chip tells a story. Make yours visible.

⭐ Star this repo if you believe chip art deserves better tooling.