extract_rust_hdl_interface 0.1.0

Extracts the information needed for a rust-hdl module from a verilog module
Documentation 
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# generate_rust_hdl_module
This crate provides a `extract_rust_hdl_interface` function that extracts all the info you need to generate a rust-hdl module from a Verilog module.

The function does not actually generate code it just extracts the interface. It is mainly meant be used through the [`wrap_verilog!`](https://docs.rs/proc-macro-error/latest/wrap_verilog_in_rust_hdl_macro/) macro.

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