#[repr(C)]pub struct RegisterBlock {Show 36 fields
pub spi_cmd: Reg<SPI_CMD_SPEC>,
pub spi_addr: Reg<SPI_ADDR_SPEC>,
pub spi_ctrl: Reg<SPI_CTRL_SPEC>,
pub spi_ctrl1: Reg<SPI_CTRL1_SPEC>,
pub spi_rd_status: Reg<SPI_RD_STATUS_SPEC>,
pub spi_ctrl2: Reg<SPI_CTRL2_SPEC>,
pub spi_clock: Reg<SPI_CLOCK_SPEC>,
pub spi_user: Reg<SPI_USER_SPEC>,
pub spi_user1: Reg<SPI_USER1_SPEC>,
pub spi_user2: Reg<SPI_USER2_SPEC>,
pub spi_wr_status: Reg<SPI_WR_STATUS_SPEC>,
pub spi_pin: Reg<SPI_PIN_SPEC>,
pub spi_slave: Reg<SPI_SLAVE_SPEC>,
pub spi_slave1: Reg<SPI_SLAVE1_SPEC>,
pub spi_slave2: Reg<SPI_SLAVE2_SPEC>,
pub spi_slave3: Reg<SPI_SLAVE3_SPEC>,
pub spi_w0: Reg<SPI_W0_SPEC>,
pub spi_w1: Reg<SPI_W1_SPEC>,
pub spi_w2: Reg<SPI_W2_SPEC>,
pub spi_w3: Reg<SPI_W3_SPEC>,
pub spi_w4: Reg<SPI_W4_SPEC>,
pub spi_w5: Reg<SPI_W5_SPEC>,
pub spi_w6: Reg<SPI_W6_SPEC>,
pub spi_w7: Reg<SPI_W7_SPEC>,
pub spi_w8: Reg<SPI_W8_SPEC>,
pub spi_w9: Reg<SPI_W9_SPEC>,
pub spi_w10: Reg<SPI_W10_SPEC>,
pub spi_w11: Reg<SPI_W11_SPEC>,
pub spi_w12: Reg<SPI_W12_SPEC>,
pub spi_w13: Reg<SPI_W13_SPEC>,
pub spi_w14: Reg<SPI_W14_SPEC>,
pub spi_w15: Reg<SPI_W15_SPEC>,
pub spi_ext0: Reg<SPI_EXT0_SPEC>,
pub spi_ext1: Reg<SPI_EXT1_SPEC>,
pub spi_ext2: Reg<SPI_EXT2_SPEC>,
pub spi_ext3: Reg<SPI_EXT3_SPEC>,
/* private fields */
}Expand description
Register block
Fields§
§spi_cmd: Reg<SPI_CMD_SPEC>0x00 - In the master mode, it is the start bit of a single operation. Self-clear by hardware
spi_addr: Reg<SPI_ADDR_SPEC>0x04 - In the master mode, it is the value of address in “address” phase.
spi_ctrl: Reg<SPI_CTRL_SPEC>0x08 - SPI_CTRL
spi_ctrl1: Reg<SPI_CTRL1_SPEC>0x0c -
spi_rd_status: Reg<SPI_RD_STATUS_SPEC>0x10 - In the slave mode, this register are the status register for the master to read out.
spi_ctrl2: Reg<SPI_CTRL2_SPEC>0x14 - spi_cs signal is delayed by 80MHz clock cycles
spi_clock: Reg<SPI_CLOCK_SPEC>0x18 - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.
spi_user: Reg<SPI_USER_SPEC>0x1c - This bit enable the “command” phase of an operation.
spi_user1: Reg<SPI_USER1_SPEC>0x20 - The length in bits of “address” phase. The register value shall be (bit_num-1)
spi_user2: Reg<SPI_USER2_SPEC>0x24 - The length in bits of “command” phase. The register value shall be (bit_num-1)
spi_wr_status: Reg<SPI_WR_STATUS_SPEC>0x28 - In the slave mode, this register are the status register for the master to write into.
spi_pin: Reg<SPI_PIN_SPEC>0x2c - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin
spi_slave: Reg<SPI_SLAVE_SPEC>0x30 - It is the synchronous reset signal of the module. This bit is self-cleared by hardware.
spi_slave1: Reg<SPI_SLAVE1_SPEC>0x34 - In the slave mode, it is the length in bits for “write-status” and “read-status” operations. The register valueshall be (bit_num-1)
spi_slave2: Reg<SPI_SLAVE2_SPEC>0x38 - In the slave mode, it is the length in spi_clk cycles “dummy” phase for “write-buffer” operations. The registervalue shall be (cycle_num-1)
spi_slave3: Reg<SPI_SLAVE3_SPEC>0x3c - In slave mode, it is the value of “write-status” command
spi_w0: Reg<SPI_W0_SPEC>0x40 - the data inside the buffer of the SPI module, word 0
spi_w1: Reg<SPI_W1_SPEC>0x44 - the data inside the buffer of the SPI module, word 1
spi_w2: Reg<SPI_W2_SPEC>0x48 - the data inside the buffer of the SPI module, word 2
spi_w3: Reg<SPI_W3_SPEC>0x4c - the data inside the buffer of the SPI module, word 3
spi_w4: Reg<SPI_W4_SPEC>0x50 - the data inside the buffer of the SPI module, word 4
spi_w5: Reg<SPI_W5_SPEC>0x54 - the data inside the buffer of the SPI module, word 5
spi_w6: Reg<SPI_W6_SPEC>0x58 - the data inside the buffer of the SPI module, word 6
spi_w7: Reg<SPI_W7_SPEC>0x5c - the data inside the buffer of the SPI module, word 7
spi_w8: Reg<SPI_W8_SPEC>0x60 - the data inside the buffer of the SPI module, word 8
spi_w9: Reg<SPI_W9_SPEC>0x64 - the data inside the buffer of the SPI module, word 9
spi_w10: Reg<SPI_W10_SPEC>0x68 - the data inside the buffer of the SPI module, word 10
spi_w11: Reg<SPI_W11_SPEC>0x6c - the data inside the buffer of the SPI module, word 11
spi_w12: Reg<SPI_W12_SPEC>0x70 - the data inside the buffer of the SPI module, word 12
spi_w13: Reg<SPI_W13_SPEC>0x74 - the data inside the buffer of the SPI module, word 13
spi_w14: Reg<SPI_W14_SPEC>0x78 - the data inside the buffer of the SPI module, word 14
spi_w15: Reg<SPI_W15_SPEC>0x7c - the data inside the buffer of the SPI module, word 15
spi_ext0: Reg<SPI_EXT0_SPEC>0xf0 -
spi_ext1: Reg<SPI_EXT1_SPEC>0xf4 -
spi_ext2: Reg<SPI_EXT2_SPEC>0xf8 -
spi_ext3: Reg<SPI_EXT3_SPEC>0xfc - This register is for two SPI masters to share the same cs, clock and data signals.