pub struct R(/* private fields */);Expand description
Register SPI_CTRL2 reader
Implementations§
Source§impl R
impl R
Sourcepub fn spi_cs_delay_num(&self) -> SPI_CS_DELAY_NUM_R
pub fn spi_cs_delay_num(&self) -> SPI_CS_DELAY_NUM_R
Bits 28:31 - spi_cs signal is delayed by 80MHz clock cycles
Sourcepub fn spi_cs_delay_mode(&self) -> SPI_CS_DELAY_MODE_R
pub fn spi_cs_delay_mode(&self) -> SPI_CS_DELAY_MODE_R
Bits 26:27 - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle
Sourcepub fn spi_mosi_delay_num(&self) -> SPI_MOSI_DELAY_NUM_R
pub fn spi_mosi_delay_num(&self) -> SPI_MOSI_DELAY_NUM_R
Bits 23:25 - MOSI signals are delayed by 80MHz clock cycles
Sourcepub fn spi_mosi_delay_mode(&self) -> SPI_MOSI_DELAY_MODE_R
pub fn spi_mosi_delay_mode(&self) -> SPI_MOSI_DELAY_MODE_R
Bits 21:22 - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle
Sourcepub fn spi_miso_delay_num(&self) -> SPI_MISO_DELAY_NUM_R
pub fn spi_miso_delay_num(&self) -> SPI_MISO_DELAY_NUM_R
Bits 18:20 - MISO signals are delayed by 80MHz clock cycles
Sourcepub fn spi_miso_delay_mode(&self) -> SPI_MISO_DELAY_MODE_R
pub fn spi_miso_delay_mode(&self) -> SPI_MISO_DELAY_MODE_R
Bits 16:17 - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle
Methods from Deref<Target = R<SPI_CTRL2_SPEC>>§
Trait Implementations§
Auto Trait Implementations§
impl Freeze for R
impl RefUnwindSafe for R
impl Send for R
impl Sync for R
impl Unpin for R
impl UnwindSafe for R
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more