#[doc = "Register `UART_INT_CLR` writer"]
pub struct W(crate::W<UART_INT_CLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<UART_INT_CLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<UART_INT_CLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<UART_INT_CLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `rxfifo_tout_int_clr` writer - Set this bit to clear the rx time-out interrupt"]
pub struct RXFIFO_TOUT_INT_CLR_W<'a> {
w: &'a mut W,
}
impl<'a> RXFIFO_TOUT_INT_CLR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(1 << 8)) | ((value as u32 & 1) << 8);
self.w
}
}
#[doc = "Field `brk_det_int_clr` writer - Set this bit to clear the rx byte start interrupt"]
pub struct BRK_DET_INT_CLR_W<'a> {
w: &'a mut W,
}
impl<'a> BRK_DET_INT_CLR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(1 << 7)) | ((value as u32 & 1) << 7);
self.w
}
}
#[doc = "Field `cts_chg_int_clr` writer - Set this bit to clear the CTS changing interrupt"]
pub struct CTS_CHG_INT_CLR_W<'a> {
w: &'a mut W,
}
impl<'a> CTS_CHG_INT_CLR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(1 << 6)) | ((value as u32 & 1) << 6);
self.w
}
}
#[doc = "Field `dsr_chg_int_clr` writer - Set this bit to clear the DSR changing interrupt"]
pub struct DSR_CHG_INT_CLR_W<'a> {
w: &'a mut W,
}
impl<'a> DSR_CHG_INT_CLR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(1 << 5)) | ((value as u32 & 1) << 5);
self.w
}
}
#[doc = "Field `rxfifo_ovf_int_clr` writer - Set this bit to clear the rx fifo over-flow interrupt"]
pub struct RXFIFO_OVF_INT_CLR_W<'a> {
w: &'a mut W,
}
impl<'a> RXFIFO_OVF_INT_CLR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(1 << 4)) | ((value as u32 & 1) << 4);
self.w
}
}
#[doc = "Field `frm_err_int_clr` writer - Set this bit to clear other rx error interrupt"]
pub struct FRM_ERR_INT_CLR_W<'a> {
w: &'a mut W,
}
impl<'a> FRM_ERR_INT_CLR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(1 << 3)) | ((value as u32 & 1) << 3);
self.w
}
}
#[doc = "Field `parity_err_int_clr` writer - Set this bit to clear the parity error interrupt"]
pub struct PARITY_ERR_INT_CLR_W<'a> {
w: &'a mut W,
}
impl<'a> PARITY_ERR_INT_CLR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(1 << 2)) | ((value as u32 & 1) << 2);
self.w
}
}
#[doc = "Field `txfifo_empty_int_clr` writer - Set this bit to clear the tx fifo empty interrupt"]
pub struct TXFIFO_EMPTY_INT_CLR_W<'a> {
w: &'a mut W,
}
impl<'a> TXFIFO_EMPTY_INT_CLR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(1 << 1)) | ((value as u32 & 1) << 1);
self.w
}
}
#[doc = "Field `rxfifo_full_int_clr` writer - Set this bit to clear the rx fifo full interrupt"]
pub struct RXFIFO_FULL_INT_CLR_W<'a> {
w: &'a mut W,
}
impl<'a> RXFIFO_FULL_INT_CLR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !1) | (value as u32 & 1);
self.w
}
}
impl W {
#[doc = "Bit 8 - Set this bit to clear the rx time-out interrupt"]
#[inline(always)]
pub fn rxfifo_tout_int_clr(&mut self) -> RXFIFO_TOUT_INT_CLR_W {
RXFIFO_TOUT_INT_CLR_W { w: self }
}
#[doc = "Bit 7 - Set this bit to clear the rx byte start interrupt"]
#[inline(always)]
pub fn brk_det_int_clr(&mut self) -> BRK_DET_INT_CLR_W {
BRK_DET_INT_CLR_W { w: self }
}
#[doc = "Bit 6 - Set this bit to clear the CTS changing interrupt"]
#[inline(always)]
pub fn cts_chg_int_clr(&mut self) -> CTS_CHG_INT_CLR_W {
CTS_CHG_INT_CLR_W { w: self }
}
#[doc = "Bit 5 - Set this bit to clear the DSR changing interrupt"]
#[inline(always)]
pub fn dsr_chg_int_clr(&mut self) -> DSR_CHG_INT_CLR_W {
DSR_CHG_INT_CLR_W { w: self }
}
#[doc = "Bit 4 - Set this bit to clear the rx fifo over-flow interrupt"]
#[inline(always)]
pub fn rxfifo_ovf_int_clr(&mut self) -> RXFIFO_OVF_INT_CLR_W {
RXFIFO_OVF_INT_CLR_W { w: self }
}
#[doc = "Bit 3 - Set this bit to clear other rx error interrupt"]
#[inline(always)]
pub fn frm_err_int_clr(&mut self) -> FRM_ERR_INT_CLR_W {
FRM_ERR_INT_CLR_W { w: self }
}
#[doc = "Bit 2 - Set this bit to clear the parity error interrupt"]
#[inline(always)]
pub fn parity_err_int_clr(&mut self) -> PARITY_ERR_INT_CLR_W {
PARITY_ERR_INT_CLR_W { w: self }
}
#[doc = "Bit 1 - Set this bit to clear the tx fifo empty interrupt"]
#[inline(always)]
pub fn txfifo_empty_int_clr(&mut self) -> TXFIFO_EMPTY_INT_CLR_W {
TXFIFO_EMPTY_INT_CLR_W { w: self }
}
#[doc = "Bit 0 - Set this bit to clear the rx fifo full interrupt"]
#[inline(always)]
pub fn rxfifo_full_int_clr(&mut self) -> RXFIFO_FULL_INT_CLR_W {
RXFIFO_FULL_INT_CLR_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART INTERRUPT CLEAR REGISTER\n\nThis register you can [`write_with_zero`]
(crate::generic::Reg::write_with_zero), [`reset`]
(crate::generic::Reg::reset), [`write`]
(crate::generic::Reg::write). See [API]
(https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_int_clr]
(index.html) module"]
pub struct UART_INT_CLR_SPEC;
impl crate::RegisterSpec for UART_INT_CLR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [uart_int_clr::W]
(W) writer structure"]
impl crate::Writable for UART_INT_CLR_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets UART_INT_CLR to value 0"]
impl crate::Resettable for UART_INT_CLR_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}