esp32s3/systimer/
int_raw.rs

1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Register `INT_RAW` writer"]
4pub type W = crate::W<INT_RAW_SPEC>;
5#[doc = "Field `TARGET(0-2)` reader - interupt%s raw"]
6pub type TARGET_R = crate::BitReader;
7#[doc = "Field `TARGET(0-2)` writer - interupt%s raw"]
8pub type TARGET_W<'a, REG> = crate::BitWriter<'a, REG>;
9impl R {
10    #[doc = "interupt(0-2) raw"]
11    #[doc = ""]
12    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TARGET0` field.</div>"]
13    #[inline(always)]
14    pub fn target(&self, n: u8) -> TARGET_R {
15        #[allow(clippy::no_effect)]
16        [(); 3][n as usize];
17        TARGET_R::new(((self.bits >> n) & 1) != 0)
18    }
19    #[doc = "Iterator for array of:"]
20    #[doc = "interupt(0-2) raw"]
21    #[inline(always)]
22    pub fn target_iter(&self) -> impl Iterator<Item = TARGET_R> + '_ {
23        (0..3).map(move |n| TARGET_R::new(((self.bits >> n) & 1) != 0))
24    }
25    #[doc = "Bit 0 - interupt0 raw"]
26    #[inline(always)]
27    pub fn target0(&self) -> TARGET_R {
28        TARGET_R::new((self.bits & 1) != 0)
29    }
30    #[doc = "Bit 1 - interupt1 raw"]
31    #[inline(always)]
32    pub fn target1(&self) -> TARGET_R {
33        TARGET_R::new(((self.bits >> 1) & 1) != 0)
34    }
35    #[doc = "Bit 2 - interupt2 raw"]
36    #[inline(always)]
37    pub fn target2(&self) -> TARGET_R {
38        TARGET_R::new(((self.bits >> 2) & 1) != 0)
39    }
40}
41#[cfg(feature = "impl-register-debug")]
42impl core::fmt::Debug for R {
43    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
44        f.debug_struct("INT_RAW")
45            .field("target0", &self.target0())
46            .field("target1", &self.target1())
47            .field("target2", &self.target2())
48            .finish()
49    }
50}
51impl W {
52    #[doc = "interupt(0-2) raw"]
53    #[doc = ""]
54    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TARGET0` field.</div>"]
55    #[inline(always)]
56    pub fn target(&mut self, n: u8) -> TARGET_W<INT_RAW_SPEC> {
57        #[allow(clippy::no_effect)]
58        [(); 3][n as usize];
59        TARGET_W::new(self, n)
60    }
61    #[doc = "Bit 0 - interupt0 raw"]
62    #[inline(always)]
63    pub fn target0(&mut self) -> TARGET_W<INT_RAW_SPEC> {
64        TARGET_W::new(self, 0)
65    }
66    #[doc = "Bit 1 - interupt1 raw"]
67    #[inline(always)]
68    pub fn target1(&mut self) -> TARGET_W<INT_RAW_SPEC> {
69        TARGET_W::new(self, 1)
70    }
71    #[doc = "Bit 2 - interupt2 raw"]
72    #[inline(always)]
73    pub fn target2(&mut self) -> TARGET_W<INT_RAW_SPEC> {
74        TARGET_W::new(self, 2)
75    }
76}
77#[doc = "systimer interrupt raw register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
78pub struct INT_RAW_SPEC;
79impl crate::RegisterSpec for INT_RAW_SPEC {
80    type Ux = u32;
81}
82#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
83impl crate::Readable for INT_RAW_SPEC {}
84#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"]
85impl crate::Writable for INT_RAW_SPEC {
86    type Safety = crate::Unsafe;
87    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
89}
90#[doc = "`reset()` method sets INT_RAW to value 0"]
91impl crate::Resettable for INT_RAW_SPEC {
92    const RESET_VALUE: u32 = 0;
93}
esp32s3/systimer/int_raw.rs

esp32s3/systimer/
int_raw.rs
