1#[doc = "Register `DMA_INT_RAW` reader"]
2pub type R = crate::R<DMA_INT_RAW_SPEC>;
3#[doc = "Register `DMA_INT_RAW` writer"]
4pub type W = crate::W<DMA_INT_RAW_SPEC>;
5#[doc = "Field `DMA_INFIFO_FULL_ERR` reader - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."]
6pub type DMA_INFIFO_FULL_ERR_R = crate::BitReader;
7#[doc = "Field `DMA_INFIFO_FULL_ERR` writer - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."]
8pub type DMA_INFIFO_FULL_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DMA_OUTFIFO_EMPTY_ERR` reader - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others."]
10pub type DMA_OUTFIFO_EMPTY_ERR_R = crate::BitReader;
11#[doc = "Field `DMA_OUTFIFO_EMPTY_ERR` writer - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others."]
12pub type DMA_OUTFIFO_EMPTY_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SLV_EX_QPI` reader - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others."]
14pub type SLV_EX_QPI_R = crate::BitReader;
15#[doc = "Field `SLV_EX_QPI` writer - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others."]
16pub type SLV_EX_QPI_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SLV_EN_QPI` reader - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others."]
18pub type SLV_EN_QPI_R = crate::BitReader;
19#[doc = "Field `SLV_EN_QPI` writer - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others."]
20pub type SLV_EN_QPI_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SLV_CMD7` reader - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others."]
22pub type SLV_CMD7_R = crate::BitReader;
23#[doc = "Field `SLV_CMD7` writer - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others."]
24pub type SLV_CMD7_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SLV_CMD8` reader - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others."]
26pub type SLV_CMD8_R = crate::BitReader;
27#[doc = "Field `SLV_CMD8` writer - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others."]
28pub type SLV_CMD8_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SLV_CMD9` reader - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others."]
30pub type SLV_CMD9_R = crate::BitReader;
31#[doc = "Field `SLV_CMD9` writer - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others."]
32pub type SLV_CMD9_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SLV_CMDA` reader - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others."]
34pub type SLV_CMDA_R = crate::BitReader;
35#[doc = "Field `SLV_CMDA` writer - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others."]
36pub type SLV_CMDA_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SLV_RD_DMA_DONE` reader - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others."]
38pub type SLV_RD_DMA_DONE_R = crate::BitReader;
39#[doc = "Field `SLV_RD_DMA_DONE` writer - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others."]
40pub type SLV_RD_DMA_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SLV_WR_DMA_DONE` reader - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others."]
42pub type SLV_WR_DMA_DONE_R = crate::BitReader;
43#[doc = "Field `SLV_WR_DMA_DONE` writer - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others."]
44pub type SLV_WR_DMA_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SLV_RD_BUF_DONE` reader - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others."]
46pub type SLV_RD_BUF_DONE_R = crate::BitReader;
47#[doc = "Field `SLV_RD_BUF_DONE` writer - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others."]
48pub type SLV_RD_BUF_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `SLV_WR_BUF_DONE` reader - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others."]
50pub type SLV_WR_BUF_DONE_R = crate::BitReader;
51#[doc = "Field `SLV_WR_BUF_DONE` writer - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others."]
52pub type SLV_WR_BUF_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `TRANS_DONE` reader - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others."]
54pub type TRANS_DONE_R = crate::BitReader;
55#[doc = "Field `TRANS_DONE` writer - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others."]
56pub type TRANS_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `DMA_SEG_TRANS_DONE` reader - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred."]
58pub type DMA_SEG_TRANS_DONE_R = crate::BitReader;
59#[doc = "Field `DMA_SEG_TRANS_DONE` writer - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred."]
60pub type DMA_SEG_TRANS_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `SEG_MAGIC_ERR` reader - The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others."]
62pub type SEG_MAGIC_ERR_R = crate::BitReader;
63#[doc = "Field `SEG_MAGIC_ERR` writer - The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others."]
64pub type SEG_MAGIC_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `SLV_BUF_ADDR_ERR` reader - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others."]
66pub type SLV_BUF_ADDR_ERR_R = crate::BitReader;
67#[doc = "Field `SLV_BUF_ADDR_ERR` writer - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others."]
68pub type SLV_BUF_ADDR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `SLV_CMD_ERR` reader - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others."]
70pub type SLV_CMD_ERR_R = crate::BitReader;
71#[doc = "Field `SLV_CMD_ERR` writer - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others."]
72pub type SLV_CMD_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `MST_RX_AFIFO_WFULL_ERR` reader - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others."]
74pub type MST_RX_AFIFO_WFULL_ERR_R = crate::BitReader;
75#[doc = "Field `MST_RX_AFIFO_WFULL_ERR` writer - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others."]
76pub type MST_RX_AFIFO_WFULL_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `MST_TX_AFIFO_REMPTY_ERR` reader - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others."]
78pub type MST_TX_AFIFO_REMPTY_ERR_R = crate::BitReader;
79#[doc = "Field `MST_TX_AFIFO_REMPTY_ERR` writer - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others."]
80pub type MST_TX_AFIFO_REMPTY_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `APP2` reader - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software."]
82pub type APP2_R = crate::BitReader;
83#[doc = "Field `APP2` writer - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software."]
84pub type APP2_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `APP1` reader - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software."]
86pub type APP1_R = crate::BitReader;
87#[doc = "Field `APP1` writer - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software."]
88pub type APP1_W<'a, REG> = crate::BitWriter<'a, REG>;
89impl R {
90 #[doc = "Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."]
91 #[inline(always)]
92 pub fn dma_infifo_full_err(&self) -> DMA_INFIFO_FULL_ERR_R {
93 DMA_INFIFO_FULL_ERR_R::new((self.bits & 1) != 0)
94 }
95 #[doc = "Bit 1 - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others."]
96 #[inline(always)]
97 pub fn dma_outfifo_empty_err(&self) -> DMA_OUTFIFO_EMPTY_ERR_R {
98 DMA_OUTFIFO_EMPTY_ERR_R::new(((self.bits >> 1) & 1) != 0)
99 }
100 #[doc = "Bit 2 - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others."]
101 #[inline(always)]
102 pub fn slv_ex_qpi(&self) -> SLV_EX_QPI_R {
103 SLV_EX_QPI_R::new(((self.bits >> 2) & 1) != 0)
104 }
105 #[doc = "Bit 3 - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others."]
106 #[inline(always)]
107 pub fn slv_en_qpi(&self) -> SLV_EN_QPI_R {
108 SLV_EN_QPI_R::new(((self.bits >> 3) & 1) != 0)
109 }
110 #[doc = "Bit 4 - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others."]
111 #[inline(always)]
112 pub fn slv_cmd7(&self) -> SLV_CMD7_R {
113 SLV_CMD7_R::new(((self.bits >> 4) & 1) != 0)
114 }
115 #[doc = "Bit 5 - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others."]
116 #[inline(always)]
117 pub fn slv_cmd8(&self) -> SLV_CMD8_R {
118 SLV_CMD8_R::new(((self.bits >> 5) & 1) != 0)
119 }
120 #[doc = "Bit 6 - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others."]
121 #[inline(always)]
122 pub fn slv_cmd9(&self) -> SLV_CMD9_R {
123 SLV_CMD9_R::new(((self.bits >> 6) & 1) != 0)
124 }
125 #[doc = "Bit 7 - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others."]
126 #[inline(always)]
127 pub fn slv_cmda(&self) -> SLV_CMDA_R {
128 SLV_CMDA_R::new(((self.bits >> 7) & 1) != 0)
129 }
130 #[doc = "Bit 8 - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others."]
131 #[inline(always)]
132 pub fn slv_rd_dma_done(&self) -> SLV_RD_DMA_DONE_R {
133 SLV_RD_DMA_DONE_R::new(((self.bits >> 8) & 1) != 0)
134 }
135 #[doc = "Bit 9 - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others."]
136 #[inline(always)]
137 pub fn slv_wr_dma_done(&self) -> SLV_WR_DMA_DONE_R {
138 SLV_WR_DMA_DONE_R::new(((self.bits >> 9) & 1) != 0)
139 }
140 #[doc = "Bit 10 - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others."]
141 #[inline(always)]
142 pub fn slv_rd_buf_done(&self) -> SLV_RD_BUF_DONE_R {
143 SLV_RD_BUF_DONE_R::new(((self.bits >> 10) & 1) != 0)
144 }
145 #[doc = "Bit 11 - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others."]
146 #[inline(always)]
147 pub fn slv_wr_buf_done(&self) -> SLV_WR_BUF_DONE_R {
148 SLV_WR_BUF_DONE_R::new(((self.bits >> 11) & 1) != 0)
149 }
150 #[doc = "Bit 12 - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others."]
151 #[inline(always)]
152 pub fn trans_done(&self) -> TRANS_DONE_R {
153 TRANS_DONE_R::new(((self.bits >> 12) & 1) != 0)
154 }
155 #[doc = "Bit 13 - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred."]
156 #[inline(always)]
157 pub fn dma_seg_trans_done(&self) -> DMA_SEG_TRANS_DONE_R {
158 DMA_SEG_TRANS_DONE_R::new(((self.bits >> 13) & 1) != 0)
159 }
160 #[doc = "Bit 14 - The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others."]
161 #[inline(always)]
162 pub fn seg_magic_err(&self) -> SEG_MAGIC_ERR_R {
163 SEG_MAGIC_ERR_R::new(((self.bits >> 14) & 1) != 0)
164 }
165 #[doc = "Bit 15 - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others."]
166 #[inline(always)]
167 pub fn slv_buf_addr_err(&self) -> SLV_BUF_ADDR_ERR_R {
168 SLV_BUF_ADDR_ERR_R::new(((self.bits >> 15) & 1) != 0)
169 }
170 #[doc = "Bit 16 - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others."]
171 #[inline(always)]
172 pub fn slv_cmd_err(&self) -> SLV_CMD_ERR_R {
173 SLV_CMD_ERR_R::new(((self.bits >> 16) & 1) != 0)
174 }
175 #[doc = "Bit 17 - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others."]
176 #[inline(always)]
177 pub fn mst_rx_afifo_wfull_err(&self) -> MST_RX_AFIFO_WFULL_ERR_R {
178 MST_RX_AFIFO_WFULL_ERR_R::new(((self.bits >> 17) & 1) != 0)
179 }
180 #[doc = "Bit 18 - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others."]
181 #[inline(always)]
182 pub fn mst_tx_afifo_rempty_err(&self) -> MST_TX_AFIFO_REMPTY_ERR_R {
183 MST_TX_AFIFO_REMPTY_ERR_R::new(((self.bits >> 18) & 1) != 0)
184 }
185 #[doc = "Bit 19 - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software."]
186 #[inline(always)]
187 pub fn app2(&self) -> APP2_R {
188 APP2_R::new(((self.bits >> 19) & 1) != 0)
189 }
190 #[doc = "Bit 20 - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software."]
191 #[inline(always)]
192 pub fn app1(&self) -> APP1_R {
193 APP1_R::new(((self.bits >> 20) & 1) != 0)
194 }
195}
196#[cfg(feature = "impl-register-debug")]
197impl core::fmt::Debug for R {
198 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
199 f.debug_struct("DMA_INT_RAW")
200 .field("dma_infifo_full_err", &self.dma_infifo_full_err())
201 .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
202 .field("slv_ex_qpi", &self.slv_ex_qpi())
203 .field("slv_en_qpi", &self.slv_en_qpi())
204 .field("slv_cmd7", &self.slv_cmd7())
205 .field("slv_cmd8", &self.slv_cmd8())
206 .field("slv_cmd9", &self.slv_cmd9())
207 .field("slv_cmda", &self.slv_cmda())
208 .field("slv_rd_dma_done", &self.slv_rd_dma_done())
209 .field("slv_wr_dma_done", &self.slv_wr_dma_done())
210 .field("slv_rd_buf_done", &self.slv_rd_buf_done())
211 .field("slv_wr_buf_done", &self.slv_wr_buf_done())
212 .field("trans_done", &self.trans_done())
213 .field("dma_seg_trans_done", &self.dma_seg_trans_done())
214 .field("seg_magic_err", &self.seg_magic_err())
215 .field("slv_buf_addr_err", &self.slv_buf_addr_err())
216 .field("slv_cmd_err", &self.slv_cmd_err())
217 .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
218 .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
219 .field("app2", &self.app2())
220 .field("app1", &self.app1())
221 .finish()
222 }
223}
224impl W {
225 #[doc = "Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."]
226 #[inline(always)]
227 pub fn dma_infifo_full_err(&mut self) -> DMA_INFIFO_FULL_ERR_W<DMA_INT_RAW_SPEC> {
228 DMA_INFIFO_FULL_ERR_W::new(self, 0)
229 }
230 #[doc = "Bit 1 - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others."]
231 #[inline(always)]
232 pub fn dma_outfifo_empty_err(&mut self) -> DMA_OUTFIFO_EMPTY_ERR_W<DMA_INT_RAW_SPEC> {
233 DMA_OUTFIFO_EMPTY_ERR_W::new(self, 1)
234 }
235 #[doc = "Bit 2 - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others."]
236 #[inline(always)]
237 pub fn slv_ex_qpi(&mut self) -> SLV_EX_QPI_W<DMA_INT_RAW_SPEC> {
238 SLV_EX_QPI_W::new(self, 2)
239 }
240 #[doc = "Bit 3 - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others."]
241 #[inline(always)]
242 pub fn slv_en_qpi(&mut self) -> SLV_EN_QPI_W<DMA_INT_RAW_SPEC> {
243 SLV_EN_QPI_W::new(self, 3)
244 }
245 #[doc = "Bit 4 - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others."]
246 #[inline(always)]
247 pub fn slv_cmd7(&mut self) -> SLV_CMD7_W<DMA_INT_RAW_SPEC> {
248 SLV_CMD7_W::new(self, 4)
249 }
250 #[doc = "Bit 5 - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others."]
251 #[inline(always)]
252 pub fn slv_cmd8(&mut self) -> SLV_CMD8_W<DMA_INT_RAW_SPEC> {
253 SLV_CMD8_W::new(self, 5)
254 }
255 #[doc = "Bit 6 - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others."]
256 #[inline(always)]
257 pub fn slv_cmd9(&mut self) -> SLV_CMD9_W<DMA_INT_RAW_SPEC> {
258 SLV_CMD9_W::new(self, 6)
259 }
260 #[doc = "Bit 7 - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others."]
261 #[inline(always)]
262 pub fn slv_cmda(&mut self) -> SLV_CMDA_W<DMA_INT_RAW_SPEC> {
263 SLV_CMDA_W::new(self, 7)
264 }
265 #[doc = "Bit 8 - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others."]
266 #[inline(always)]
267 pub fn slv_rd_dma_done(&mut self) -> SLV_RD_DMA_DONE_W<DMA_INT_RAW_SPEC> {
268 SLV_RD_DMA_DONE_W::new(self, 8)
269 }
270 #[doc = "Bit 9 - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others."]
271 #[inline(always)]
272 pub fn slv_wr_dma_done(&mut self) -> SLV_WR_DMA_DONE_W<DMA_INT_RAW_SPEC> {
273 SLV_WR_DMA_DONE_W::new(self, 9)
274 }
275 #[doc = "Bit 10 - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others."]
276 #[inline(always)]
277 pub fn slv_rd_buf_done(&mut self) -> SLV_RD_BUF_DONE_W<DMA_INT_RAW_SPEC> {
278 SLV_RD_BUF_DONE_W::new(self, 10)
279 }
280 #[doc = "Bit 11 - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others."]
281 #[inline(always)]
282 pub fn slv_wr_buf_done(&mut self) -> SLV_WR_BUF_DONE_W<DMA_INT_RAW_SPEC> {
283 SLV_WR_BUF_DONE_W::new(self, 11)
284 }
285 #[doc = "Bit 12 - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others."]
286 #[inline(always)]
287 pub fn trans_done(&mut self) -> TRANS_DONE_W<DMA_INT_RAW_SPEC> {
288 TRANS_DONE_W::new(self, 12)
289 }
290 #[doc = "Bit 13 - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred."]
291 #[inline(always)]
292 pub fn dma_seg_trans_done(&mut self) -> DMA_SEG_TRANS_DONE_W<DMA_INT_RAW_SPEC> {
293 DMA_SEG_TRANS_DONE_W::new(self, 13)
294 }
295 #[doc = "Bit 14 - The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others."]
296 #[inline(always)]
297 pub fn seg_magic_err(&mut self) -> SEG_MAGIC_ERR_W<DMA_INT_RAW_SPEC> {
298 SEG_MAGIC_ERR_W::new(self, 14)
299 }
300 #[doc = "Bit 15 - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others."]
301 #[inline(always)]
302 pub fn slv_buf_addr_err(&mut self) -> SLV_BUF_ADDR_ERR_W<DMA_INT_RAW_SPEC> {
303 SLV_BUF_ADDR_ERR_W::new(self, 15)
304 }
305 #[doc = "Bit 16 - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others."]
306 #[inline(always)]
307 pub fn slv_cmd_err(&mut self) -> SLV_CMD_ERR_W<DMA_INT_RAW_SPEC> {
308 SLV_CMD_ERR_W::new(self, 16)
309 }
310 #[doc = "Bit 17 - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others."]
311 #[inline(always)]
312 pub fn mst_rx_afifo_wfull_err(&mut self) -> MST_RX_AFIFO_WFULL_ERR_W<DMA_INT_RAW_SPEC> {
313 MST_RX_AFIFO_WFULL_ERR_W::new(self, 17)
314 }
315 #[doc = "Bit 18 - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others."]
316 #[inline(always)]
317 pub fn mst_tx_afifo_rempty_err(&mut self) -> MST_TX_AFIFO_REMPTY_ERR_W<DMA_INT_RAW_SPEC> {
318 MST_TX_AFIFO_REMPTY_ERR_W::new(self, 18)
319 }
320 #[doc = "Bit 19 - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software."]
321 #[inline(always)]
322 pub fn app2(&mut self) -> APP2_W<DMA_INT_RAW_SPEC> {
323 APP2_W::new(self, 19)
324 }
325 #[doc = "Bit 20 - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software."]
326 #[inline(always)]
327 pub fn app1(&mut self) -> APP1_W<DMA_INT_RAW_SPEC> {
328 APP1_W::new(self, 20)
329 }
330}
331#[doc = "SPI interrupt raw register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
332pub struct DMA_INT_RAW_SPEC;
333impl crate::RegisterSpec for DMA_INT_RAW_SPEC {
334 type Ux = u32;
335}
336#[doc = "`read()` method returns [`dma_int_raw::R`](R) reader structure"]
337impl crate::Readable for DMA_INT_RAW_SPEC {}
338#[doc = "`write(|w| ..)` method takes [`dma_int_raw::W`](W) writer structure"]
339impl crate::Writable for DMA_INT_RAW_SPEC {
340 type Safety = crate::Unsafe;
341 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
342 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
343}
344#[doc = "`reset()` method sets DMA_INT_RAW to value 0"]
345impl crate::Resettable for DMA_INT_RAW_SPEC {
346 const RESET_VALUE: u32 = 0;
347}