esp32s3/rtc_i2c/
int_ena.rs

1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `SLAVE_TRAN_COMP` reader - enable slave transit complete interrupt"]
6pub type SLAVE_TRAN_COMP_R = crate::BitReader;
7#[doc = "Field `SLAVE_TRAN_COMP` writer - enable slave transit complete interrupt"]
8pub type SLAVE_TRAN_COMP_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ARBITRATION_LOST` reader - enable arbitration lost interrupt"]
10pub type ARBITRATION_LOST_R = crate::BitReader;
11#[doc = "Field `ARBITRATION_LOST` writer - enable arbitration lost interrupt"]
12pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MASTER_TRAN_COMP` reader - enable master transit complete interrupt"]
14pub type MASTER_TRAN_COMP_R = crate::BitReader;
15#[doc = "Field `MASTER_TRAN_COMP` writer - enable master transit complete interrupt"]
16pub type MASTER_TRAN_COMP_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TRANS_COMPLETE` reader - enable transit complete interrupt"]
18pub type TRANS_COMPLETE_R = crate::BitReader;
19#[doc = "Field `TRANS_COMPLETE` writer - enable transit complete interrupt"]
20pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TIME_OUT` reader - enable time out interrupt"]
22pub type TIME_OUT_R = crate::BitReader;
23#[doc = "Field `TIME_OUT` writer - enable time out interrupt"]
24pub type TIME_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ACK_ERR` reader - enable eack error interrupt"]
26pub type ACK_ERR_R = crate::BitReader;
27#[doc = "Field `ACK_ERR` writer - enable eack error interrupt"]
28pub type ACK_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `RX_DATA` reader - enable receive data interrupt"]
30pub type RX_DATA_R = crate::BitReader;
31#[doc = "Field `RX_DATA` writer - enable receive data interrupt"]
32pub type RX_DATA_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `TX_DATA` reader - enable transit data interrupt"]
34pub type TX_DATA_R = crate::BitReader;
35#[doc = "Field `TX_DATA` writer - enable transit data interrupt"]
36pub type TX_DATA_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `DETECT_START` reader - enable detect start interrupt"]
38pub type DETECT_START_R = crate::BitReader;
39#[doc = "Field `DETECT_START` writer - enable detect start interrupt"]
40pub type DETECT_START_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42    #[doc = "Bit 0 - enable slave transit complete interrupt"]
43    #[inline(always)]
44    pub fn slave_tran_comp(&self) -> SLAVE_TRAN_COMP_R {
45        SLAVE_TRAN_COMP_R::new((self.bits & 1) != 0)
46    }
47    #[doc = "Bit 1 - enable arbitration lost interrupt"]
48    #[inline(always)]
49    pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R {
50        ARBITRATION_LOST_R::new(((self.bits >> 1) & 1) != 0)
51    }
52    #[doc = "Bit 2 - enable master transit complete interrupt"]
53    #[inline(always)]
54    pub fn master_tran_comp(&self) -> MASTER_TRAN_COMP_R {
55        MASTER_TRAN_COMP_R::new(((self.bits >> 2) & 1) != 0)
56    }
57    #[doc = "Bit 3 - enable transit complete interrupt"]
58    #[inline(always)]
59    pub fn trans_complete(&self) -> TRANS_COMPLETE_R {
60        TRANS_COMPLETE_R::new(((self.bits >> 3) & 1) != 0)
61    }
62    #[doc = "Bit 4 - enable time out interrupt"]
63    #[inline(always)]
64    pub fn time_out(&self) -> TIME_OUT_R {
65        TIME_OUT_R::new(((self.bits >> 4) & 1) != 0)
66    }
67    #[doc = "Bit 5 - enable eack error interrupt"]
68    #[inline(always)]
69    pub fn ack_err(&self) -> ACK_ERR_R {
70        ACK_ERR_R::new(((self.bits >> 5) & 1) != 0)
71    }
72    #[doc = "Bit 6 - enable receive data interrupt"]
73    #[inline(always)]
74    pub fn rx_data(&self) -> RX_DATA_R {
75        RX_DATA_R::new(((self.bits >> 6) & 1) != 0)
76    }
77    #[doc = "Bit 7 - enable transit data interrupt"]
78    #[inline(always)]
79    pub fn tx_data(&self) -> TX_DATA_R {
80        TX_DATA_R::new(((self.bits >> 7) & 1) != 0)
81    }
82    #[doc = "Bit 8 - enable detect start interrupt"]
83    #[inline(always)]
84    pub fn detect_start(&self) -> DETECT_START_R {
85        DETECT_START_R::new(((self.bits >> 8) & 1) != 0)
86    }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91        f.debug_struct("INT_ENA")
92            .field("slave_tran_comp", &self.slave_tran_comp())
93            .field("arbitration_lost", &self.arbitration_lost())
94            .field("master_tran_comp", &self.master_tran_comp())
95            .field("trans_complete", &self.trans_complete())
96            .field("time_out", &self.time_out())
97            .field("ack_err", &self.ack_err())
98            .field("rx_data", &self.rx_data())
99            .field("tx_data", &self.tx_data())
100            .field("detect_start", &self.detect_start())
101            .finish()
102    }
103}
104impl W {
105    #[doc = "Bit 0 - enable slave transit complete interrupt"]
106    #[inline(always)]
107    pub fn slave_tran_comp(&mut self) -> SLAVE_TRAN_COMP_W<INT_ENA_SPEC> {
108        SLAVE_TRAN_COMP_W::new(self, 0)
109    }
110    #[doc = "Bit 1 - enable arbitration lost interrupt"]
111    #[inline(always)]
112    pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_ENA_SPEC> {
113        ARBITRATION_LOST_W::new(self, 1)
114    }
115    #[doc = "Bit 2 - enable master transit complete interrupt"]
116    #[inline(always)]
117    pub fn master_tran_comp(&mut self) -> MASTER_TRAN_COMP_W<INT_ENA_SPEC> {
118        MASTER_TRAN_COMP_W::new(self, 2)
119    }
120    #[doc = "Bit 3 - enable transit complete interrupt"]
121    #[inline(always)]
122    pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_ENA_SPEC> {
123        TRANS_COMPLETE_W::new(self, 3)
124    }
125    #[doc = "Bit 4 - enable time out interrupt"]
126    #[inline(always)]
127    pub fn time_out(&mut self) -> TIME_OUT_W<INT_ENA_SPEC> {
128        TIME_OUT_W::new(self, 4)
129    }
130    #[doc = "Bit 5 - enable eack error interrupt"]
131    #[inline(always)]
132    pub fn ack_err(&mut self) -> ACK_ERR_W<INT_ENA_SPEC> {
133        ACK_ERR_W::new(self, 5)
134    }
135    #[doc = "Bit 6 - enable receive data interrupt"]
136    #[inline(always)]
137    pub fn rx_data(&mut self) -> RX_DATA_W<INT_ENA_SPEC> {
138        RX_DATA_W::new(self, 6)
139    }
140    #[doc = "Bit 7 - enable transit data interrupt"]
141    #[inline(always)]
142    pub fn tx_data(&mut self) -> TX_DATA_W<INT_ENA_SPEC> {
143        TX_DATA_W::new(self, 7)
144    }
145    #[doc = "Bit 8 - enable detect start interrupt"]
146    #[inline(always)]
147    pub fn detect_start(&mut self) -> DETECT_START_W<INT_ENA_SPEC> {
148        DETECT_START_W::new(self, 8)
149    }
150}
151#[doc = "interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct INT_ENA_SPEC;
153impl crate::RegisterSpec for INT_ENA_SPEC {
154    type Ux = u32;
155}
156#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
157impl crate::Readable for INT_ENA_SPEC {}
158#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
159impl crate::Writable for INT_ENA_SPEC {
160    type Safety = crate::Unsafe;
161    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
162    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
163}
164#[doc = "`reset()` method sets INT_ENA to value 0"]
165impl crate::Resettable for INT_ENA_SPEC {
166    const RESET_VALUE: u32 = 0;
167}
esp32s3/rtc_i2c/int_ena.rs

esp32s3/rtc_i2c/
int_ena.rs
